1
2 samiam9512
Release 8.2.02i - xst I.33
2
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
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--> Parameter TMPDIR set to ./xst/projnav.tmp
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CPU : 0.00 / 0.23 s | Elapsed : 0.00 / 1.00 s
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--> Parameter xsthdpdir set to ./xst
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CPU : 0.00 / 0.23 s | Elapsed : 0.00 / 1.00 s
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--> Reading design: testbench.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Compilation
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3) Design Hierarchy Analysis
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4) HDL Analysis
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5) HDL Synthesis
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5.1) HDL Synthesis Report
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6) Advanced HDL Synthesis
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6.1) Advanced HDL Synthesis Report
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7) Low Level Synthesis
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8) Partition Report
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9) Final Report
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9.1) Device utilization summary
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9.2) TIMING REPORT
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26
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "testbench.prj"
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "testbench"
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Output Format : NGC
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Target Device : xc3s200-5-pq208
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---- Source Options
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Top Module Name : testbench
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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FSM Style : lut
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RAM Extraction : Yes
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RAM Style : Auto
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ROM Extraction : Yes
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Mux Style : Auto
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Decoder Extraction : YES
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Priority Encoder Extraction : YES
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Shift Register Extraction : YES
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Logical Shifter Extraction : YES
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XOR Collapsing : YES
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ROM Style : Auto
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Mux Extraction : YES
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Resource Sharing : YES
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Multiplier Style : auto
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Automatic Register Balancing : No
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---- Target Options
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Add IO Buffers : YES
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Global Maximum Fanout : 500
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Add Generic Clock Buffer(BUFG) : 8
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Register Duplication : YES
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Slice Packing : YES
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Pack IO Registers into IOBs : auto
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 1
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Keep Hierarchy : NO
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RTL Output : Yes
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Global Optimization : AllClockNets
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Write Timing Constraints : NO
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : maintain
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Slice Utilization Ratio : 100
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Slice Utilization Ratio Delta : 5
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---- Other Options
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lso : testbench.lso
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Read Cores : YES
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cross_clock_analysis : NO
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verilog2001 : YES
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safe_implementation : No
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Optimize Instantiated Primitives : NO
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use_clock_enable : Yes
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use_sync_set : Yes
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use_sync_reset : Yes
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=========================================================================
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling verilog file "cpu8080.v" in library work
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Module compiled
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Compiling verilog file "testbench.v" in library work
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Module compiled
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Module compiled
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Module compiled
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Module compiled
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Module compiled
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Module compiled
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No errors in compilation
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Analysis of file <"testbench.prj"> succeeded.
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111
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=========================================================================
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* Design Hierarchy Analysis *
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=========================================================================
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Building hierarchy successfully finished.
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=========================================================================
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* HDL Analysis *
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=========================================================================
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Analyzing top module .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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WARNING:Xst:905 - "testbench.v" line 229: The signals are missing in the sensitivity list of always block.
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Performing bidirectional port resolution...
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Synthesizing Unit .
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Related source file is "testbench.v".
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Found 8-bit tristate buffer for signal .
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Summary:
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inferred 8 Tristate(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "testbench.v".
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Found 1024x8-bit single-port block RAM for signal .
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-----------------------------------------------------------------------
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| ram_style | Auto | |
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-----------------------------------------------------------------------
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| Port A |
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| aspect ratio | 1024-word x 8-bit | |
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| mode | read-first | |
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| clkA | connected to signal | rise |
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| enA | connected to signal | high |
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| weA | connected to signal | high |
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| addrA | connected to signal | |
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| diA | connected to signal | |
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| doA | connected to signal | |
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-----------------------------------------------------------------------
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Found 8-bit tristate buffer for signal .
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Summary:
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inferred 1 RAM(s).
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inferred 8 Tristate(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "testbench.v".
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WARNING:Xst:647 - Input > is never used.
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WARNING:Xst:647 - Input > is never used.
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WARNING:Xst:737 - Found 6-bit latch for signal .
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WARNING:Xst:737 - Found 8-bit latch for signal .
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WARNING:Xst:737 - Found 8-bit latch for signal .
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Found 8-bit tristate buffer for signal .
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Found 6-bit comparator equal for signal <$cmp_eq0000> created at line 226.
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Summary:
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inferred 1 Comparator(s).
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inferred 8 Tristate(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "cpu8080.v".
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WARNING:Xst:646 - Signal is assigned but never used.
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Found 1-bit 8-to-1 multiplexer for signal .
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Found 1-bit 8-to-1 multiplexer for signal .
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Found 5-bit adder for signal <$add0001> created at line 1441.
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Found 8-bit adder carry out for signal <$addsub0000> created at line 1434.
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Found 4-bit adder carry out for signal <$addsub0001> created at line 1435.
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Found 6-bit subtractor for signal <$sub0000> created at line 1447.
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Found 6-bit subtractor for signal <$sub0001> created at line 1453.
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Found 9-bit subtractor for signal <$sub0002> created at line 1446.
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Found 8-bit xor2 for signal <$xor0000> created at line 1464.
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Found 1-bit xor8 for signal <$xor0002>.
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Summary:
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inferred 8 Adder/Subtractor(s).
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inferred 10 Multiplexer(s).
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inferred 1 Xor(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "testbench.v".
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Found 1-bit register for signal .
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Found 8-bit tristate buffer for signal .
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Found 8-bit register for signal .
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Found 4-bit comparator equal for signal .
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Found 4-bit register for signal .
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Summary:
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inferred 13 D-type flip-flop(s).
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inferred 1 Comparator(s).
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inferred 8 Tristate(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "cpu8080.v".
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Found finite state machine for signal .
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-----------------------------------------------------------------------
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| States | 30 |
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| Transitions | 897 |
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| Inputs | 138 |
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| Outputs | 31 |
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| Clock | clock (rising_edge) |
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| Reset | reset (positive) |
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| Reset type | synchronous |
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| Reset State | 00001 |
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| Encoding | automatic |
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| Implementation | LUT |
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-----------------------------------------------------------------------
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Found 4x1-bit ROM for signal <$mux0041> created at line 271.
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Found 16-bit register for signal .
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Found 1-bit register for signal .
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Found 1-bit register for signal .
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Found 1-bit register for signal .
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Found 1-bit register for signal .
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Found 1-bit register for signal .
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Found 8-bit tristate buffer for signal .
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Found 32-bit adder for signal <$add0001> created at line 453.
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Found 32-bit adder for signal <$add0002> created at line 465.
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Found 32-bit adder for signal <$add0003> created at line 477.
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Found 16-bit adder for signal <$add0004> created at line 930.
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Found 16-bit adder for signal <$add0005> created at line 845.
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Found 32-bit adder for signal <$add0006> created at line 522.
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Found 32-bit adder for signal <$add0007> created at line 510.
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Found 32-bit adder for signal <$add0008> created at line 498.
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Found 17-bit adder for signal <$add0009> created at line 443.
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Found 17-bit adder for signal <$addsub0000>.
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Found 17-bit adder for signal <$addsub0001>.
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Found 17-bit adder for signal <$addsub0002>.
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Found 8-bit adder for signal <$addsub0003>.
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Found 8-bit addsub for signal <$addsub0004>.
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Found 8-bit addsub for signal <$addsub0005>.
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Found 8-bit addsub for signal <$addsub0006>.
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Found 16-bit adder for signal <$addsub0007> created at line 1001.
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Found 16-bit adder for signal <$addsub0008> created at line 1042.
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Found 8-bit adder carry out for signal <$addsub0009>.
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Found 4-bit adder carry out for signal <$addsub0010> created at line 318.
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Found 8-bit adder carry out for signal <$addsub0011>.
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Found 4-bit comparator greater for signal <$cmp_gt0000> created at line 315.
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Found 4-bit comparator greater for signal <$cmp_gt0001> created at line 1251.
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Found 3-bit 4-to-1 multiplexer for signal <$mux0020> created at line 271.
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Found 8-bit 4-to-1 multiplexer for signal <$mux0021> created at line 271.
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Found 3-bit 4-to-1 multiplexer for signal <$mux0023> created at line 271.
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Found 8-bit 4-to-1 multiplexer for signal <$mux0029> created at line 271.
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Found 3-bit 4-to-1 multiplexer for signal <$mux0043>.
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Found 3-bit 4-to-1 multiplexer for signal <$mux0048> created at line 275.
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Found 8-bit 4-to-1 multiplexer for signal <$mux0049>.
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Found 16-bit adder for signal <$share0000> created at line 271.
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Found 6-bit adder for signal <$share0005> created at line 250.
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Found 16-bit addsub for signal <$share0006> created at line 271.
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Found 32-bit subtractor for signal <$sub0000> created at line 498.
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Found 32-bit subtractor for signal <$sub0001> created at line 510.
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Found 32-bit subtractor for signal <$sub0002> created at line 522.
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Found 16-bit subtractor for signal <$sub0003> created at line 719.
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Found 1-bit register for signal .
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Found 8-bit register for signal .
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Found 8-bit register for signal .
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Found 3-bit register for signal .
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Found 1-bit register for signal .
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Found 1-bit register for signal .
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Found 1-bit register for signal .
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Found 8-bit register for signal .
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Found 1-bit register for signal .
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Found 1-bit register for signal .
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Found 16-bit register for signal .
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Found 2-bit register for signal .
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Found 16-bit register for signal .
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Found 8-bit register for signal .
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Found 8-bit register for signal .
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Found 3-bit register for signal .
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Found 64-bit register for signal .
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Found 1-bit register for signal .
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Found 16-bit register for signal .
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Found 6-bit register for signal .
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Found 16-bit register for signal .
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Found 8-bit register for signal .
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Found 8-bit register for signal .
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Found 1-bit register for signal .
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Summary:
328
inferred 1 Finite State Machine(s).
329
inferred 1 ROM(s).
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inferred 227 D-type flip-flop(s).
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inferred 34 Adder/Subtractor(s).
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inferred 2 Comparator(s).
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inferred 52 Multiplexer(s).
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inferred 8 Tristate(s).
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Unit synthesized.
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Synthesizing Unit .
339
Related source file is "testbench.v".
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WARNING:Xst:646 - Signal is assigned but never used.
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WARNING:Xst:646 - Signal is assigned but never used.
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WARNING:Xst:646 - Signal is assigned but never used.
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Found 8-bit tristate buffer for signal .
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Summary:
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inferred 8 Tristate(s).
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Unit synthesized.
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INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
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=========================================================================
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HDL Synthesis Report
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Macro Statistics
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# RAMs : 1
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1024x8-bit single-port block RAM : 1
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# ROMs : 1
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4x1-bit ROM : 1
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# Adders/Subtractors : 42
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16-bit adder : 5
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16-bit addsub : 1
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16-bit subtractor : 1
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17-bit adder : 8
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32-bit adder : 6
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32-bit subtractor : 3
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4-bit adder carry out : 2
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5-bit adder : 1
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6-bit adder : 1
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6-bit subtractor : 2
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8-bit adder : 1
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8-bit adder carry out : 3
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8-bit addsub : 3
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9-bit adder : 3
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9-bit subtractor : 2
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# Registers : 40
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1-bit register : 14
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16-bit register : 5
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2-bit register : 1
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3-bit register : 2
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4-bit register : 1
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6-bit register : 1
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8-bit register : 16
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# Latches : 12
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6-bit latch : 4
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8-bit latch : 8
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# Comparators : 7
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4-bit comparator equal : 1
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4-bit comparator greater : 2
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6-bit comparator equal : 4
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# Multiplexers : 12
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1-bit 8-to-1 multiplexer : 2
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3-bit 4-to-1 multiplexer : 4
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8-bit 4-to-1 multiplexer : 3
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8-bit 8-to-1 multiplexer : 3
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# Tristates : 9
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8-bit tristate buffer : 9
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# Xors : 2
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1-bit xor8 : 1
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8-bit xor2 : 1
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400
=========================================================================
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=========================================================================
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* Advanced HDL Synthesis *
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=========================================================================
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Analyzing FSM for best encoding.
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Optimizing FSM on signal with speed1 encoding.
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-------------------------------------------
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State | Encoding
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-------------------------------------------
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00001 | 10000000000000000000000000000000
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00010 | 01000000000000000000000000000000
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00011 | 00000010000000000000000000000000
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00100 | 00000001000010000000000000000000
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00101 | 00010000000010000000000000000000
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00110 | 00000000000011000000000000000000
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00111 | 00000000000010100000000000000000
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01000 | 00000000000010010000000000000000
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01001 | 00000000000010001000000000000000
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01010 | 00000000000000000000000010000001
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01011 | 00000000000010000000010000000000
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01100 | 00001000000000000000000000000000
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01101 | 00000000100000000000000000000000
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01110 | 00000000010000000000000000000000
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01111 | 00000000001000000000000000000001
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10000 | 00000100000000000000000000000000
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10001 | 00000000000000000000000000100000
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10010 | 00000000000000000100000000000000
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10011 | 00000000000000000000000100000000
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10100 | 00000000000010000000000000010000
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10101 | 00000000000000000000000001000000
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10110 | 00000000000000000000000000001000
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10111 | 00000000000000000000000000000100
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11000 | 00000000000010000000000000000010
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11001 | 00000000000100000000000000000001
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11010 | 00000000000000000010000000000001
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11011 | 00000000000000000000100000000001
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11100 | 00000000000000000000001000000001
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11101 | 00000000000000000001000000000000
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11110 | 00100000000010000000000000000000
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-------------------------------------------
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Loading device for application Rf_Device from file '3s200.nph' in environment C:\Xilinx.
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WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block .
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .
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WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .
447
448
=========================================================================
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Advanced HDL Synthesis Report
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451
Macro Statistics
452
# FSMs : 1
453
# RAMs : 1
454
1024x8-bit single-port block RAM : 1
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# ROMs : 1
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4x1-bit ROM : 1
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# Adders/Subtractors : 42
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16-bit adder : 5
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16-bit addsub : 1
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16-bit subtractor : 1
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17-bit adder : 8
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32-bit adder : 6
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32-bit subtractor : 3
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4-bit adder carry out : 2
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5-bit adder : 1
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6-bit adder : 1
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6-bit subtractor : 2
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8-bit adder : 1
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8-bit adder carry out : 3
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8-bit addsub : 3
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9-bit adder : 3
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9-bit subtractor : 2
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# Registers : 267
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Flip-Flops : 267
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# Latches : 12
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6-bit latch : 4
477
8-bit latch : 8
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# Comparators : 7
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4-bit comparator equal : 1
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4-bit comparator greater : 2
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6-bit comparator equal : 4
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# Multiplexers : 12
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1-bit 8-to-1 multiplexer : 2
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3-bit 4-to-1 multiplexer : 4
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8-bit 4-to-1 multiplexer : 3
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8-bit 8-to-1 multiplexer : 3
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# Xors : 2
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1-bit xor8 : 1
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8-bit xor2 : 1
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=========================================================================
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493
=========================================================================
494
* Low Level Synthesis *
495
=========================================================================
496
WARNING:Xst:2040 - Unit testbench: 8 multi-source signals are replaced by logic (pull-up yes): N11, N13, N15, N17, N3, N5, N7, N9.
497
498
Optimizing unit ...
499
500
Optimizing unit ...
501
502
Mapping all equations...
503
Building and optimizing final netlist ...
504
Found area constraint ratio of 100 (+ 5) on block testbench, actual ratio is 65.
505
FlipFlop cpu/alusel_0 has been replicated 2 time(s)
506
FlipFlop cpu/alusel_1 has been replicated 2 time(s)
507
FlipFlop cpu/alusel_2 has been replicated 2 time(s)
508
FlipFlop cpu/regd_0 has been replicated 1 time(s)
509
FlipFlop cpu/regd_1 has been replicated 1 time(s)
510
FlipFlop cpu/regd_2 has been replicated 1 time(s)
511
FlipFlop cpu/regfil_5_0 has been replicated 1 time(s)
512
FlipFlop cpu/regfil_5_1 has been replicated 2 time(s)
513
FlipFlop cpu/state_FFd12 has been replicated 3 time(s)
514
FlipFlop cpu/state_FFd18 has been replicated 2 time(s)
515
FlipFlop cpu/state_FFd2 has been replicated 4 time(s)
516
FlipFlop cpu/state_FFd4 has been replicated 3 time(s)
517
FlipFlop cpu/statesel_1 has been replicated 1 time(s)
518
FlipFlop cpu/statesel_2 has been replicated 2 time(s)
519
FlipFlop cpu/statesel_3 has been replicated 2 time(s)
520
FlipFlop cpu/statesel_4 has been replicated 1 time(s)
521
FlipFlop cpu/statesel_5 has been replicated 1 time(s)
522
523
Final Macro Processing ...
524
525
=========================================================================
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Final Register Report
527
528
Macro Statistics
529
# Registers : 297
530
Flip-Flops : 297
531
532
=========================================================================
533
534
=========================================================================
535
* Partition Report *
536
=========================================================================
537
538
Partition Implementation Status
539
-------------------------------
540
541
No Partitions were found in this design.
542
543
-------------------------------
544
545
=========================================================================
546
* Final Report *
547
=========================================================================
548
Final Results
549
RTL Top Level Output File Name : testbench.ngr
550
Top Level Output File Name : testbench
551
Output Format : NGC
552
Optimization Goal : Speed
553
Keep Hierarchy : NO
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555
Design Statistics
556
# IOs : 33
557
558
Cell Usage :
559
# BELS : 2939
560
# GND : 1
561
# INV : 82
562
# LUT1 : 139
563
# LUT2 : 154
564
# LUT2_D : 6
565
# LUT2_L : 3
566
# LUT3 : 306
567
# LUT3_D : 20
568
# LUT3_L : 32
569
# LUT4 : 1115
570
# LUT4_D : 41
571
# LUT4_L : 255
572
# MULT_AND : 28
573
# MUXCY : 279
574
# MUXF5 : 215
575
# MUXF6 : 24
576
# VCC : 1
577
# XORCY : 238
578
# FlipFlops/Latches : 371
579
# FDE : 226
580
# FDR : 27
581
# FDRE : 5
582
# FDRS : 34
583
# FDRSE : 2
584
# FDS : 1
585
# FDSE : 2
586
# LDCE : 50
587
# LDE_1 : 24
588
# RAMS : 1
589
# RAMB16_S9 : 1
590
# Clock Buffers : 2
591
# BUFGP : 2
592
# IO Buffers : 31
593
# IBUF : 2
594
# IOBUF : 8
595
# OBUF : 21
596
=========================================================================
597
598
Device utilization summary:
599
---------------------------
600
601
Selected Device : 3s200pq208-5
602
603
Number of Slices: 1139 out of 1920 59%
604
Number of Slice Flip Flops: 371 out of 3840 9%
605
Number of 4 input LUTs: 2153 out of 3840 56%
606
Number of IOs: 33
607
Number of bonded IOBs: 33 out of 141 23%
608
Number of BRAMs: 1 out of 12 8%
609
Number of GCLKs: 2 out of 8 25%
610
611
612
=========================================================================
613
TIMING REPORT
614
615
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
616
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
617
GENERATED AFTER PLACE-and-ROUTE.
618
619
Clock Information:
620
------------------
621
-----------------------------------------------------+--------------------------------+-------+
622
Clock Signal | Clock buffer(FF name) | Load |
623
-----------------------------------------------------+--------------------------------+-------+
624
clock | BUFGP | 297 |
625
reset | BUFGP | 24 |
626
select1/selectd/_and0000(select1/selectd/_and00001:O)| NONE(*)(select1/selectd/mask_7)| 11 |
627
select1/selectc/_and0000(select1/selectc/_and00001:O)| NONE(*)(select1/selectc/comp_1)| 11 |
628
select1/selectb/_and0000(select1/selectb/_and00001:O)| NONE(*)(select1/selectb/mask_2)| 14 |
629
select1/selecta/_and0000(select1/selecta/_and00001:O)| NONE(*)(select1/selecta/comp_3)| 14 |
630
-----------------------------------------------------+--------------------------------+-------+
631
(*) These 4 clock signal(s) are generated by combinatorial logic,
632
and XST is not able to identify which are the primary clock signals.
633
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
634
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
635
636
Asynchronous Control Signals Information:
637
----------------------------------------
638
-----------------------------------+------------------------+-------+
639
Control Signal | Buffer(FF name) | Load |
640
-----------------------------------+------------------------+-------+
641
reset | BUFGP | 50 |
642
-----------------------------------+------------------------+-------+
643
644
Timing Summary:
645
---------------
646
Speed Grade: -5
647
648
Minimum period: 9.734ns (Maximum Frequency: 102.728MHz)
649
Minimum input arrival time before clock: 15.385ns
650
Maximum output required time after clock: 16.387ns
651
Maximum combinational path delay: No path found
652
653
Timing Detail:
654
--------------
655
All values displayed in nanoseconds (ns)
656
657
=========================================================================
658
Timing constraint: Default period analysis for Clock 'clock'
659
Clock period: 9.734ns (frequency: 102.728MHz)
660
Total number of paths / destination ports: 22856 / 378
661
-------------------------------------------------------------------------
662
Delay: 9.734ns (Levels of Logic = 10)
663
Source: cpu/aluoprb_0 (FF)
664
Destination: cpu/regfil_2_5 (FF)
665
Source Clock: clock rising
666
Destination Clock: clock rising
667
668
Data Path: cpu/aluoprb_0 to cpu/regfil_2_5
669
Gate Net
670
Cell:in->out fanout Delay Delay Logical Name (Net Name)
671
---------------------------------------- ------------
672
FDE:C->Q 13 0.626 1.289 cpu/aluoprb_0 (cpu/aluoprb_0)
673
LUT2:I0->O 1 0.479 0.000 cpu/alu/Msub__sub0002_lut<0> (cpu/alu/N19)
674
MUXCY:S->O 1 0.435 0.000 cpu/alu/Msub__sub0002_cy<0> (cpu/alu/Msub__sub0002_cy<0>)
675
MUXCY:CI->O 1 0.056 0.000 cpu/alu/Msub__sub0002_cy<1> (cpu/alu/Msub__sub0002_cy<1>)
676
MUXCY:CI->O 1 0.056 0.000 cpu/alu/Msub__sub0002_cy<2> (cpu/alu/Msub__sub0002_cy<2>)
677
XORCY:CI->O 7 0.786 1.076 cpu/alu/Msub__sub0002_xor<3> (cpu/alu/_sub0002<3>)
678
LUT2:I1->O 1 0.479 0.740 cpu/alu/Msub__AUX_32_xor<5>11_SW0 (N9996)
679
LUT4:I2->O 1 0.479 0.000 cpu/alu/sel<0>22 (cpu/alu/N241)
680
MUXF5:I1->O 2 0.314 0.745 cpu/alu/sel<1>_f5_10 (cpu/alu/sel<1>_f511)
681
MUXF5:S->O 8 0.540 0.980 cpu/alu/res<5>1 (cpu/alures<5>)
682
LUT4:I2->O 1 0.479 0.000 cpu/_mux0016<5>60 (cpu/_mux0016<5>)
683
FDE:D 0.176 cpu/regfil_2_5
684
----------------------------------------
685
Total 9.734ns (4.904ns logic, 4.830ns route)
686
(50.4% logic, 49.6% route)
687
688
=========================================================================
689
Timing constraint: Default OFFSET IN BEFORE for Clock 'clock'
690
Total number of paths / destination ports: 15524 / 569
691
-------------------------------------------------------------------------
692
Offset: 15.385ns (Levels of Logic = 10)
693
Source: data<4> (PAD)
694
Destination: cpu/regfil_1_5 (FF)
695
Destination Clock: clock rising
696
697
Data Path: data<4> to cpu/regfil_1_5
698
Gate Net
699
Cell:in->out fanout Delay Delay Logical Name (Net Name)
700
---------------------------------------- ------------
701
IOBUF:IO->O 153 0.715 2.459 data_4_IOBUF (N9902)
702
LUT2:I0->O 18 0.479 1.227 cpu/_mux0026<5>29 (N112)
703
LUT4:I3->O 14 0.479 1.304 cpu/_cmp_eq00652 (cpu/_cmp_eq0065)
704
LUT4:I0->O 1 0.479 0.976 cpu/_cmp_eq00671_SW0 (N10381)
705
LUT4_D:I0->O 10 0.479 0.987 cpu/_mux0016<7>1113 (N149)
706
LUT4:I3->O 1 0.479 0.740 cpu/_mux0015<2>31_SW2 (N10542)
707
LUT4:I2->O 8 0.479 0.944 cpu/_mux0015<2>31 (N277)
708
LUT4:I3->O 2 0.479 0.745 cpu/_mux0015<5>38 (cpu/_mux0015<5>_map1354)
709
MUXF5:S->O 1 0.540 0.740 cpu/_mux0012<5>31_SW5 (N10424)
710
LUT4:I2->O 1 0.479 0.000 cpu/_mux0015<5>40 (cpu/_mux0015<5>)
711
FDE:D 0.176 cpu/regfil_1_5
712
----------------------------------------
713
Total 15.385ns (5.263ns logic, 10.122ns route)
714
(34.2% logic, 65.8% route)
715
716
=========================================================================
717
Timing constraint: Default OFFSET IN BEFORE for Clock 'select1/selectd/_and0000'
718
Total number of paths / destination ports: 11 / 11
719
-------------------------------------------------------------------------
720
Offset: 3.304ns (Levels of Logic = 1)
721
Source: data<3> (PAD)
722
Destination: select1/selectd/mask_3 (LATCH)
723
Destination Clock: select1/selectd/_and0000 falling
724
725
Data Path: data<3> to select1/selectd/mask_3
726
Gate Net
727
Cell:in->out fanout Delay Delay Logical Name (Net Name)
728
---------------------------------------- ------------
729
IOBUF:IO->O 204 0.715 2.413 data_3_IOBUF (N9903)
730
LDCE:D 0.176 select1/selectd/mask_3
731
----------------------------------------
732
Total 3.304ns (0.891ns logic, 2.413ns route)
733
(27.0% logic, 73.0% route)
734
735
=========================================================================
736
Timing constraint: Default OFFSET IN BEFORE for Clock 'select1/selectc/_and0000'
737
Total number of paths / destination ports: 11 / 11
738
-------------------------------------------------------------------------
739
Offset: 3.304ns (Levels of Logic = 1)
740
Source: data<3> (PAD)
741
Destination: select1/selectc/mask_3 (LATCH)
742
Destination Clock: select1/selectc/_and0000 falling
743
744
Data Path: data<3> to select1/selectc/mask_3
745
Gate Net
746
Cell:in->out fanout Delay Delay Logical Name (Net Name)
747
---------------------------------------- ------------
748
IOBUF:IO->O 204 0.715 2.413 data_3_IOBUF (N9903)
749
LDCE:D 0.176 select1/selectc/mask_3
750
----------------------------------------
751
Total 3.304ns (0.891ns logic, 2.413ns route)
752
(27.0% logic, 73.0% route)
753
754
=========================================================================
755
Timing constraint: Default OFFSET IN BEFORE for Clock 'select1/selectb/_and0000'
756
Total number of paths / destination ports: 14 / 14
757
-------------------------------------------------------------------------
758
Offset: 3.304ns (Levels of Logic = 1)
759
Source: data<3> (PAD)
760
Destination: select1/selectb/mask_3 (LATCH)
761
Destination Clock: select1/selectb/_and0000 falling
762
763
Data Path: data<3> to select1/selectb/mask_3
764
Gate Net
765
Cell:in->out fanout Delay Delay Logical Name (Net Name)
766
---------------------------------------- ------------
767
IOBUF:IO->O 204 0.715 2.413 data_3_IOBUF (N9903)
768
LDCE:D 0.176 select1/selectb/mask_3
769
----------------------------------------
770
Total 3.304ns (0.891ns logic, 2.413ns route)
771
(27.0% logic, 73.0% route)
772
773
=========================================================================
774
Timing constraint: Default OFFSET IN BEFORE for Clock 'select1/selecta/_and0000'
775
Total number of paths / destination ports: 14 / 14
776
-------------------------------------------------------------------------
777
Offset: 3.304ns (Levels of Logic = 1)
778
Source: data<3> (PAD)
779
Destination: select1/selecta/mask_3 (LATCH)
780
Destination Clock: select1/selecta/_and0000 falling
781
782
Data Path: data<3> to select1/selecta/mask_3
783
Gate Net
784
Cell:in->out fanout Delay Delay Logical Name (Net Name)
785
---------------------------------------- ------------
786
IOBUF:IO->O 204 0.715 2.413 data_3_IOBUF (N9903)
787
LDCE:D 0.176 select1/selecta/mask_3
788
----------------------------------------
789
Total 3.304ns (0.891ns logic, 2.413ns route)
790
(27.0% logic, 73.0% route)
791
792
=========================================================================
793
Timing constraint: Default OFFSET OUT AFTER for Clock 'clock'
794
Total number of paths / destination ports: 1369 / 29
795
-------------------------------------------------------------------------
796
Offset: 16.387ns (Levels of Logic = 9)
797
Source: cpu/addr_2 (FF)
798
Destination: data<7> (PAD)
799
Source Clock: clock rising
800
801
Data Path: cpu/addr_2 to data<7>
802
Gate Net
803
Cell:in->out fanout Delay Delay Logical Name (Net Name)
804
---------------------------------------- ------------
805
FDE:C->Q 31 0.626 1.593 cpu/addr_2 (cpu/addr_2)
806
LUT4:I3->O 1 0.479 0.000 select1/select11021 (N11407)
807
MUXF5:I1->O 1 0.314 0.851 select1/select1102_f5 (select1/select1_map3479)
808
LUT4:I1->O 1 0.479 0.851 select1/select1123 (select1/select1_map3481)
809
LUT4:I1->O 10 0.479 1.259 select1/select1446 (romsel)
810
LUT3:I0->O 2 0.479 1.040 N11LogicTrst438 (N565)
811
LUT4:I0->O 4 0.479 1.074 N17LogicTrst21 (N191)
812
LUT4:I0->O 1 0.479 0.000 N17LogicTrst802 (N11410)
813
MUXF5:I0->O 1 0.314 0.681 N17LogicTrst80_f5 (data_0_IOBUF)
814
IOBUF:I->IO 4.909 data_0_IOBUF (data<0>)
815
----------------------------------------
816
Total 16.387ns (9.037ns logic, 7.350ns route)
817
(55.1% logic, 44.9% route)
818
819
=========================================================================
820
Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selecta/_and0000'
821
Total number of paths / destination ports: 810 / 8
822
-------------------------------------------------------------------------
823
Offset: 15.933ns (Levels of Logic = 9)
824
Source: select1/selecta/mask_1 (LATCH)
825
Destination: data<7> (PAD)
826
Source Clock: select1/selecta/_and0000 falling
827
828
Data Path: select1/selecta/mask_1 to data<7>
829
Gate Net
830
Cell:in->out fanout Delay Delay Logical Name (Net Name)
831
---------------------------------------- ------------
832
LDCE:G->Q 7 0.551 1.201 select1/selecta/mask_1 (select1/selecta/mask_1)
833
LUT4:I0->O 1 0.479 0.000 select1/select11961 (N11471)
834
MUXF5:I1->O 1 0.314 0.976 select1/select1196_f5 (select1/select1_map3499)
835
LUT4:I0->O 1 0.479 0.740 select1/select1420 (select1/select1_map3553)
836
LUT4:I2->O 10 0.479 1.259 select1/select1446 (romsel)
837
LUT3:I0->O 2 0.479 1.040 N11LogicTrst438 (N565)
838
LUT4:I0->O 4 0.479 1.074 N17LogicTrst21 (N191)
839
LUT4:I0->O 1 0.479 0.000 N17LogicTrst802 (N11410)
840
MUXF5:I0->O 1 0.314 0.681 N17LogicTrst80_f5 (data_0_IOBUF)
841
IOBUF:I->IO 4.909 data_0_IOBUF (data<0>)
842
----------------------------------------
843
Total 15.933ns (8.962ns logic, 6.971ns route)
844
(56.2% logic, 43.8% route)
845
846
=========================================================================
847
Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selectb/_and0000'
848
Total number of paths / destination ports: 806 / 8
849
-------------------------------------------------------------------------
850
Offset: 16.154ns (Levels of Logic = 10)
851
Source: select1/selectb/mask_1 (LATCH)
852
Destination: data<7> (PAD)
853
Source Clock: select1/selectb/_and0000 falling
854
855
Data Path: select1/selectb/mask_1 to data<7>
856
Gate Net
857
Cell:in->out fanout Delay Delay Logical Name (Net Name)
858
---------------------------------------- ------------
859
LDCE:G->Q 7 0.551 1.201 select1/selectb/mask_1 (select1/selectb/mask_1)
860
LUT4:I0->O 1 0.479 0.000 select1/selectb/_cmp_eq000011 (N11441)
861
MUXF5:I1->O 3 0.314 1.066 select1/selectb/_cmp_eq00001_f5 (select1/selectb/_cmp_eq00002)
862
LUT3:I0->O 1 0.479 0.000 ram/_and0000_inv231 (N11451)
863
MUXF5:I1->O 1 0.314 0.740 ram/_and0000_inv23_f5 (ram/_and0000_inv_map3882)
864
LUT4:I2->O 12 0.479 1.120 ram/_and0000_inv79 (ram/_and0000_inv)
865
LUT4:I1->O 11 0.479 0.995 N21 (N2)
866
LUT4:I3->O 4 0.479 1.074 N17LogicTrst21 (N191)
867
LUT4:I0->O 1 0.479 0.000 N17LogicTrst802 (N11410)
868
MUXF5:I0->O 1 0.314 0.681 N17LogicTrst80_f5 (data_0_IOBUF)
869
IOBUF:I->IO 4.909 data_0_IOBUF (data<0>)
870
----------------------------------------
871
Total 16.154ns (9.276ns logic, 6.878ns route)
872
(57.4% logic, 42.6% route)
873
874
=========================================================================
875
Timing constraint: Default OFFSET OUT AFTER for Clock 'reset'
876
Total number of paths / destination ports: 41 / 6
877
-------------------------------------------------------------------------
878
Offset: 11.595ns (Levels of Logic = 6)
879
Source: select1/selecta/datai_3 (LATCH)
880
Destination: data<3> (PAD)
881
Source Clock: reset rising
882
883
Data Path: select1/selecta/datai_3 to data<3>
884
Gate Net
885
Cell:in->out fanout Delay Delay Logical Name (Net Name)
886
---------------------------------------- ------------
887
LDE_1:G->Q 2 0.551 0.804 select1/selecta/datai_3 (select1/selecta/datai_3)
888
LUT4:I2->O 1 0.479 0.000 N11LogicTrst461_SW02 (N11480)
889
MUXF5:I0->O 1 0.314 0.740 N11LogicTrst461_SW0_f5 (N11197)
890
LUT4:I2->O 1 0.479 0.976 N11LogicTrst461 (N11LogicTrst_map3597)
891
LUT4:I0->O 1 0.479 0.704 N11LogicTrst76 (N11LogicTrst_map3602)
892
LUT4:I3->O 1 0.479 0.681 N11LogicTrst87 (data_3_IOBUF)
893
IOBUF:I->IO 4.909 data_3_IOBUF (data<3>)
894
----------------------------------------
895
Total 11.595ns (7.690ns logic, 3.905ns route)
896
(66.3% logic, 33.7% route)
897
898
=========================================================================
899
CPU : 119.56 / 119.83 s | Elapsed : 119.00 / 120.00 s
900
901
-->
902
903
Total memory usage is 198928 kilobytes
904
905
Number of errors : 0 ( 0 filtered)
906
Number of warnings : 15 ( 0 filtered)
907
Number of infos : 2 ( 0 filtered)
908
