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Release 8.2.02i - xst I.33
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Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
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--> Parameter TMPDIR set to ./xst/projnav.tmp
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CPU : 0.00 / 0.39 s | Elapsed : 0.00 / 0.00 s
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--> Parameter xsthdpdir set to ./xst
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CPU : 0.00 / 0.39 s | Elapsed : 0.00 / 0.00 s
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--> Reading design: testbench.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Compilation
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3) Design Hierarchy Analysis
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4) HDL Analysis
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5) HDL Synthesis
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5.1) HDL Synthesis Report
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6) Advanced HDL Synthesis
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6.1) Advanced HDL Synthesis Report
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7) Low Level Synthesis
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8) Partition Report
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9) Final Report
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9.1) Device utilization summary
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9.2) TIMING REPORT
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "testbench.prj"
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "testbench"
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Output Format : NGC
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Target Device : xc3s1000-4-ft256
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---- Source Options
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Top Module Name : testbench
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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FSM Style : lut
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RAM Extraction : Yes
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RAM Style : Auto
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ROM Extraction : Yes
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Mux Style : Auto
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Decoder Extraction : YES
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Priority Encoder Extraction : YES
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Shift Register Extraction : YES
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Logical Shifter Extraction : YES
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XOR Collapsing : YES
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ROM Style : Auto
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Mux Extraction : YES
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Resource Sharing : YES
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Multiplier Style : auto
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Automatic Register Balancing : No
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---- Target Options
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Add IO Buffers : YES
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Global Maximum Fanout : 500
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Add Generic Clock Buffer(BUFG) : 8
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Register Duplication : YES
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Slice Packing : YES
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Pack IO Registers into IOBs : auto
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 1
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Keep Hierarchy : NO
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RTL Output : Yes
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Global Optimization : AllClockNets
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Write Timing Constraints : NO
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : maintain
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Slice Utilization Ratio : 100
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Slice Utilization Ratio Delta : 5
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---- Other Options
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lso : testbench.lso
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Read Cores : YES
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cross_clock_analysis : NO
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verilog2001 : YES
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safe_implementation : No
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Optimize Instantiated Primitives : NO
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use_clock_enable : Yes
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use_sync_set : Yes
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use_sync_reset : Yes
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=========================================================================
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling vhdl file "C:/Xilinx/ISEexamples/cpu8080/common.vhd" in Library work.
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Architecture common of Entity common is up to date.
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Compiling vhdl file "C:/Xilinx/ISEexamples/cpu8080/ps2_kbd.vhd" in Library work.
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Architecture arch of Entity ps2_kbd is up to date.
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Compiling vhdl file "C:/Xilinx/ISEexamples/cpu8080/vga.vhd" in Library work.
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Package compiled.
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Entity compiled.
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Entity (Architecture ) compiled.
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Entity compiled.
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Entity (Architecture ) compiled.
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Compiling verilog file "vgachr.v" in library work
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Module compiled
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Module compiled
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Module compiled
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Module compiled
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Compiling verilog file "cpu8080.v" in library work
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Module compiled
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Module compiled
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Compiling verilog file "testbench.v" in library work
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Module compiled
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Module compiled
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Module compiled
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Module compiled
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Module compiled
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Compiling verilog include file "test.rom"
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Module compiled
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Module compiled
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No errors in compilation
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Analysis of file <"testbench.prj"> succeeded.
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=========================================================================
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* Design Hierarchy Analysis *
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=========================================================================
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for entity in library (architecture ) with generics.
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FREQ = 50000
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for entity in library (architecture ) with generics.
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CLK_DIV = 2
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FIT_TO_SCREEN = true
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FREQ = 50000
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LINES_PER_FRAME = 480
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NUM_RGB_BITS = 3
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PIXEL_WIDTH = 1
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PIXELS_PER_LINE = 640
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for entity in library (architecture ) with generics.
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FREQ = 25000
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PERIOD = 32
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START = 26
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VISIBLE = 640
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WIDTH = 4
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Analyzing hierarchy for entity in library (architecture ) with generics.
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FREQ = 31
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PERIOD = 16784
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START = 15700
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VISIBLE = 480
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WIDTH = 64
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Building hierarchy successfully finished.
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=========================================================================
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* HDL Analysis *
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=========================================================================
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Analyzing top module .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing generic Entity in library (Architecture ).
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PIXEL_WIDTH = 1
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PIXELS_PER_LINE = 640
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CLK_DIV = 2
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FIT_TO_SCREEN = true
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FREQ = 50000
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LINES_PER_FRAME = 480
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NUM_RGB_BITS = 3
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Entity analyzed. Unit generated.
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Analyzing generic Entity in library (Architecture ).
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FREQ = 25000
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VISIBLE = 640
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WIDTH = 4
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PERIOD = 32
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START = 26
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Entity analyzed. Unit generated.
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Analyzing generic Entity in library (Architecture ).
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FREQ = 31
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PERIOD = 16784
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START = 15700
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VISIBLE = 480
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WIDTH = 64
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Entity analyzed. Unit generated.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing generic Entity in library (Architecture ).
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FREQ = 50000
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Entity analyzed. Unit generated.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Performing bidirectional port resolution...
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Synthesizing Unit .
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Related source file is "testbench.v".
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Found 128x8-bit ROM for signal <$mux0000>.
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Found 8-bit tristate buffer for signal .
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Summary:
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inferred 1 ROM(s).
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inferred 8 Tristate(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "testbench.v".
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Found 1024x8-bit single-port block RAM for signal .
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-----------------------------------------------------------------------
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| ram_style | Auto | |
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-----------------------------------------------------------------------
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| Port A |
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| aspect ratio | 1024-word x 8-bit | |
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| mode | read-first | |
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| clkA | connected to signal | fall |
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| enA | connected to signal | high |
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| weA | connected to signal | high |
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| addrA | connected to signal | |
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| diA | connected to signal | |
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| doA | connected to signal | |
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-----------------------------------------------------------------------
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Found 8-bit tristate buffer for signal .
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Summary:
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inferred 1 RAM(s).
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inferred 8 Tristate(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "testbench.v".
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Found finite state machine for signal .
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-----------------------------------------------------------------------
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| States | 3 |
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| Transitions | 3 |
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| Inputs | 0 |
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| Outputs | 4 |
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| Clock | clock (falling_edge) |
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| Clock enable | $not0004 (positive) |
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| Reset | reset (positive) |
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| Reset type | synchronous |
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| Reset State | 0000 |
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| Encoding | automatic |
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| Implementation | LUT |
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-----------------------------------------------------------------------
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Found 8-bit tristate buffer for signal .
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Found 1-bit 4-to-1 multiplexer for signal <$mux0000>.
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Found 1-bit 4-to-1 multiplexer for signal <$mux0001>.
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Found 1-bit 4-to-1 multiplexer for signal <$mux0002>.
319
Found 1-bit 4-to-1 multiplexer for signal <$mux0003>.
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Found 1-bit 4-to-1 multiplexer for signal <$mux0004>.
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Found 1-bit 4-to-1 multiplexer for signal <$mux0005>.
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Found 1-bit 4-to-1 multiplexer for signal <$mux0006>.
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Found 1-bit 4-to-1 multiplexer for signal <$mux0007>.
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Found 8-bit register for signal .
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Found 8-bit register for signal .
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Found 8-bit register for signal .
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Found 8-bit register for signal .
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Found 8-bit register for signal .
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Found 8-bit register for signal .
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Summary:
331
inferred 1 Finite State Machine(s).
332
inferred 48 D-type flip-flop(s).
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inferred 8 Multiplexer(s).
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inferred 8 Tristate(s).
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Unit synthesized.
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Synthesizing Unit .
339
Related source file is "testbench.v".
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WARNING:Xst:647 - Input > is never used.
341
WARNING:Xst:647 - Input > is never used.
342
WARNING:Xst:737 - Found 6-bit latch for signal .
343
WARNING:Xst:737 - Found 8-bit latch for signal .
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WARNING:Xst:737 - Found 8-bit latch for signal .
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Found 8-bit tristate buffer for signal .
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Found 6-bit comparator equal for signal <$cmp_eq0000> created at line 291.
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Summary:
348
inferred 1 Comparator(s).
349
inferred 8 Tristate(s).
350
Unit synthesized.
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353
Synthesizing Unit .
354
Related source file is "cpu8080.v".
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WARNING:Xst:646 - Signal is assigned but never used.
356
Found 1-bit 8-to-1 multiplexer for signal .
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Found 1-bit 8-to-1 multiplexer for signal .
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Found 5-bit adder for signal <$add0001> created at line 1514.
359
Found 8-bit adder carry out for signal <$addsub0000> created at line 1507.
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Found 4-bit adder carry out for signal <$addsub0001> created at line 1508.
361
Found 6-bit subtractor for signal <$sub0000> created at line 1520.
362
Found 6-bit subtractor for signal <$sub0001> created at line 1526.
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Found 9-bit subtractor for signal <$sub0002> created at line 1519.
364
Found 8-bit xor2 for signal <$xor0000> created at line 1537.
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Found 1-bit xor8 for signal <$xor0002>.
366
Summary:
367
inferred 8 Adder/Subtractor(s).
368
inferred 10 Multiplexer(s).
369
inferred 1 Xor(s).
370
Unit synthesized.
371
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Synthesizing Unit .
374
Related source file is "C:/Xilinx/ISEexamples/cpu8080/ps2_kbd.vhd".
375
WARNING:Xst:646 - Signal is assigned but never used.
376
Found 13-bit adder for signal <$addsub0000> created at line 112.
377
Found 4-bit up counter for signal .
378
Found 1-bit register for signal .
379
Found 5-bit register for signal .
380
Found 1-bit register for signal .
381
Found 10-bit register for signal .
382
Found 13-bit register for signal .
383
Summary:
384
inferred 1 Counter(s).
385
inferred 30 D-type flip-flop(s).
386
inferred 1 Adder/Subtractor(s).
387
Unit synthesized.
388
389
390
Synthesizing Unit .
391
Related source file is "vgachr.v".
392
Unit synthesized.
393
394
395
Synthesizing Unit .
396
Related source file is "vgachr.v".
397
Unit synthesized.
398
399
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Synthesizing Unit .
401
Related source file is "vgachr.v".
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Found 2048x8-bit ROM for signal .
403
Summary:
404
inferred 1 ROM(s).
405
Unit synthesized.
406
407
408
Synthesizing Unit .
409
Related source file is "C:/Xilinx/ISEexamples/cpu8080/vga.vhd".
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Found 16-bit adder for signal <$addsub0000> created at line 398.
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Found 1-bit register for signal .
412
Found 16-bit register for signal .
413
Found 1-bit register for signal .
414
Found 1-bit register for signal .
415
Summary:
416
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inferred 3 D-type flip-flop(s).
417
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inferred 1 Adder/Subtractor(s).
418
Unit synthesized.
419
420
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Synthesizing Unit .
422
Related source file is "C:/Xilinx/ISEexamples/cpu8080/vga.vhd".
423
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Found 16-bit adder for signal <$addsub0000> created at line 398.
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Found 1-bit register for signal .
425
Found 16-bit register for signal .
426
Found 1-bit register for signal .
427
Found 1-bit register for signal .
428
Summary:
429
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inferred 3 D-type flip-flop(s).
430
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inferred 1 Adder/Subtractor(s).
431
Unit synthesized.
432
433
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Synthesizing Unit .
435
Related source file is "testbench.v".
436
Found 1-bit register for signal .
437
Found 8-bit tristate buffer for signal .
438
Found 8-bit register for signal .
439
Found 4-bit comparator equal for signal .
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Found 4-bit register for signal .
441
Summary:
442
inferred 13 D-type flip-flop(s).
443
inferred 1 Comparator(s).
444
inferred 8 Tristate(s).
445
Unit synthesized.
446
447
448
Synthesizing Unit .
449
Related source file is "cpu8080.v".
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INFO:Xst:1799 - State 0XXXXX is never reached in FSM .
451
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Found finite state machine for signal .
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-----------------------------------------------------------------------
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| States | 34 |
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| Transitions | 901 |
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| Inputs | 139 |
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| Outputs | 33 |
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| Clock | clock (rising_edge) |
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| Reset | reset (positive) |
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| Reset type | synchronous |
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| Reset State | 000001 |
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| Encoding | automatic |
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| Implementation | LUT |
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-----------------------------------------------------------------------
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Found 4x1-bit ROM for signal <$mux0043> created at line 309.
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Found 16-bit register for signal .
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Found 1-bit register for signal .
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Found 1-bit register for signal .
468
Found 1-bit register for signal .
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Found 1-bit register for signal .
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Found 1-bit register for signal .
471
Found 8-bit tristate buffer for signal .
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Found 32-bit adder for signal <$add0001> created at line 491.
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Found 32-bit adder for signal <$add0002> created at line 503.
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Found 32-bit adder for signal <$add0003> created at line 515.
475
Found 16-bit adder for signal <$add0004> created at line 975.
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Found 16-bit adder for signal <$add0005> created at line 886.
477
Found 32-bit adder for signal <$add0006> created at line 560.
478
Found 32-bit adder for signal <$add0007> created at line 548.
479
Found 32-bit adder for signal <$add0008> created at line 536.
480
Found 17-bit adder for signal <$add0009> created at line 481.
481
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Found 17-bit adder for signal <$addsub0000>.
482
Found 17-bit adder for signal <$addsub0001>.
483
Found 17-bit adder for signal <$addsub0002>.
484
Found 8-bit adder for signal <$addsub0003>.
485
Found 8-bit addsub for signal <$addsub0004>.
486
Found 8-bit addsub for signal <$addsub0005>.
487
Found 8-bit addsub for signal <$addsub0006>.
488
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Found 16-bit adder for signal <$addsub0007> created at line 1046.
489
Found 6-bit adder for signal <$addsub0008>.
490
Found 16-bit adder for signal <$addsub0009> created at line 1087.
491
Found 8-bit adder carry out for signal <$addsub0010>.
492
Found 4-bit adder carry out for signal <$addsub0011> created at line 356.
493
Found 8-bit adder carry out for signal <$addsub0012>.
494
Found 4-bit comparator greater for signal <$cmp_gt0000> created at line 353.
495
Found 4-bit comparator greater for signal <$cmp_gt0001> created at line 1324.
496
Found 3-bit 4-to-1 multiplexer for signal <$mux0022> created at line 309.
497
Found 8-bit 4-to-1 multiplexer for signal <$mux0023> created at line 309.
498
Found 3-bit 4-to-1 multiplexer for signal <$mux0025> created at line 309.
499
Found 8-bit 4-to-1 multiplexer for signal <$mux0031> created at line 309.
500
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Found 3-bit 4-to-1 multiplexer for signal <$mux0045>.
501
18 samiam9512
Found 3-bit 4-to-1 multiplexer for signal <$mux0050> created at line 313.
502
11 samiam9512
Found 8-bit 4-to-1 multiplexer for signal <$mux0051>.
503
18 samiam9512
Found 16-bit adder for signal <$share0000> created at line 309.
504
Found 16-bit addsub for signal <$share0006> created at line 309.
505
Found 32-bit subtractor for signal <$sub0000> created at line 536.
506
Found 32-bit subtractor for signal <$sub0001> created at line 548.
507
Found 32-bit subtractor for signal <$sub0002> created at line 560.
508
Found 16-bit subtractor for signal <$sub0003> created at line 757.
509
2 samiam9512
Found 1-bit register for signal .
510
Found 8-bit register for signal .
511
Found 8-bit register for signal .
512
Found 3-bit register for signal .
513
Found 1-bit register for signal .
514
Found 1-bit register for signal .
515
Found 1-bit register for signal .
516
Found 8-bit register for signal .
517
Found 1-bit register for signal .
518
11 samiam9512
Found 1-bit register for signal .
519
9 samiam9512
Found 1-bit register for signal .
520
11 samiam9512
Found 8-bit register for signal .
521
2 samiam9512
Found 1-bit register for signal .
522
Found 16-bit register for signal .
523
Found 2-bit register for signal .
524
Found 16-bit register for signal .
525
Found 8-bit register for signal .
526
Found 8-bit register for signal .
527
Found 3-bit register for signal .
528
Found 64-bit register for signal .
529
Found 1-bit register for signal .
530
Found 16-bit register for signal .
531
Found 6-bit register for signal .
532
Found 16-bit register for signal .
533
Found 8-bit register for signal .
534
Found 8-bit register for signal .
535
Found 1-bit register for signal .
536
Summary:
537
inferred 1 Finite State Machine(s).
538
inferred 1 ROM(s).
539
11 samiam9512
inferred 237 D-type flip-flop(s).
540
2 samiam9512
inferred 34 Adder/Subtractor(s).
541
inferred 2 Comparator(s).
542
inferred 52 Multiplexer(s).
543
inferred 8 Tristate(s).
544
Unit synthesized.
545
546
547
11 samiam9512
Synthesizing Unit .
548
Related source file is "C:/Xilinx/ISEexamples/cpu8080/vga.vhd".
549
WARNING:Xst:646 - Signal is assigned but never used.
550
WARNING:Xst:646 - Signal > is assigned but never used.
551
Found 3-bit register for signal .
552
Found 1-bit register for signal .
553
Found 8-bit up counter for signal .
554
Found 1-bit register for signal .
555
Found 3-bit register for signal .
556
Found 16-bit register for signal .
557
Found 1-bit register for signal .
558
Found 9-bit register for signal .
559
Summary:
560
inferred 1 Counter(s).
561
inferred 34 D-type flip-flop(s).
562
Unit synthesized.
563
564
565
Synthesizing Unit .
566
Related source file is "vgachr.v".
567
20 samiam9512
WARNING:Xst:646 - Signal > is assigned but never used.
568
11 samiam9512
WARNING:Xst:646 - Signal is assigned but never used.
569
Found 1920x8-bit single-port block RAM for signal .
570
-----------------------------------------------------------------------
571
| ram_style | Auto | |
572
-----------------------------------------------------------------------
573
| Port A |
574
| aspect ratio | 1920-word x 8-bit | |
575
| mode | read-first | |
576
| clkA | connected to signal | rise |
577
| weA | connected to signal | high |
578
| addrA | connected to signal | |
579
| diA | connected to signal | |
580
| doA | connected to signal | |
581
-----------------------------------------------------------------------
582
Found 1920x8-bit dual-port distributed RAM for signal .
583
-----------------------------------------------------------------------
584
| ram_style | Auto | |
585
-----------------------------------------------------------------------
586
| Port A |
587
| aspect ratio | 1920-word x 8-bit | |
588
| clkA | connected to signal | rise |
589
| weA | connected to signal | high |
590
| addrA | connected to signal | |
591
| diA | connected to signal | |
592
-----------------------------------------------------------------------
593
| Port B |
594
| aspect ratio | 1920-word x 8-bit | |
595
| addrB | connected to internal node | |
596
| doB | connected to internal node | |
597
-----------------------------------------------------------------------
598
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronously. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
599
20 samiam9512
Found 1920x5-bit dual-port block RAM for signal .
600
-----------------------------------------------------------------------
601
| ram_style | Auto | |
602
-----------------------------------------------------------------------
603
| Port A |
604
| aspect ratio | 1920-word x 5-bit | |
605
| mode | read-first | |
606
| clkA | connected to signal | rise |
607
| weA | connected to signal | high |
608
| addrA | connected to signal | |
609
| diA | connected to signal | |
610
| doA | connected to signal | |
611
-----------------------------------------------------------------------
612
| Port B |
613
| aspect ratio | 1920-word x 5-bit | |
614
| mode | read-first | |
615
| clkB | connected to signal | rise |
616
| addrB | connected to internal node | |
617
| doB | connected to signal | |
618
-----------------------------------------------------------------------
619
INFO:Xst:2117 - HDL ADVISOR - Mux Selector of Case statement line 867 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
620
11 samiam9512
- add an 'INIT' attribute on signal (optimization is then done without any risk)
621
- use the attribute 'signal_encoding user' to avoid onehot optimization
622
- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
623
Found finite state machine for signal .
624
-----------------------------------------------------------------------
625
| States | 4 |
626
18 samiam9512
| Transitions | 7 |
627
| Inputs | 1 |
628
11 samiam9512
| Outputs | 6 |
629
| Clock | clk (rising_edge) |
630
18 samiam9512
| Clock enable | $not0008 (positive) |
631
| Reset | rst (positive) |
632
11 samiam9512
| Reset type | synchronous |
633
| Reset State | 00 |
634
| Encoding | automatic |
635
| Implementation | LUT |
636
-----------------------------------------------------------------------
637
20 samiam9512
WARNING:Xst:643 - "vgachr.v" line 939: The result of a 9x6-bit multiplication is partially used. Only the 11 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
638
Found 5-bit tristate buffer for signal .
639
11 samiam9512
Found 8-bit tristate buffer for signal .
640
20 samiam9512
Found 11-bit adder for signal <$add0000> created at line 922.
641
Found 9-bit subtractor for signal <$addsub0000> created at line 939.
642
Found 11-bit adder for signal <$addsub0001> created at line 939.
643
Found 11-bit comparator equal for signal <$cmp_eq0003> created at line 876.
644
Found 32-bit comparator greatequal for signal <$cmp_ge0000> created at line 808.
645
Found 7-bit comparator greatequal for signal <$cmp_ge0001> created at line 848.
646
Found 5-bit comparator greatequal for signal <$cmp_ge0002> created at line 852.
647
Found 7-bit comparator less for signal <$cmp_lt0000> created at line 848.
648
Found 5-bit comparator less for signal <$cmp_lt0001> created at line 852.
649
Found 8-bit comparator less for signal <$cmp_lt0002> created at line 939.
650
Found 9x6-bit multiplier for signal <$mult0002> created at line 939.
651
Found 16-bit 4-to-1 multiplexer for signal <$mux0000> created at line 905.
652
Found 1-bit 4-to-1 multiplexer for signal <$mux0001> created at line 898.
653
Found 1-bit 4-to-1 multiplexer for signal <$mux0002> created at line 898.
654
Found 1-bit 4-to-1 multiplexer for signal <$mux0003> created at line 898.
655
Found 1-bit 4-to-1 multiplexer for signal <$mux0004> created at line 898.
656
Found 1-bit 4-to-1 multiplexer for signal <$mux0005> created at line 898.
657
Found 1-bit 4-to-1 multiplexer for signal <$mux0006> created at line 898.
658
Found 1-bit 4-to-1 multiplexer for signal <$mux0007> created at line 898.
659
Found 1-bit 4-to-1 multiplexer for signal <$mux0008> created at line 898.
660
Found 8-bit 4-to-1 multiplexer for signal <$mux0009> created at line 877.
661
Found 1-bit xor2 for signal <$xor0000> created at line 897.
662
Found 32-bit up counter for signal .
663
Found 1-bit register for signal .
664
11 samiam9512
Found 7-bit up counter for signal .
665
18 samiam9512
Found 8-bit register for signal .
666
11 samiam9512
Found 5-bit up counter for signal .
667
18 samiam9512
Found 8-bit register for signal .
668
11 samiam9512
Found 16-bit register for signal .
669
Found 5-bit up counter for signal .
670
Found 11-bit up accumulator for signal .
671
Summary:
672
inferred 1 Finite State Machine(s).
673
20 samiam9512
inferred 3 RAM(s).
674
inferred 4 Counter(s).
675
11 samiam9512
inferred 1 Accumulator(s).
676
20 samiam9512
inferred 33 D-type flip-flop(s).
677
11 samiam9512
inferred 3 Adder/Subtractor(s).
678
inferred 1 Multiplier(s).
679
20 samiam9512
inferred 7 Comparator(s).
680
inferred 32 Multiplexer(s).
681
inferred 13 Tristate(s).
682
11 samiam9512
Unit synthesized.
683
684
685
Synthesizing Unit .
686
Related source file is "vgachr.v".
687
18 samiam9512
WARNING:Xst:646 - Signal is assigned but never used.
688
20 samiam9512
WARNING:Xst:646 - Signal > is assigned but never used.
689
18 samiam9512
WARNING:Xst:646 - Signal is assigned but never used.
690
20 samiam9512
Register equivalent to has been removed
691
11 samiam9512
Found finite state machine for signal .
692
-----------------------------------------------------------------------
693
20 samiam9512
| States | 20 |
694
| Transitions | 88 |
695
| Inputs | 21 |
696
| Outputs | 21 |
697
18 samiam9512
| Clock | clock (rising_edge) |
698
11 samiam9512
| Reset | reset (positive) |
699
| Reset type | synchronous |
700
20 samiam9512
| Reset State | 00100 |
701
11 samiam9512
| Encoding | automatic |
702
| Implementation | LUT |
703
-----------------------------------------------------------------------
704
20 samiam9512
WARNING:Xst:643 - "vgachr.v" line 682: The result of a 9x8-bit multiplication is partially used. Only the 11 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
705
Found 4x1-bit ROM for signal <$mux0023> created at line 366.
706
11 samiam9512
Found 8-bit tristate buffer for signal .
707
20 samiam9512
Found 11-bit adder for signal <$add0002> created at line 552.
708
Found 9-bit subtractor for signal <$addsub0000> created at line 682.
709
Found 11-bit adder for signal <$addsub0001> created at line 515.
710
Found 11-bit adder for signal <$addsub0002>.
711
Found 11-bit adder carry out for signal <$addsub0003> created at line 535.
712
Found 8-bit comparator greatequal for signal <$cmp_ge0000> created at line 378.
713
Found 11-bit comparator greatequal for signal <$cmp_ge0001> created at line 407.
714
Found 8-bit comparator greatequal for signal <$cmp_ge0002> created at line 679.
715
Found 8-bit comparator greatequal for signal <$cmp_ge0003> created at line 352.
716
Found 8-bit comparator greatequal for signal <$cmp_ge0004> created at line 355.
717
Found 12-bit comparator greater for signal <$cmp_gt0000> created at line 535.
718
Found 8-bit comparator greater for signal <$cmp_gt0001> created at line 701.
719
Found 11-bit comparator greater for signal <$cmp_gt0002> created at line 419.
720
Found 12-bit comparator greater for signal <$cmp_gt0003> created at line 535.
721
Found 8-bit comparator lessequal for signal <$cmp_le0000> created at line 679.
722
Found 8-bit comparator lessequal for signal <$cmp_le0001> created at line 679.
723
Found 8-bit comparator lessequal for signal <$cmp_le0002> created at line 352.
724
Found 8-bit comparator lessequal for signal <$cmp_le0003> created at line 355.
725
Found 11-bit comparator less for signal <$cmp_lt0000> created at line 392.
726
Found 11-bit comparator less for signal <$cmp_lt0001> created at line 513.
727
Found 11-bit comparator less for signal <$cmp_lt0002> created at line 549.
728
Found 11-bit comparator less for signal <$cmp_lt0003> created at line 597.
729
Found 8-bit comparator less for signal <$cmp_lt0004> created at line 701.
730
Found 11-bit comparator less for signal <$cmp_lt0005> created at line 426.
731
Found 9x8-bit multiplier for signal <$mult0002> created at line 682.
732
Found 1-bit 4-to-1 multiplexer for signal <$mux0005>.
733
Found 1-bit 8-to-1 multiplexer for signal <$mux0007>.
734
Found 11-bit addsub for signal <$share0000> created at line 366.
735
Found 10-bit subtractor for signal <$sub0000> created at line 682.
736
Found 5-bit subtractor for signal <$sub0001> created at line 702.
737
18 samiam9512
Found 1-bit register for signal .
738
11 samiam9512
Found 8-bit register for signal .
739
18 samiam9512
Found 1-bit register for signal .
740
11 samiam9512
Found 11-bit register for signal .
741
20 samiam9512
Found 5-bit tristate buffer for signal .
742
Found 8-bit register for signal .
743
11 samiam9512
Found 8-bit tristate buffer for signal .
744
Found 1-bit register for signal .
745
Found 8-bit register for signal .
746
18 samiam9512
Found 1-bit register for signal .
747
11 samiam9512
Found 1-bit register for signal .
748
20 samiam9512
Found 5-bit register for signal .
749
11 samiam9512
Found 11-bit register for signal .
750
Found 8-bit register for signal .
751
18 samiam9512
Found 1-bit register for signal .
752
20 samiam9512
Found 1-bit register for signal .
753
18 samiam9512
Found 1-bit register for signal .
754
Found 1-bit register for signal .
755
11 samiam9512
Found 1-bit register for signal .
756
18 samiam9512
Found 1-bit register for signal .
757
Found 1-bit register for signal .
758
Found 1-bit register for signal .
759
20 samiam9512
Found 8-bit register for signal .
760
18 samiam9512
Found 1-bit register for signal .
761
Found 11-bit register for signal .
762
11 samiam9512
Found 1-bit register for signal .
763
Summary:
764
inferred 1 Finite State Machine(s).
765
20 samiam9512
inferred 1 ROM(s).
766
inferred 93 D-type flip-flop(s).
767
inferred 8 Adder/Subtractor(s).
768
inferred 1 Multiplier(s).
769
inferred 19 Comparator(s).
770
inferred 2 Multiplexer(s).
771
inferred 21 Tristate(s).
772
11 samiam9512
Unit synthesized.
773
774
775
2 samiam9512
Synthesizing Unit .
776
Related source file is "testbench.v".
777
Unit synthesized.
778
779
INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
780
781
=========================================================================
782
HDL Synthesis Report
783
784
Macro Statistics
785
20 samiam9512
# RAMs : 4
786
2 samiam9512
1024x8-bit single-port block RAM : 1
787
20 samiam9512
1920x5-bit dual-port block RAM : 1
788
11 samiam9512
1920x8-bit dual-port distributed RAM : 1
789
18 samiam9512
1920x8-bit single-port block RAM : 1
790
20 samiam9512
# ROMs : 4
791
11 samiam9512
128x8-bit ROM : 1
792
2048x8-bit ROM : 1
793
18 samiam9512
4x1-bit ROM : 2
794
20 samiam9512
# Multipliers : 2
795
11 samiam9512
9x6-bit multiplier : 1
796
20 samiam9512
9x8-bit multiplier : 1
797
# Adders/Subtractors : 56
798
10-bit subtractor : 1
799
18 samiam9512
11-bit adder : 5
800
11-bit adder carry out : 1
801
11-bit addsub : 1
802
13-bit adder : 1
803
11 samiam9512
16-bit adder : 7
804
2 samiam9512
16-bit addsub : 1
805
16-bit subtractor : 1
806
17-bit adder : 8
807
32-bit adder : 6
808
32-bit subtractor : 3
809
4-bit adder carry out : 2
810
5-bit adder : 1
811
20 samiam9512
5-bit subtractor : 1
812
2 samiam9512
6-bit adder : 1
813
6-bit subtractor : 2
814
8-bit adder : 1
815
8-bit adder carry out : 3
816
8-bit addsub : 3
817
9-bit adder : 3
818
20 samiam9512
9-bit subtractor : 4
819
# Counters : 6
820
32-bit up counter : 1
821
18 samiam9512
4-bit up counter : 1
822
11 samiam9512
5-bit up counter : 2
823
7-bit up counter : 1
824
18 samiam9512
8-bit up counter : 1
825
11 samiam9512
# Accumulators : 1
826
11-bit up accumulator : 1
827
20 samiam9512
# Registers : 104
828
1-bit register : 51
829
18 samiam9512
10-bit register : 1
830
11-bit register : 3
831
13-bit register : 1
832
11 samiam9512
16-bit register : 9
833
2 samiam9512
2-bit register : 1
834
11 samiam9512
3-bit register : 4
835
2 samiam9512
4-bit register : 1
836
20 samiam9512
5-bit register : 2
837
2 samiam9512
6-bit register : 1
838
20 samiam9512
8-bit register : 29
839
11 samiam9512
9-bit register : 1
840
2 samiam9512
# Latches : 12
841
6-bit latch : 4
842
8-bit latch : 8
843
20 samiam9512
# Comparators : 33
844
18 samiam9512
11-bit comparator equal : 1
845
11-bit comparator greatequal : 1
846
11-bit comparator greater : 1
847
11-bit comparator less : 5
848
12-bit comparator greater : 2
849
20 samiam9512
32-bit comparator greatequal : 1
850
2 samiam9512
4-bit comparator equal : 1
851
4-bit comparator greater : 2
852
11 samiam9512
5-bit comparator greatequal : 1
853
5-bit comparator less : 1
854
2 samiam9512
6-bit comparator equal : 4
855
11 samiam9512
7-bit comparator greatequal : 1
856
7-bit comparator less : 1
857
20 samiam9512
8-bit comparator greatequal : 4
858
8-bit comparator greater : 1
859
8-bit comparator less : 2
860
8-bit comparator lessequal : 4
861
# Multiplexers : 32
862
1-bit 4-to-1 multiplexer : 17
863
1-bit 8-to-1 multiplexer : 3
864
16-bit 4-to-1 multiplexer : 1
865
2 samiam9512
3-bit 4-to-1 multiplexer : 4
866
20 samiam9512
8-bit 4-to-1 multiplexer : 4
867
2 samiam9512
8-bit 8-to-1 multiplexer : 3
868
20 samiam9512
# Tristates : 14
869
5-bit tristate buffer : 2
870
18 samiam9512
8-bit tristate buffer : 12
871
20 samiam9512
# Xors : 3
872
1-bit xor2 : 1
873
2 samiam9512
1-bit xor8 : 1
874
8-bit xor2 : 1
875
876
=========================================================================
877
878
=========================================================================
879
* Advanced HDL Synthesis *
880
=========================================================================
881
882
11 samiam9512
Analyzing FSM for best encoding.
883
20 samiam9512
Optimizing FSM on signal with one-hot encoding.
884
-------------------------------
885
18 samiam9512
State | Encoding
886
20 samiam9512
-------------------------------
887
00000 | 00000000000000100000
888
00001 | 00000000000000000010
889
00010 | 00000000000001000000
890
00011 | 00000000000010000000
891
00100 | 00000000000000000001
892
00101 | 00000000000100000000
893
00110 | 00000000001000000000
894
00111 | 00000000010000000000
895
01000 | 00000000000000001000
896
01001 | 00000000000000000100
897
01010 | 00000000100000000000
898
01011 | 00000010000000000000
899
01100 | 00000100000000000000
900
01101 | 00001000000000000000
901
01110 | 00000001000000000000
902
01111 | 00010000000000000000
903
10000 | 00000000000000010000
904
10001 | 00100000000000000000
905
10010 | 10000000000000000000
906
10011 | 01000000000000000000
907
-------------------------------
908
11 samiam9512
Analyzing FSM for best encoding.
909
Optimizing FSM on signal with gray encoding.
910
-------------------
911
State | Encoding
912
-------------------
913
00 | 00
914
01 | 01
915
10 | 11
916
11 | 10
917
-------------------
918
9 samiam9512
Analyzing FSM for best encoding.
919
18 samiam9512
Optimizing FSM on signal with speed1 encoding.
920
------------------------------------------------
921
State | Encoding
922
------------------------------------------------
923
000001 | 000001000000000000000000000000000000
924
000010 | 000000100000000000000000000000000000
925
000011 | 100000000000000000000000000000000000
926
000100 | 000100000000000000000000000000000000
927
000101 | 000000000001000000000000000000000000
928
000110 | 010000000000100000000000000000000000
929
000111 | 010000001000000000000000000000000000
930
001000 | 010000000000000001000000000000000000
931
001001 | 010000000000000000010000000000000000
932
001010 | 010000000000000000000100000000000000
933
001011 | 010000000000000000000010000000000000
934
001100 | 000010000000000000001000000000000000
935
001101 | 010000000000000000000000000100000000
936
001110 | 000000000100000000000000000000000000
937
001111 | 000000000000010000000000000000000000
938
010000 | 000000000000001000000000000000000000
939
010001 | 000010000000000100000000000000000000
940
010010 | 000000000010000000000000000000000000
941
010011 | 000000000000000000000000000000000100
942
010100 | 001010000000000000000000000000000000
943
010101 | 010000000000000000000001000000000000
944
010110 | 000000000000000000000000000001000000
945
010111 | 000000000000000000000000000000000001
946
011000 | 010000000000000000000000000010000000
947
011001 | 000000000000000000000000000000010000
948
011010 | 000000000000000000000000000000100000
949
011011 | 000000000000000000000000000000001000
950
011100 | 010000000000000000000000000000000010
951
011101 | 000010000000000010000000000000000000
952
011110 | 000010000000000000000000100000000000
953
011111 | 000010000000000000000000001000000000
954
0XXXXX | unreached
955
100000 | 000010000000000000100000000000000000
956
100001 | 000000000000000000000000010000000000
957
100010 | 010000010000000000000000000000000000
958
------------------------------------------------
959
9 samiam9512
Analyzing FSM for best encoding.
960
Optimizing FSM on signal with gray encoding.
961
-------------------
962
State | Encoding
963
-------------------
964
0000 | 00
965
0001 | 01
966
0010 | 11
967
-------------------
968
11 samiam9512
Loading device for application Rf_Device from file '3s1000.nph' in environment C:\Xilinx.
969
18 samiam9512
WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block .
970
11 samiam9512
WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block .
971
20 samiam9512
WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block .
972
9 samiam9512
INFO:Xst:1651 - Address input of ROM is tied to register .
973
INFO:Xst:1650 - The register is removed and the ROM is implemented as read-only block RAM.
974
2 samiam9512
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block .
975
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .
976
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .
977
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .
978
18 samiam9512
INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 8 FFs/Latches, which will be removed :
979
20 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
980
WARNING:Xst:1291 - FF/Latch is unconnected in block .
981
WARNING:Xst:1291 - FF/Latch is unconnected in block .
982
11 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
983
2 samiam9512
984
=========================================================================
985
Advanced HDL Synthesis Report
986
987
Macro Statistics
988
11 samiam9512
# FSMs : 4
989
20 samiam9512
# RAMs : 5
990
2 samiam9512
1024x8-bit single-port block RAM : 1
991
11 samiam9512
128x8-bit single-port block RAM : 1
992
20 samiam9512
1920x5-bit dual-port block RAM : 1
993
11 samiam9512
1920x8-bit dual-port distributed RAM : 1
994
18 samiam9512
1920x8-bit single-port block RAM : 1
995
20 samiam9512
# ROMs : 3
996
11 samiam9512
2048x8-bit ROM : 1
997
18 samiam9512
4x1-bit ROM : 2
998
20 samiam9512
# Multipliers : 2
999
11 samiam9512
9x6-bit multiplier : 1
1000
20 samiam9512
9x8-bit multiplier : 1
1001
# Adders/Subtractors : 56
1002
10-bit subtractor : 1
1003
18 samiam9512
11-bit adder : 5
1004
11-bit adder carry out : 1
1005
11-bit addsub : 1
1006
13-bit adder : 1
1007
11 samiam9512
16-bit adder : 7
1008
2 samiam9512
16-bit addsub : 1
1009
16-bit subtractor : 1
1010
17-bit adder : 8
1011
32-bit adder : 6
1012
32-bit subtractor : 3
1013
4-bit adder carry out : 2
1014
5-bit adder : 1
1015
20 samiam9512
5-bit subtractor : 1
1016
2 samiam9512
6-bit adder : 1
1017
6-bit subtractor : 2
1018
8-bit adder : 1
1019
8-bit adder carry out : 3
1020
8-bit addsub : 3
1021
9-bit adder : 3
1022
20 samiam9512
9-bit subtractor : 4
1023
# Counters : 6
1024
32-bit up counter : 1
1025
18 samiam9512
4-bit up counter : 1
1026
11 samiam9512
5-bit up counter : 2
1027
7-bit up counter : 1
1028
18 samiam9512
8-bit up counter : 1
1029
11 samiam9512
# Accumulators : 1
1030
11-bit up accumulator : 1
1031
20 samiam9512
# Registers : 575
1032
Flip-Flops : 575
1033
2 samiam9512
# Latches : 12
1034
6-bit latch : 4
1035
8-bit latch : 8
1036
20 samiam9512
# Comparators : 33
1037
18 samiam9512
11-bit comparator equal : 1
1038
11-bit comparator greatequal : 1
1039
11-bit comparator greater : 1
1040
11-bit comparator less : 5
1041
12-bit comparator greater : 2
1042
20 samiam9512
32-bit comparator greatequal : 1
1043
2 samiam9512
4-bit comparator equal : 1
1044
4-bit comparator greater : 2
1045
11 samiam9512
5-bit comparator greatequal : 1
1046
5-bit comparator less : 1
1047
2 samiam9512
6-bit comparator equal : 4
1048
11 samiam9512
7-bit comparator greatequal : 1
1049
7-bit comparator less : 1
1050
20 samiam9512
8-bit comparator greatequal : 4
1051
8-bit comparator greater : 1
1052
8-bit comparator less : 2
1053
8-bit comparator lessequal : 4
1054
# Multiplexers : 32
1055
1-bit 4-to-1 multiplexer : 17
1056
1-bit 8-to-1 multiplexer : 3
1057
16-bit 4-to-1 multiplexer : 1
1058
2 samiam9512
3-bit 4-to-1 multiplexer : 4
1059
20 samiam9512
8-bit 4-to-1 multiplexer : 4
1060
2 samiam9512
8-bit 8-to-1 multiplexer : 3
1061
20 samiam9512
# Xors : 3
1062
1-bit xor2 : 1
1063
2 samiam9512
1-bit xor8 : 1
1064
8-bit xor2 : 1
1065
1066
=========================================================================
1067
1068
=========================================================================
1069
* Low Level Synthesis *
1070
=========================================================================
1071
20 samiam9512
WARNING:Xst:1988 - Unit : instances , of unit and unit are dual, second instance is removed
1072
WARNING:Xst:1988 - Unit : instances , of unit and unit are dual, second instance is removed
1073
WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed
1074
11 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1075
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1076
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1077
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1078
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1079
20 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1080
11 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1081
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1082
20 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1083
11 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1084
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1085
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1086
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1087
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1088
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1089
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1090
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1091
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1092
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1093
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1094
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1095
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1096
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1097
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1098
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1099
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1100
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1101
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1102
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1103
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1104
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1105
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1106
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1107
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1108
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1109
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1110
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1111
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1112
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1113
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1114
20 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1115
11 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1116
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1117
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1118
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1119
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1120
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1121
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1122
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1123
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1124
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1125
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1126
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1127
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1128
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1129
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1130
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1131
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1132
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1133
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1134
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1135
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1136
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1137
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1138
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1139
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1140
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1141
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1142
20 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1143
11 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1144
20 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1145
11 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1146
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1147
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1148
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1149
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1150
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1151
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1152
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1153
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1154
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1155
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1156
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1157
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1158
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1159
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1160
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1161
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1162
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1163
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1164
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1165
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1166
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1167
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1168
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1169
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1170
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1171
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1172
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1173
20 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1174
11 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1175
20 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1176
11 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1177
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1178
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1179
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1180
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1181
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1182
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1183
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1184
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1185
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1186
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1187
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1188
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1189
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1190
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1191
20 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1192
11 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1193
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1194
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1195
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1196
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1197
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1198
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1199
18 samiam9512
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block .
1200
11 samiam9512
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .
1201
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .
1202
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .
1203
20 samiam9512
WARNING:Xst:2040 - Unit testbench: 21 multi-source signals are replaced by logic (pull-up yes): adm3a/cmattr<0>, adm3a/cmattr<1>, adm3a/cmattr<2>, adm3a/cmattr<3>, adm3a/cmattr<4>, adm3a/cmdata<0>, adm3a/cmdata<1>, adm3a/cmdata<2>, adm3a/cmdata<3>, adm3a/cmdata<4>, adm3a/cmdata<5>, adm3a/cmdata<6>, adm3a/cmdata<7>, N185, N187, N189, N1911, N193, N195, N197, N199.
1204
WARNING:Xst:2042 - Unit chrmemmap: 13 internal tristates are replaced by logic (pull-up yes): attr<0>, attr<1>, attr<2>, attr<3>, attr<4>, data<0>, data<1>, data<2>, data<3>, data<4>, data<5>, data<6>, data<7>.
1205
2 samiam9512
1206
Optimizing unit ...
1207
1208
18 samiam9512
Optimizing unit ...
1209
1210
Optimizing unit ...
1211
1212
11 samiam9512
Optimizing unit ...
1213
1214
Optimizing unit ...
1215
1216
Optimizing unit ...
1217
1218
2 samiam9512
Mapping all equations...
1219
11 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1220
2 samiam9512
Building and optimizing final netlist ...
1221
18 samiam9512
Found area constraint ratio of 100 (+ 5) on block testbench, actual ratio is 32.
1222
11 samiam9512
FlipFlop adm3a/cmaddr_0 has been replicated 5 time(s)
1223
FlipFlop adm3a/cmaddr_1 has been replicated 5 time(s)
1224
FlipFlop adm3a/cmaddr_2 has been replicated 5 time(s)
1225
FlipFlop adm3a/cmaddr_3 has been replicated 5 time(s)
1226
18 samiam9512
FlipFlop adm3a/display/chrcnt_0 has been replicated 1 time(s)
1227
FlipFlop adm3a/display/chrcnt_1 has been replicated 1 time(s)
1228
FlipFlop adm3a/display/chrcnt_2 has been replicated 1 time(s)
1229
FlipFlop adm3a/display/chrcnt_3 has been replicated 1 time(s)
1230
FlipFlop adm3a/vgai/sc_r_0 has been replicated 1 time(s)
1231
20 samiam9512
FlipFlop adm3a/vgai/sc_r_1 has been replicated 1 time(s)
1232
18 samiam9512
FlipFlop adm3a/vgai/sc_r_3 has been replicated 1 time(s)
1233
20 samiam9512
FlipFlop adm3a/vgai/sc_r_4 has been replicated 1 time(s)
1234
FlipFlop adm3a/vgai/sc_r_5 has been replicated 1 time(s)
1235
FlipFlop adm3a/vgai/sc_r_6 has been replicated 1 time(s)
1236
FlipFlop adm3a/vgai/sc_r_7 has been replicated 1 time(s)
1237
18 samiam9512
FlipFlop cpu/addr_0 has been replicated 1 time(s)
1238
20 samiam9512
FlipFlop cpu/addr_1 has been replicated 2 time(s)
1239
18 samiam9512
FlipFlop cpu/addr_2 has been replicated 2 time(s)
1240
9 samiam9512
FlipFlop cpu/addr_3 has been replicated 1 time(s)
1241
20 samiam9512
FlipFlop cpu/readio has been replicated 1 time(s)
1242
2 samiam9512
1243
Final Macro Processing ...
1244
1245
11 samiam9512
Processing Unit :
1246
20 samiam9512
INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
1247
18 samiam9512
INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
1248
20 samiam9512
INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
1249
18 samiam9512
INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
1250
11 samiam9512
INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
1251
INFO:Xst:2387 - HDL ADVISOR - A 3-bit shift register was found for signal and currently occupies 3 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
1252
Unit processed.
1253
1254
2 samiam9512
=========================================================================
1255
Final Register Report
1256
1257
Macro Statistics
1258
20 samiam9512
# Registers : 668
1259
Flip-Flops : 668
1260
2 samiam9512
1261
=========================================================================
1262
1263
=========================================================================
1264
* Partition Report *
1265
=========================================================================
1266
1267
Partition Implementation Status
1268
-------------------------------
1269
1270
No Partitions were found in this design.
1271
1272
-------------------------------
1273
1274
=========================================================================
1275
* Final Report *
1276
=========================================================================
1277
Final Results
1278
RTL Top Level Output File Name : testbench.ngr
1279
Top Level Output File Name : testbench
1280
Output Format : NGC
1281
Optimization Goal : Speed
1282
Keep Hierarchy : NO
1283
1284
Design Statistics
1285
18 samiam9512
# IOs : 54
1286
2 samiam9512
1287
Cell Usage :
1288
20 samiam9512
# BELS : 6537
1289
2 samiam9512
# GND : 1
1290
20 samiam9512
# INV : 104
1291
# LUT1 : 233
1292
# LUT2 : 416
1293
# LUT2_D : 34
1294
# LUT2_L : 11
1295
# LUT3 : 1128
1296
# LUT3_D : 36
1297
# LUT3_L : 29
1298
# LUT4 : 2320
1299
# LUT4_D : 88
1300
# LUT4_L : 235
1301
2 samiam9512
# MULT_AND : 28
1302
20 samiam9512
# MUXCY : 662
1303
# MUXF5 : 609
1304
# MUXF6 : 175
1305
# MUXF7 : 59
1306
11 samiam9512
# MUXF8 : 23
1307
2 samiam9512
# VCC : 1
1308
20 samiam9512
# XORCY : 345
1309
# FlipFlops/Latches : 756
1310
18 samiam9512
# FD : 7
1311
# FDC : 23
1312
20 samiam9512
# FDCE : 62
1313
# FDE : 324
1314
18 samiam9512
# FDE_1 : 8
1315
# FDP : 6
1316
# FDPE : 21
1317
20 samiam9512
# FDR : 75
1318
# FDRE : 39
1319
18 samiam9512
# FDRE_1 : 42
1320
20 samiam9512
# FDRS : 47
1321
# FDRSE : 10
1322
18 samiam9512
# FDS : 3
1323
9 samiam9512
# FDSE : 1
1324
11 samiam9512
# LDCE : 56
1325
# LDE_1 : 32
1326
20 samiam9512
# RAMS : 844
1327
11 samiam9512
# RAM16X1D : 840
1328
18 samiam9512
# RAMB16_S9 : 3
1329
20 samiam9512
# RAMB16_S9_S9 : 1
1330
18 samiam9512
# Clock Buffers : 2
1331
2 samiam9512
# BUFGP : 2
1332
18 samiam9512
# IO Buffers : 52
1333
# IBUF : 2
1334
2 samiam9512
# IOBUF : 8
1335
18 samiam9512
# OBUF : 42
1336
20 samiam9512
# MULTs : 2
1337
# MULT18X18 : 2
1338
2 samiam9512
=========================================================================
1339
1340
Device utilization summary:
1341
---------------------------
1342
1343
11 samiam9512
Selected Device : 3s1000ft256-4
1344
2 samiam9512
1345
20 samiam9512
Number of Slices: 2421 out of 7680 31%
1346
Number of Slice Flip Flops: 756 out of 15360 4%
1347
Number of 4 input LUTs: 6314 out of 15360 41%
1348
Number used as logic: 4634
1349
11 samiam9512
Number used as RAMs: 1680
1350
18 samiam9512
Number of IOs: 54
1351
Number of bonded IOBs: 54 out of 173 31%
1352
20 samiam9512
Number of BRAMs: 4 out of 24 16%
1353
Number of MULT18X18s: 2 out of 24 8%
1354
18 samiam9512
Number of GCLKs: 2 out of 8 25%
1355
2 samiam9512
1356
1357
=========================================================================
1358
TIMING REPORT
1359
1360
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
1361
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
1362
GENERATED AFTER PLACE-and-ROUTE.
1363
1364
Clock Information:
1365
------------------
1366
-----------------------------------------------------+--------------------------------+-------+
1367
Clock Signal | Clock buffer(FF name) | Load |
1368
-----------------------------------------------------+--------------------------------+-------+
1369
20 samiam9512
clock | BUFGP | 1509 |
1370
11 samiam9512
reset_n | BUFGP | 32 |
1371
20 samiam9512
select1/selectd/_and0000(select1/selectd/_and00001:O)| NONE(*)(select1/selectd/mask_2)| 14 |
1372
select1/selectc/_and0000(select1/selectc/_and00001:O)| NONE(*)(select1/selectc/mask_2)| 14 |
1373
select1/selectb/_and0000(select1/selectb/_and00001:O)| NONE(*)(select1/selectb/comp_0)| 14 |
1374
select1/selecta/_and0000(select1/selecta/_and00001:O)| NONE(*)(select1/selecta/comp_2)| 14 |
1375
2 samiam9512
-----------------------------------------------------+--------------------------------+-------+
1376
(*) These 4 clock signal(s) are generated by combinatorial logic,
1377
and XST is not able to identify which are the primary clock signals.
1378
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
1379
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
1380
1381
Asynchronous Control Signals Information:
1382
----------------------------------------
1383
20 samiam9512
-----------------------------------+----------------------------------------------------+-------+
1384
Control Signal | Buffer(FF name) | Load |
1385
-----------------------------------+----------------------------------------------------+-------+
1386
reset(reset1_INV_0:O) | NONE(adm3a/display/vgai/gen_syncs_fit.vsync/sync_r)| 168 |
1387
-----------------------------------+----------------------------------------------------+-------+
1388
2 samiam9512
1389
Timing Summary:
1390
---------------
1391
11 samiam9512
Speed Grade: -4
1392
2 samiam9512
1393
20 samiam9512
Minimum period: 21.398ns (Maximum Frequency: 46.733MHz)
1394
Minimum input arrival time before clock: 8.800ns
1395
Maximum output required time after clock: 20.238ns
1396
18 samiam9512
Maximum combinational path delay: 7.342ns
1397
2 samiam9512
1398
Timing Detail:
1399
--------------
1400
All values displayed in nanoseconds (ns)
1401
1402
=========================================================================
1403
Timing constraint: Default period analysis for Clock 'clock'
1404
20 samiam9512
Clock period: 21.398ns (frequency: 46.733MHz)
1405
Total number of paths / destination ports: 244771 / 9411
1406
2 samiam9512
-------------------------------------------------------------------------
1407
20 samiam9512
Delay: 10.699ns (Levels of Logic = 6)
1408
18 samiam9512
Source: cpu/addr_10 (FF)
1409
Destination: intc/active_7 (FF)
1410
2 samiam9512
Source Clock: clock rising
1411
18 samiam9512
Destination Clock: clock falling
1412
2 samiam9512
1413
18 samiam9512
Data Path: cpu/addr_10 to intc/active_7
1414
2 samiam9512
Gate Net
1415
Cell:in->out fanout Delay Delay Logical Name (Net Name)
1416
---------------------------------------- ------------
1417
20 samiam9512
FDE:C->Q 6 0.720 1.071 cpu/addr_10 (cpu/addr_10)
1418
LUT4:I2->O 1 0.551 0.000 select1/selectc/selectout1511 (N17364)
1419
MUXF5:I1->O 2 0.360 1.216 select1/selectc/selectout151_f5 (select1/selectc/selectout_map6043)
1420
LUT4_D:I0->O 1 0.551 0.827 select1/selectc/selectout169_1 (select1/selectc/selectout169)
1421
LUT4_D:I3->O 14 0.551 1.255 intc/_xor00151 (intc/_xor0015)
1422
LUT4_D:I2->O 7 0.551 1.092 intc/_not00161 (N2811)
1423
LUT4:I3->O 1 0.551 0.801 intc/_not0016 (intc/_not0016)
1424
FDRE_1:CE 0.602 intc/active_7
1425
2 samiam9512
----------------------------------------
1426
20 samiam9512
Total 10.699ns (4.437ns logic, 6.262ns route)
1427
(41.5% logic, 58.5% route)
1428
2 samiam9512
1429
=========================================================================
1430
Timing constraint: Default OFFSET IN BEFORE for Clock 'clock'
1431
20 samiam9512
Total number of paths / destination ports: 633 / 633
1432
2 samiam9512
-------------------------------------------------------------------------
1433
20 samiam9512
Offset: 8.800ns (Levels of Logic = 2)
1434
11 samiam9512
Source: reset_n (PAD)
1435
18 samiam9512
Destination: cpu/readmem (FF)
1436
2 samiam9512
Destination Clock: clock rising
1437
1438
18 samiam9512
Data Path: reset_n to cpu/readmem
1439
2 samiam9512
Gate Net
1440
Cell:in->out fanout Delay Delay Logical Name (Net Name)
1441
---------------------------------------- ------------
1442
20 samiam9512
BUFGP:I->O 240 0.401 3.045 reset_n_BUFGP (reset_n_BUFGP)
1443
INV:I->O 368 0.551 3.778 reset1_INV_0 (reset)
1444
18 samiam9512
FDRSE:R 1.026 cpu/writemem
1445
2 samiam9512
----------------------------------------
1446
20 samiam9512
Total 8.800ns (1.978ns logic, 6.822ns route)
1447
(22.5% logic, 77.5% route)
1448
2 samiam9512
1449
=========================================================================
1450
Timing constraint: Default OFFSET IN BEFORE for Clock 'select1/selectd/_and0000'
1451
11 samiam9512
Total number of paths / destination ports: 14 / 14
1452
2 samiam9512
-------------------------------------------------------------------------
1453
11 samiam9512
Offset: 2.474ns (Levels of Logic = 1)
1454
Source: data<6> (PAD)
1455
Destination: select1/selectd/mask_6 (LATCH)
1456
2 samiam9512
Destination Clock: select1/selectd/_and0000 falling
1457
1458
11 samiam9512
Data Path: data<6> to select1/selectd/mask_6
1459
2 samiam9512
Gate Net
1460
Cell:in->out fanout Delay Delay Logical Name (Net Name)
1461
---------------------------------------- ------------
1462
20 samiam9512
IOBUF:IO->O 19 0.821 1.450 data_6_IOBUF (N15524)
1463
11 samiam9512
LDCE:D 0.203 select1/selectd/mask_6
1464
2 samiam9512
----------------------------------------
1465
11 samiam9512
Total 2.474ns (1.024ns logic, 1.450ns route)
1466
(41.4% logic, 58.6% route)
1467
2 samiam9512
1468
=========================================================================
1469
Timing constraint: Default OFFSET IN BEFORE for Clock 'select1/selectc/_and0000'
1470
9 samiam9512
Total number of paths / destination ports: 14 / 14
1471
2 samiam9512
-------------------------------------------------------------------------
1472
11 samiam9512
Offset: 2.474ns (Levels of Logic = 1)
1473
Source: data<6> (PAD)
1474
Destination: select1/selectc/mask_6 (LATCH)
1475
2 samiam9512
Destination Clock: select1/selectc/_and0000 falling
1476
1477
11 samiam9512
Data Path: data<6> to select1/selectc/mask_6
1478
2 samiam9512
Gate Net
1479
Cell:in->out fanout Delay Delay Logical Name (Net Name)
1480
---------------------------------------- ------------
1481
20 samiam9512
IOBUF:IO->O 19 0.821 1.450 data_6_IOBUF (N15524)
1482
11 samiam9512
LDCE:D 0.203 select1/selectc/mask_6
1483
2 samiam9512
----------------------------------------
1484
11 samiam9512
Total 2.474ns (1.024ns logic, 1.450ns route)
1485
(41.4% logic, 58.6% route)
1486
2 samiam9512
1487
=========================================================================
1488
Timing constraint: Default OFFSET IN BEFORE for Clock 'select1/selectb/_and0000'
1489
Total number of paths / destination ports: 14 / 14
1490
-------------------------------------------------------------------------
1491
11 samiam9512
Offset: 2.474ns (Levels of Logic = 1)
1492
Source: data<6> (PAD)
1493
Destination: select1/selectb/mask_6 (LATCH)
1494
2 samiam9512
Destination Clock: select1/selectb/_and0000 falling
1495
1496
11 samiam9512
Data Path: data<6> to select1/selectb/mask_6
1497
2 samiam9512
Gate Net
1498
Cell:in->out fanout Delay Delay Logical Name (Net Name)
1499
---------------------------------------- ------------
1500
20 samiam9512
IOBUF:IO->O 19 0.821 1.450 data_6_IOBUF (N15524)
1501
11 samiam9512
LDCE:D 0.203 select1/selectb/mask_6
1502
2 samiam9512
----------------------------------------
1503
11 samiam9512
Total 2.474ns (1.024ns logic, 1.450ns route)
1504
(41.4% logic, 58.6% route)
1505
2 samiam9512
1506
=========================================================================
1507
Timing constraint: Default OFFSET IN BEFORE for Clock 'select1/selecta/_and0000'
1508
Total number of paths / destination ports: 14 / 14
1509
-------------------------------------------------------------------------
1510
11 samiam9512
Offset: 2.474ns (Levels of Logic = 1)
1511
Source: data<6> (PAD)
1512
Destination: select1/selecta/mask_6 (LATCH)
1513
2 samiam9512
Destination Clock: select1/selecta/_and0000 falling
1514
1515
11 samiam9512
Data Path: data<6> to select1/selecta/mask_6
1516
2 samiam9512
Gate Net
1517
Cell:in->out fanout Delay Delay Logical Name (Net Name)
1518
---------------------------------------- ------------
1519
20 samiam9512
IOBUF:IO->O 19 0.821 1.450 data_6_IOBUF (N15524)
1520
11 samiam9512
LDCE:D 0.203 select1/selecta/mask_6
1521
2 samiam9512
----------------------------------------
1522
11 samiam9512
Total 2.474ns (1.024ns logic, 1.450ns route)
1523
(41.4% logic, 58.6% route)
1524
2 samiam9512
1525
=========================================================================
1526
18 samiam9512
Timing constraint: Default OFFSET OUT AFTER for Clock 'clock'
1527
Total number of paths / destination ports: 2401 / 47
1528
2 samiam9512
-------------------------------------------------------------------------
1529
20 samiam9512
Offset: 20.238ns (Levels of Logic = 10)
1530
Source: cpu/addr_2 (FF)
1531
2 samiam9512
Destination: data<7> (PAD)
1532
18 samiam9512
Source Clock: clock rising
1533
2 samiam9512
1534
20 samiam9512
Data Path: cpu/addr_2 to data<7>
1535
2 samiam9512
Gate Net
1536
Cell:in->out fanout Delay Delay Logical Name (Net Name)
1537
---------------------------------------- ------------
1538
20 samiam9512
FDE:C->Q 29 0.720 2.031 cpu/addr_2 (cpu/addr_2)
1539
LUT4:I1->O 1 0.551 0.000 _and0000_inv168_SW01 (N17393)
1540
MUXF5:I1->O 2 0.360 0.903 _and0000_inv168_SW0_f5 (N16510)
1541
LUT4:I3->O 1 0.551 0.000 _and0000_inv1682 (N17396)
1542
MUXF5:I0->O 1 0.360 0.827 _and0000_inv168_f5 (_and0000_inv_map5607)
1543
LUT4:I3->O 9 0.551 1.192 _and0000_inv211 (_and0000_inv)
1544
LUT4:I2->O 1 0.551 1.140 N185LogicTrst120 (N185LogicTrst1_map5693)
1545
LUT4:I0->O 1 0.551 0.827 N185LogicTrst142_SW0 (N17018)
1546
LUT4:I3->O 16 0.551 1.576 N185LogicTrst142 (N256)
1547
LUT3:I0->O 1 0.551 0.801 N197LogicTrst115 (data_1_IOBUF)
1548
18 samiam9512
IOBUF:I->IO 5.644 data_1_IOBUF (data<1>)
1549
2 samiam9512
----------------------------------------
1550
20 samiam9512
Total 20.238ns (10.941ns logic, 9.297ns route)
1551
(54.1% logic, 45.9% route)
1552
2 samiam9512
1553
=========================================================================
1554
18 samiam9512
Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selectc/_and0000'
1555
20 samiam9512
Total number of paths / destination ports: 552 / 8
1556
2 samiam9512
-------------------------------------------------------------------------
1557
20 samiam9512
Offset: 16.200ns (Levels of Logic = 7)
1558
18 samiam9512
Source: select1/selectc/mask_1 (LATCH)
1559
2 samiam9512
Destination: data<7> (PAD)
1560
18 samiam9512
Source Clock: select1/selectc/_and0000 falling
1561
2 samiam9512
1562
18 samiam9512
Data Path: select1/selectc/mask_1 to data<7>
1563
2 samiam9512
Gate Net
1564
Cell:in->out fanout Delay Delay Logical Name (Net Name)
1565
---------------------------------------- ------------
1566
20 samiam9512
LDCE:G->Q 7 0.633 1.405 select1/selectc/mask_1 (select1/selectc/mask_1)
1567
LUT4:I0->O 1 0.551 0.000 select1/selectc/selectout1511 (N17364)
1568
MUXF5:I1->O 2 0.360 1.216 select1/selectc/selectout151_f5 (select1/selectc/selectout_map6043)
1569
LUT4_D:I0->LO 1 0.551 0.126 select1/selectc/selectout169_1 (N17618)
1570
LUT4:I3->O 17 0.551 1.684 intc/_not0027_SW0 (intc/_and0009)
1571
LUT4:I0->O 16 0.551 1.576 N185LogicTrst142 (N256)
1572
LUT3:I0->O 1 0.551 0.801 N197LogicTrst115 (data_1_IOBUF)
1573
18 samiam9512
IOBUF:I->IO 5.644 data_1_IOBUF (data<1>)
1574
2 samiam9512
----------------------------------------
1575
20 samiam9512
Total 16.200ns (9.392ns logic, 6.808ns route)
1576
(58.0% logic, 42.0% route)
1577
2 samiam9512
1578
=========================================================================
1579
Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selectb/_and0000'
1580
11 samiam9512
Total number of paths / destination ports: 840 / 8
1581
2 samiam9512
-------------------------------------------------------------------------
1582
20 samiam9512
Offset: 17.126ns (Levels of Logic = 8)
1583
11 samiam9512
Source: select1/selectb/comp_1 (LATCH)
1584
2 samiam9512
Destination: data<7> (PAD)
1585
Source Clock: select1/selectb/_and0000 falling
1586
1587
11 samiam9512
Data Path: select1/selectb/comp_1 to data<7>
1588
2 samiam9512
Gate Net
1589
Cell:in->out fanout Delay Delay Logical Name (Net Name)
1590
---------------------------------------- ------------
1591
11 samiam9512
LDCE:G->Q 3 0.633 1.246 select1/selectb/comp_1 (select1/selectb/comp_1)
1592
20 samiam9512
LUT4:I0->O 1 0.551 0.000 select1/select248_SW02 (N17390)
1593
MUXF5:I0->O 2 0.360 1.216 select1/select248_SW0_f5 (N16508)
1594
LUT4:I0->O 1 0.551 0.000 select1/select2482 (N17392)
1595
MUXF5:I0->O 2 0.360 1.216 select1/select248_f5 (select1/select2_map5499)
1596
18 samiam9512
LUT4:I0->O 9 0.551 1.319 ram/_and0000_inv1 (ram/_and0000_inv)
1597
20 samiam9512
LUT4:I1->O 16 0.551 1.576 N185LogicTrst142 (N256)
1598
LUT3:I0->O 1 0.551 0.801 N197LogicTrst115 (data_1_IOBUF)
1599
18 samiam9512
IOBUF:I->IO 5.644 data_1_IOBUF (data<1>)
1600
2 samiam9512
----------------------------------------
1601
20 samiam9512
Total 17.126ns (9.752ns logic, 7.374ns route)
1602
(56.9% logic, 43.1% route)
1603
2 samiam9512
1604
=========================================================================
1605
11 samiam9512
Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selecta/_and0000'
1606
Total number of paths / destination ports: 840 / 8
1607
2 samiam9512
-------------------------------------------------------------------------
1608
20 samiam9512
Offset: 19.715ns (Levels of Logic = 9)
1609
11 samiam9512
Source: select1/selecta/mask_1 (LATCH)
1610
18 samiam9512
Destination: data<7> (PAD)
1611
11 samiam9512
Source Clock: select1/selecta/_and0000 falling
1612
1613
18 samiam9512
Data Path: select1/selecta/mask_1 to data<7>
1614
11 samiam9512
Gate Net
1615
Cell:in->out fanout Delay Delay Logical Name (Net Name)
1616
---------------------------------------- ------------
1617
LDCE:G->Q 7 0.633 1.405 select1/selecta/mask_1 (select1/selecta/mask_1)
1618
20 samiam9512
LUT4:I0->O 1 0.551 0.000 _and0000_inv181 (N17350)
1619
MUXF5:I1->O 1 0.360 1.140 _and0000_inv18_f5 (_and0000_inv_map5561)
1620
LUT4:I0->O 1 0.551 1.140 _and0000_inv108 (_and0000_inv_map5588)
1621
LUT4:I0->O 9 0.551 1.192 _and0000_inv211 (_and0000_inv)
1622
LUT4:I2->O 1 0.551 1.140 N185LogicTrst120 (N185LogicTrst1_map5693)
1623
LUT4:I0->O 1 0.551 0.827 N185LogicTrst142_SW0 (N17018)
1624
LUT4:I3->O 16 0.551 1.576 N185LogicTrst142 (N256)
1625
LUT3:I0->O 1 0.551 0.801 N197LogicTrst115 (data_1_IOBUF)
1626
11 samiam9512
IOBUF:I->IO 5.644 data_1_IOBUF (data<1>)
1627
----------------------------------------
1628
20 samiam9512
Total 19.715ns (10.494ns logic, 9.221ns route)
1629
(53.2% logic, 46.8% route)
1630
11 samiam9512
1631
=========================================================================
1632
18 samiam9512
Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selectd/_and0000'
1633
Total number of paths / destination ports: 624 / 8
1634
11 samiam9512
-------------------------------------------------------------------------
1635
20 samiam9512
Offset: 17.403ns (Levels of Logic = 8)
1636
18 samiam9512
Source: select1/selectd/mask_1 (LATCH)
1637
9 samiam9512
Destination: data<7> (PAD)
1638
18 samiam9512
Source Clock: select1/selectd/_and0000 falling
1639
2 samiam9512
1640
18 samiam9512
Data Path: select1/selectd/mask_1 to data<7>
1641
2 samiam9512
Gate Net
1642
Cell:in->out fanout Delay Delay Logical Name (Net Name)
1643
---------------------------------------- ------------
1644
20 samiam9512
LDCE:G->Q 7 0.633 1.405 select1/selectd/mask_1 (select1/selectd/mask_1)
1645
LUT4:I0->O 1 0.551 0.000 select1/selectd/selectout791 (N17330)
1646
MUXF5:I1->O 1 0.360 1.140 select1/selectd/selectout79_f5 (select1/selectd/selectout_map5389)
1647
LUT4_D:I0->O 8 0.551 1.278 select1/selectd/selectout169 (select1/selectd/selectout_map5416)
1648
LUT4:I1->O 1 0.551 0.827 N187LogicTrst127_SW0_SW0 (N17028)
1649
LUT4:I3->O 1 0.551 1.140 N187LogicTrst127_SW0 (N16922)
1650
LUT4:I0->O 1 0.551 0.869 N187LogicTrst127 (N187LogicTrst_map5838)
1651
LUT3:I2->O 1 0.551 0.801 N187LogicTrst134 (data_6_IOBUF)
1652
IOBUF:I->IO 5.644 data_6_IOBUF (data<6>)
1653
2 samiam9512
----------------------------------------
1654
20 samiam9512
Total 17.403ns (9.943ns logic, 7.460ns route)
1655
(57.1% logic, 42.9% route)
1656
2 samiam9512
1657
=========================================================================
1658
18 samiam9512
Timing constraint: Default OFFSET OUT AFTER for Clock 'reset_n'
1659
Total number of paths / destination ports: 32 / 8
1660
9 samiam9512
-------------------------------------------------------------------------
1661
20 samiam9512
Offset: 15.912ns (Levels of Logic = 7)
1662
18 samiam9512
Source: select1/selectb/datai_3 (LATCH)
1663
Destination: data<3> (PAD)
1664
Source Clock: reset_n falling
1665
9 samiam9512
1666
18 samiam9512
Data Path: select1/selectb/datai_3 to data<3>
1667
9 samiam9512
Gate Net
1668
Cell:in->out fanout Delay Delay Logical Name (Net Name)
1669
---------------------------------------- ------------
1670
18 samiam9512
LDE_1:G->Q 1 0.633 0.869 select1/selectb/datai_3 (select1/selectb/datai_3)
1671
20 samiam9512
LUT4:I2->O 1 0.551 0.996 N193LogicTrst26 (N193LogicTrst_map5708)
1672
LUT4:I1->O 1 0.551 0.827 N193LogicTrst34 (N193LogicTrst_map5710)
1673
LUT4:I3->O 1 0.551 0.827 N193LogicTrst61 (N193LogicTrst_map5716)
1674
LUT4:I3->O 1 0.551 1.140 N193LogicTrst97_SW0 (N16914)
1675
LUT4:I0->O 1 0.551 0.869 N193LogicTrst97 (N193LogicTrst_map5723)
1676
18 samiam9512
LUT3:I2->O 1 0.551 0.801 N193LogicTrst110 (data_3_IOBUF)
1677
IOBUF:I->IO 5.644 data_3_IOBUF (data<3>)
1678
9 samiam9512
----------------------------------------
1679
20 samiam9512
Total 15.912ns (9.583ns logic, 6.329ns route)
1680
(60.2% logic, 39.8% route)
1681
9 samiam9512
1682
=========================================================================
1683
18 samiam9512
Timing constraint: Default path analysis
1684
Total number of paths / destination ports: 2 / 2
1685
11 samiam9512
-------------------------------------------------------------------------
1686
18 samiam9512
Delay: 7.342ns (Levels of Logic = 2)
1687
Source: ps2_data (PAD)
1688
Destination: diag<4> (PAD)
1689
11 samiam9512
1690
18 samiam9512
Data Path: ps2_data to diag<4>
1691
11 samiam9512
Gate Net
1692
Cell:in->out fanout Delay Delay Logical Name (Net Name)
1693
---------------------------------------- ------------
1694
18 samiam9512
IBUF:I->O 2 0.821 0.877 ps2_data_IBUF (ps2_data_IBUF)
1695
OBUF:I->O 5.644 diag_4_OBUF (diag<4>)
1696
11 samiam9512
----------------------------------------
1697
18 samiam9512
Total 7.342ns (6.465ns logic, 0.877ns route)
1698
(88.1% logic, 11.9% route)
1699
11 samiam9512
1700
=========================================================================
1701
20 samiam9512
CPU : 204.47 / 204.97 s | Elapsed : 205.00 / 205.00 s
1702
2 samiam9512
1703
-->
1704
1705
20 samiam9512
Total memory usage is 239120 kilobytes
1706
2 samiam9512
1707
Number of errors : 0 ( 0 filtered)
1708
20 samiam9512
Number of warnings : 162 ( 0 filtered)
1709
Number of infos : 14 ( 0 filtered)
1710
2 samiam9512
