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Release 8.2.02i - xst I.33
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Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
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--> Parameter TMPDIR set to ./xst/projnav.tmp
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CPU : 0.00 / 0.50 s | Elapsed : 0.00 / 0.00 s
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--> Parameter xsthdpdir set to ./xst
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CPU : 0.00 / 0.50 s | Elapsed : 0.00 / 0.00 s
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--> Reading design: testbench.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Compilation
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3) Design Hierarchy Analysis
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4) HDL Analysis
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5) HDL Synthesis
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5.1) HDL Synthesis Report
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6) Advanced HDL Synthesis
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6.1) Advanced HDL Synthesis Report
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7) Low Level Synthesis
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8) Partition Report
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9) Final Report
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9.1) Device utilization summary
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9.2) TIMING REPORT
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "testbench.prj"
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "testbench"
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Output Format : NGC
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Target Device : xc3s1000-4-ft256
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---- Source Options
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Top Module Name : testbench
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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FSM Style : lut
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RAM Extraction : Yes
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RAM Style : Auto
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ROM Extraction : Yes
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Mux Style : Auto
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Decoder Extraction : YES
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Priority Encoder Extraction : YES
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Shift Register Extraction : YES
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Logical Shifter Extraction : YES
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XOR Collapsing : YES
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ROM Style : Auto
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Mux Extraction : YES
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Resource Sharing : YES
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Multiplier Style : auto
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Automatic Register Balancing : No
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---- Target Options
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Add IO Buffers : YES
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Global Maximum Fanout : 500
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Add Generic Clock Buffer(BUFG) : 8
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Register Duplication : YES
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Slice Packing : YES
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Pack IO Registers into IOBs : auto
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 1
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Keep Hierarchy : NO
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RTL Output : Yes
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Global Optimization : AllClockNets
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Write Timing Constraints : NO
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : maintain
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Slice Utilization Ratio : 100
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Slice Utilization Ratio Delta : 5
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---- Other Options
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lso : testbench.lso
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Read Cores : YES
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cross_clock_analysis : NO
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verilog2001 : YES
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safe_implementation : No
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Optimize Instantiated Primitives : NO
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use_clock_enable : Yes
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use_sync_set : Yes
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use_sync_reset : Yes
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=========================================================================
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling vhdl file "C:/Xilinx/ISEexamples/cpu8080/common.vhd" in Library work.
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Architecture common of Entity common is up to date.
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Compiling vhdl file "C:/Xilinx/ISEexamples/cpu8080/ps2_kbd.vhd" in Library work.
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Architecture arch of Entity ps2_kbd is up to date.
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Compiling vhdl file "C:/Xilinx/ISEexamples/cpu8080/vga.vhd" in Library work.
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Architecture vga_arch of Entity vga is up to date.
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Architecture sync_arch of Entity sync is up to date.
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Compiling verilog file "vgachr.v" in library work
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Module compiled
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Module compiled
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Module compiled
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Module compiled
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Compiling verilog file "cpu8080.v" in library work
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Module compiled
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Module compiled
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Compiling verilog file "testbench.v" in library work
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Module compiled
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Module compiled
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Module compiled
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Module compiled
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Module compiled
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Compiling verilog include file "test.rom"
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Module compiled
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Module compiled
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No errors in compilation
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Analysis of file <"testbench.prj"> succeeded.
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=========================================================================
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* Design Hierarchy Analysis *
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=========================================================================
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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134
Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for entity in library (architecture ) with generics.
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FREQ = 50000
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for entity in library (architecture ) with generics.
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CLK_DIV = 2
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FIT_TO_SCREEN = true
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FREQ = 50000
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LINES_PER_FRAME = 480
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NUM_RGB_BITS = 3
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PIXEL_WIDTH = 1
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PIXELS_PER_LINE = 640
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for entity in library (architecture ) with generics.
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FREQ = 25000
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PERIOD = 32
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START = 26
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VISIBLE = 640
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WIDTH = 4
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Analyzing hierarchy for entity in library (architecture ) with generics.
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FREQ = 31
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PERIOD = 16784
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START = 15700
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VISIBLE = 480
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WIDTH = 64
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Building hierarchy successfully finished.
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=========================================================================
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* HDL Analysis *
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=========================================================================
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Analyzing top module .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing generic Entity in library (Architecture ).
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PIXEL_WIDTH = 1
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PIXELS_PER_LINE = 640
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CLK_DIV = 2
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FIT_TO_SCREEN = true
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FREQ = 50000
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LINES_PER_FRAME = 480
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NUM_RGB_BITS = 3
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Entity analyzed. Unit generated.
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Analyzing generic Entity in library (Architecture ).
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FREQ = 25000
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VISIBLE = 640
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WIDTH = 4
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PERIOD = 32
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START = 26
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Entity analyzed. Unit generated.
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Analyzing generic Entity in library (Architecture ).
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FREQ = 31
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PERIOD = 16784
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START = 15700
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VISIBLE = 480
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WIDTH = 64
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Entity analyzed. Unit generated.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing generic Entity in library (Architecture ).
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FREQ = 50000
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Entity analyzed. Unit generated.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Performing bidirectional port resolution...
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Synthesizing Unit .
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Related source file is "testbench.v".
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Found 2048x8-bit ROM for signal .
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Found 8-bit tristate buffer for signal .
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Summary:
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inferred 1 ROM(s).
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inferred 8 Tristate(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "testbench.v".
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Found 1024x8-bit single-port block RAM for signal .
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-----------------------------------------------------------------------
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| ram_style | Auto | |
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-----------------------------------------------------------------------
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| Port A |
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| aspect ratio | 1024-word x 8-bit | |
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| mode | read-first | |
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| clkA | connected to signal | fall |
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| enA | connected to signal | high |
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| weA | connected to signal | high |
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| addrA | connected to signal | |
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| diA | connected to signal | |
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| doA | connected to signal | |
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-----------------------------------------------------------------------
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Found 8-bit tristate buffer for signal .
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Summary:
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inferred 1 RAM(s).
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inferred 8 Tristate(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "testbench.v".
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Found finite state machine for signal .
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-----------------------------------------------------------------------
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| States | 3 |
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| Transitions | 3 |
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| Inputs | 0 |
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| Outputs | 4 |
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| Clock | clock (falling_edge) |
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| Clock enable | $not0004 (positive) |
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| Reset | reset (positive) |
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| Reset type | synchronous |
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| Reset State | 0000 |
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| Encoding | automatic |
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| Implementation | LUT |
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-----------------------------------------------------------------------
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Found 8-bit tristate buffer for signal .
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Found 1-bit 4-to-1 multiplexer for signal <$mux0000>.
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Found 1-bit 4-to-1 multiplexer for signal <$mux0001>.
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Found 1-bit 4-to-1 multiplexer for signal <$mux0002>.
316
Found 1-bit 4-to-1 multiplexer for signal <$mux0003>.
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Found 1-bit 4-to-1 multiplexer for signal <$mux0004>.
318
Found 1-bit 4-to-1 multiplexer for signal <$mux0005>.
319
Found 1-bit 4-to-1 multiplexer for signal <$mux0006>.
320
Found 1-bit 4-to-1 multiplexer for signal <$mux0007>.
321
Found 8-bit register for signal .
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Found 8-bit register for signal .
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Found 8-bit register for signal .
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Found 8-bit register for signal .
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Found 8-bit register for signal .
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Found 8-bit register for signal .
327
Summary:
328
inferred 1 Finite State Machine(s).
329
inferred 48 D-type flip-flop(s).
330
inferred 8 Multiplexer(s).
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inferred 8 Tristate(s).
332
Unit synthesized.
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Synthesizing Unit .
336
Related source file is "testbench.v".
337
WARNING:Xst:647 - Input > is never used.
338
WARNING:Xst:647 - Input > is never used.
339
WARNING:Xst:737 - Found 6-bit latch for signal .
340
WARNING:Xst:737 - Found 8-bit latch for signal .
341
WARNING:Xst:737 - Found 8-bit latch for signal .
342
Found 8-bit tristate buffer for signal .
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Found 6-bit comparator equal for signal <$cmp_eq0000> created at line 291.
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Summary:
345
inferred 1 Comparator(s).
346
inferred 8 Tristate(s).
347
Unit synthesized.
348
349
350
Synthesizing Unit .
351
Related source file is "cpu8080.v".
352
WARNING:Xst:646 - Signal is assigned but never used.
353
Found 1-bit 8-to-1 multiplexer for signal .
354
Found 1-bit 8-to-1 multiplexer for signal .
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Found 5-bit adder for signal <$add0001> created at line 1578.
356
Found 8-bit adder carry out for signal <$addsub0000> created at line 1571.
357
Found 4-bit adder carry out for signal <$addsub0001> created at line 1572.
358
Found 6-bit subtractor for signal <$sub0000> created at line 1584.
359
Found 6-bit subtractor for signal <$sub0001> created at line 1590.
360
Found 9-bit subtractor for signal <$sub0002> created at line 1583.
361
Found 8-bit xor2 for signal <$xor0000> created at line 1601.
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Found 1-bit xor8 for signal <$xor0002>.
363
Summary:
364
inferred 8 Adder/Subtractor(s).
365
inferred 10 Multiplexer(s).
366
inferred 1 Xor(s).
367
Unit synthesized.
368
369
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Synthesizing Unit .
371
Related source file is "C:/Xilinx/ISEexamples/cpu8080/ps2_kbd.vhd".
372
WARNING:Xst:646 - Signal is assigned but never used.
373
Found 13-bit adder for signal <$addsub0000> created at line 112.
374
Found 4-bit up counter for signal .
375
Found 1-bit register for signal .
376
Found 5-bit register for signal .
377
Found 1-bit register for signal .
378
Found 10-bit register for signal .
379
Found 13-bit register for signal .
380
Summary:
381
inferred 1 Counter(s).
382
inferred 30 D-type flip-flop(s).
383
inferred 1 Adder/Subtractor(s).
384
Unit synthesized.
385
386
387
Synthesizing Unit .
388
Related source file is "vgachr.v".
389
Unit synthesized.
390
391
392
Synthesizing Unit .
393
Related source file is "vgachr.v".
394
Unit synthesized.
395
396
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Synthesizing Unit .
398
Related source file is "vgachr.v".
399
Found 2048x8-bit ROM for signal .
400
Summary:
401
inferred 1 ROM(s).
402
Unit synthesized.
403
404
405
Synthesizing Unit .
406
Related source file is "C:/Xilinx/ISEexamples/cpu8080/vga.vhd".
407
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Found 16-bit adder for signal <$addsub0000> created at line 398.
408
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Found 1-bit register for signal .
409
Found 16-bit register for signal .
410
Found 1-bit register for signal .
411
Found 1-bit register for signal .
412
Summary:
413
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inferred 3 D-type flip-flop(s).
414
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inferred 1 Adder/Subtractor(s).
415
Unit synthesized.
416
417
418
Synthesizing Unit .
419
Related source file is "C:/Xilinx/ISEexamples/cpu8080/vga.vhd".
420
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Found 16-bit adder for signal <$addsub0000> created at line 398.
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Found 1-bit register for signal .
422
Found 16-bit register for signal .
423
Found 1-bit register for signal .
424
Found 1-bit register for signal .
425
Summary:
426
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inferred 3 D-type flip-flop(s).
427
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inferred 1 Adder/Subtractor(s).
428
Unit synthesized.
429
430
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Synthesizing Unit .
432
Related source file is "testbench.v".
433
Found 1-bit register for signal .
434
Found 8-bit tristate buffer for signal .
435
Found 8-bit register for signal .
436
Found 4-bit comparator equal for signal .
437
Found 4-bit register for signal .
438
Summary:
439
inferred 13 D-type flip-flop(s).
440
inferred 1 Comparator(s).
441
inferred 8 Tristate(s).
442
Unit synthesized.
443
444
445
Synthesizing Unit .
446
Related source file is "cpu8080.v".
447
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INFO:Xst:1799 - State 0XXXXX is never reached in FSM .
448
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Found finite state machine for signal .
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-----------------------------------------------------------------------
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| States | 39 |
451
| Transitions | 1171 |
452
| Inputs | 148 |
453
| Outputs | 38 |
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| Clock | clock (rising_edge) |
455
| Reset | reset (positive) |
456
| Reset type | synchronous |
457
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| Reset State | 000001 |
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| Encoding | automatic |
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| Implementation | LUT |
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-----------------------------------------------------------------------
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Found 4x16-bit ROM for signal <$mux0041> created at line 268.
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Found 16-bit register for signal .
463
Found 1-bit register for signal .
464
Found 1-bit register for signal .
465
Found 1-bit register for signal .
466
Found 1-bit register for signal .
467
Found 1-bit register for signal .
468
Found 8-bit tristate buffer for signal .
469
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Found 32-bit adder for signal <$add0000> created at line 501.
470
Found 32-bit adder for signal <$add0001> created at line 513.
471
Found 32-bit adder for signal <$add0002> created at line 525.
472
Found 16-bit adder for signal <$add0003> created at line 980.
473
Found 16-bit adder for signal <$add0004> created at line 895.
474
Found 32-bit adder for signal <$add0005> created at line 570.
475
Found 32-bit adder for signal <$add0006> created at line 558.
476
Found 32-bit adder for signal <$add0007> created at line 546.
477
Found 17-bit adder for signal <$add0008> created at line 491.
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Found 17-bit adder for signal <$addsub0000>.
479
Found 17-bit adder for signal <$addsub0001>.
480
Found 17-bit adder for signal <$addsub0002>.
481
Found 8-bit adder for signal <$addsub0003>.
482
Found 8-bit addsub for signal <$addsub0004>.
483
Found 8-bit addsub for signal <$addsub0005>.
484
Found 8-bit addsub for signal <$addsub0006>.
485
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Found 16-bit adder for signal <$addsub0007> created at line 1092.
486
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Found 6-bit adder for signal <$addsub0008>.
487
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Found 16-bit adder for signal <$addsub0009> created at line 1051.
488
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Found 8-bit adder carry out for signal <$addsub0010>.
489
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Found 8-bit adder carry out for signal <$addsub0011>.
490
Found 4-bit comparator greater for signal <$cmp_gt0000> created at line 1373.
491
Found 4-bit comparator greater for signal <$cmp_gt0001> created at line 361.
492
Found 3-bit 4-to-1 multiplexer for signal <$mux0025> created at line 317.
493
Found 8-bit 4-to-1 multiplexer for signal <$mux0031> created at line 317.
494
Found 3-bit 4-to-1 multiplexer for signal <$mux0044> created at line 321.
495
Found 8-bit 4-to-1 multiplexer for signal <$mux0045>.
496
Found 16-bit adder for signal <$share0000> created at line 317.
497
Found 16-bit addsub for signal <$share0006> created at line 268.
498
Found 32-bit subtractor for signal <$sub0000> created at line 546.
499
Found 32-bit subtractor for signal <$sub0001> created at line 558.
500
Found 32-bit subtractor for signal <$sub0002> created at line 570.
501
Found 16-bit subtractor for signal <$sub0003> created at line 766.
502
2 samiam9512
Found 1-bit register for signal .
503
Found 8-bit register for signal .
504
Found 8-bit register for signal .
505
Found 3-bit register for signal .
506
Found 1-bit register for signal .
507
Found 1-bit register for signal .
508
Found 1-bit register for signal .
509
Found 8-bit register for signal .
510
Found 1-bit register for signal .
511
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Found 1-bit register for signal .
512
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Found 1-bit register for signal .
513
11 samiam9512
Found 8-bit register for signal .
514
2 samiam9512
Found 1-bit register for signal .
515
Found 16-bit register for signal .
516
Found 2-bit register for signal .
517
Found 16-bit register for signal .
518
Found 8-bit register for signal .
519
Found 8-bit register for signal .
520
Found 3-bit register for signal .
521
Found 64-bit register for signal .
522
Found 1-bit register for signal .
523
Found 16-bit register for signal .
524
Found 6-bit register for signal .
525
Found 16-bit register for signal .
526
Found 8-bit register for signal .
527
Found 8-bit register for signal .
528
Found 1-bit register for signal .
529
Summary:
530
inferred 1 Finite State Machine(s).
531
inferred 1 ROM(s).
532
11 samiam9512
inferred 237 D-type flip-flop(s).
533
28 samiam9512
inferred 33 Adder/Subtractor(s).
534
2 samiam9512
inferred 2 Comparator(s).
535
28 samiam9512
inferred 38 Multiplexer(s).
536
2 samiam9512
inferred 8 Tristate(s).
537
Unit synthesized.
538
539
540
11 samiam9512
Synthesizing Unit .
541
Related source file is "C:/Xilinx/ISEexamples/cpu8080/vga.vhd".
542
WARNING:Xst:646 - Signal is assigned but never used.
543
WARNING:Xst:646 - Signal > is assigned but never used.
544
Found 3-bit register for signal .
545
Found 1-bit register for signal .
546
Found 8-bit up counter for signal .
547
Found 1-bit register for signal .
548
Found 3-bit register for signal .
549
Found 16-bit register for signal .
550
Found 1-bit register for signal .
551
Found 9-bit register for signal .
552
Summary:
553
inferred 1 Counter(s).
554
inferred 34 D-type flip-flop(s).
555
Unit synthesized.
556
557
558
Synthesizing Unit .
559
Related source file is "vgachr.v".
560
20 samiam9512
WARNING:Xst:646 - Signal > is assigned but never used.
561
11 samiam9512
WARNING:Xst:646 - Signal is assigned but never used.
562
Found 1920x8-bit single-port block RAM for signal .
563
-----------------------------------------------------------------------
564
| ram_style | Auto | |
565
-----------------------------------------------------------------------
566
| Port A |
567
| aspect ratio | 1920-word x 8-bit | |
568
| mode | read-first | |
569
| clkA | connected to signal | rise |
570
| weA | connected to signal | high |
571
| addrA | connected to signal | |
572
| diA | connected to signal | |
573
| doA | connected to signal | |
574
-----------------------------------------------------------------------
575
Found 1920x8-bit dual-port distributed RAM for signal .
576
-----------------------------------------------------------------------
577
| ram_style | Auto | |
578
-----------------------------------------------------------------------
579
| Port A |
580
| aspect ratio | 1920-word x 8-bit | |
581
| clkA | connected to signal | rise |
582
| weA | connected to signal | high |
583
| addrA | connected to signal | |
584
| diA | connected to signal | |
585
-----------------------------------------------------------------------
586
| Port B |
587
| aspect ratio | 1920-word x 8-bit | |
588
| addrB | connected to internal node | |
589
| doB | connected to internal node | |
590
-----------------------------------------------------------------------
591
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronously. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
592
20 samiam9512
Found 1920x5-bit dual-port block RAM for signal .
593
-----------------------------------------------------------------------
594
| ram_style | Auto | |
595
-----------------------------------------------------------------------
596
| Port A |
597
| aspect ratio | 1920-word x 5-bit | |
598
| mode | read-first | |
599
| clkA | connected to signal | rise |
600
| weA | connected to signal | high |
601
| addrA | connected to signal | |
602
| diA | connected to signal | |
603
| doA | connected to signal | |
604
-----------------------------------------------------------------------
605
| Port B |
606
| aspect ratio | 1920-word x 5-bit | |
607
| mode | read-first | |
608
| clkB | connected to signal | rise |
609
| addrB | connected to internal node | |
610
| doB | connected to signal | |
611
-----------------------------------------------------------------------
612
24 samiam9512
INFO:Xst:2117 - HDL ADVISOR - Mux Selector of Case statement line 873 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
613
11 samiam9512
- add an 'INIT' attribute on signal (optimization is then done without any risk)
614
- use the attribute 'signal_encoding user' to avoid onehot optimization
615
- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
616
Found finite state machine for signal .
617
-----------------------------------------------------------------------
618
| States | 4 |
619
18 samiam9512
| Transitions | 7 |
620
| Inputs | 1 |
621
11 samiam9512
| Outputs | 6 |
622
| Clock | clk (rising_edge) |
623
18 samiam9512
| Clock enable | $not0008 (positive) |
624
| Reset | rst (positive) |
625
11 samiam9512
| Reset type | synchronous |
626
| Reset State | 00 |
627
| Encoding | automatic |
628
| Implementation | LUT |
629
-----------------------------------------------------------------------
630
24 samiam9512
WARNING:Xst:643 - "vgachr.v" line 945: The result of a 9x6-bit multiplication is partially used. Only the 11 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
631
20 samiam9512
Found 5-bit tristate buffer for signal .
632
11 samiam9512
Found 8-bit tristate buffer for signal .
633
24 samiam9512
Found 11-bit adder for signal <$add0000> created at line 928.
634
Found 9-bit subtractor for signal <$addsub0000> created at line 945.
635
Found 11-bit adder for signal <$addsub0001> created at line 945.
636
Found 11-bit comparator equal for signal <$cmp_eq0003> created at line 882.
637
Found 32-bit comparator greatequal for signal <$cmp_ge0000> created at line 814.
638
Found 7-bit comparator greatequal for signal <$cmp_ge0001> created at line 854.
639
Found 5-bit comparator greatequal for signal <$cmp_ge0002> created at line 858.
640
Found 7-bit comparator less for signal <$cmp_lt0000> created at line 854.
641
Found 5-bit comparator less for signal <$cmp_lt0001> created at line 858.
642
Found 8-bit comparator less for signal <$cmp_lt0002> created at line 945.
643
Found 9x6-bit multiplier for signal <$mult0002> created at line 945.
644
Found 16-bit 4-to-1 multiplexer for signal <$mux0000> created at line 911.
645
Found 1-bit 4-to-1 multiplexer for signal <$mux0001> created at line 904.
646
Found 1-bit 4-to-1 multiplexer for signal <$mux0002> created at line 904.
647
Found 1-bit 4-to-1 multiplexer for signal <$mux0003> created at line 904.
648
Found 1-bit 4-to-1 multiplexer for signal <$mux0004> created at line 904.
649
Found 1-bit 4-to-1 multiplexer for signal <$mux0005> created at line 904.
650
Found 1-bit 4-to-1 multiplexer for signal <$mux0006> created at line 904.
651
Found 1-bit 4-to-1 multiplexer for signal <$mux0007> created at line 904.
652
Found 1-bit 4-to-1 multiplexer for signal <$mux0008> created at line 904.
653
Found 8-bit 4-to-1 multiplexer for signal <$mux0009> created at line 883.
654
Found 1-bit xor2 for signal <$xor0000> created at line 903.
655
20 samiam9512
Found 32-bit up counter for signal .
656
Found 1-bit register for signal .
657
11 samiam9512
Found 7-bit up counter for signal .
658
18 samiam9512
Found 8-bit register for signal .
659
11 samiam9512
Found 5-bit up counter for signal .
660
18 samiam9512
Found 8-bit register for signal .
661
11 samiam9512
Found 16-bit register for signal .
662
Found 5-bit up counter for signal .
663
Found 11-bit up accumulator for signal .
664
Summary:
665
inferred 1 Finite State Machine(s).
666
20 samiam9512
inferred 3 RAM(s).
667
inferred 4 Counter(s).
668
11 samiam9512
inferred 1 Accumulator(s).
669
20 samiam9512
inferred 33 D-type flip-flop(s).
670
11 samiam9512
inferred 3 Adder/Subtractor(s).
671
inferred 1 Multiplier(s).
672
20 samiam9512
inferred 7 Comparator(s).
673
inferred 32 Multiplexer(s).
674
inferred 13 Tristate(s).
675
11 samiam9512
Unit synthesized.
676
677
678
Synthesizing Unit .
679
Related source file is "vgachr.v".
680
18 samiam9512
WARNING:Xst:646 - Signal is assigned but never used.
681
20 samiam9512
WARNING:Xst:646 - Signal > is assigned but never used.
682
18 samiam9512
WARNING:Xst:646 - Signal is assigned but never used.
683
20 samiam9512
Register equivalent to has been removed
684
11 samiam9512
Found finite state machine for signal .
685
-----------------------------------------------------------------------
686
20 samiam9512
| States | 20 |
687
| Transitions | 88 |
688
| Inputs | 21 |
689
| Outputs | 21 |
690
18 samiam9512
| Clock | clock (rising_edge) |
691
11 samiam9512
| Reset | reset (positive) |
692
| Reset type | synchronous |
693
20 samiam9512
| Reset State | 00100 |
694
11 samiam9512
| Encoding | automatic |
695
| Implementation | LUT |
696
-----------------------------------------------------------------------
697
24 samiam9512
WARNING:Xst:643 - "vgachr.v" line 688: The result of a 9x8-bit multiplication is partially used. Only the 11 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
698
Found 4x1-bit ROM for signal <$mux0023> created at line 372.
699
11 samiam9512
Found 8-bit tristate buffer for signal .
700
24 samiam9512
Found 11-bit adder for signal <$add0002> created at line 558.
701
Found 9-bit subtractor for signal <$addsub0000> created at line 688.
702
Found 11-bit adder for signal <$addsub0001> created at line 521.
703
20 samiam9512
Found 11-bit adder for signal <$addsub0002>.
704
24 samiam9512
Found 11-bit adder carry out for signal <$addsub0003> created at line 541.
705
Found 8-bit comparator greatequal for signal <$cmp_ge0000> created at line 384.
706
Found 11-bit comparator greatequal for signal <$cmp_ge0001> created at line 413.
707
Found 8-bit comparator greatequal for signal <$cmp_ge0002> created at line 685.
708
Found 8-bit comparator greatequal for signal <$cmp_ge0003> created at line 358.
709
Found 8-bit comparator greatequal for signal <$cmp_ge0004> created at line 361.
710
Found 12-bit comparator greater for signal <$cmp_gt0000> created at line 541.
711
Found 8-bit comparator greater for signal <$cmp_gt0001> created at line 707.
712
Found 11-bit comparator greater for signal <$cmp_gt0002> created at line 425.
713
Found 12-bit comparator greater for signal <$cmp_gt0003> created at line 541.
714
Found 8-bit comparator lessequal for signal <$cmp_le0000> created at line 685.
715
Found 8-bit comparator lessequal for signal <$cmp_le0001> created at line 685.
716
Found 8-bit comparator lessequal for signal <$cmp_le0002> created at line 358.
717
Found 8-bit comparator lessequal for signal <$cmp_le0003> created at line 361.
718
Found 11-bit comparator less for signal <$cmp_lt0000> created at line 398.
719
Found 11-bit comparator less for signal <$cmp_lt0001> created at line 519.
720
Found 11-bit comparator less for signal <$cmp_lt0002> created at line 555.
721
Found 11-bit comparator less for signal <$cmp_lt0003> created at line 603.
722
Found 8-bit comparator less for signal <$cmp_lt0004> created at line 707.
723
Found 11-bit comparator less for signal <$cmp_lt0005> created at line 432.
724
Found 9x8-bit multiplier for signal <$mult0002> created at line 688.
725
20 samiam9512
Found 1-bit 4-to-1 multiplexer for signal <$mux0005>.
726
Found 1-bit 8-to-1 multiplexer for signal <$mux0007>.
727
24 samiam9512
Found 11-bit addsub for signal <$share0000> created at line 372.
728
Found 10-bit subtractor for signal <$sub0000> created at line 688.
729
Found 5-bit subtractor for signal <$sub0001> created at line 708.
730
18 samiam9512
Found 1-bit register for signal .
731
11 samiam9512
Found 8-bit register for signal .
732
18 samiam9512
Found 1-bit register for signal .
733
11 samiam9512
Found 11-bit register for signal .
734
20 samiam9512
Found 5-bit tristate buffer for signal .
735
Found 8-bit register for signal .
736
11 samiam9512
Found 8-bit tristate buffer for signal .
737
Found 1-bit register for signal .
738
Found 8-bit register for signal .
739
18 samiam9512
Found 1-bit register for signal .
740
11 samiam9512
Found 1-bit register for signal .
741
20 samiam9512
Found 5-bit register for signal .
742
11 samiam9512
Found 11-bit register for signal .
743
Found 8-bit register for signal .
744
18 samiam9512
Found 1-bit register for signal .
745
20 samiam9512
Found 1-bit register for signal .
746
18 samiam9512
Found 1-bit register for signal .
747
Found 1-bit register for signal .
748
11 samiam9512
Found 1-bit register for signal .
749
18 samiam9512
Found 1-bit register for signal .
750
Found 1-bit register for signal .
751
Found 1-bit register for signal .
752
20 samiam9512
Found 8-bit register for signal .
753
18 samiam9512
Found 1-bit register for signal .
754
Found 11-bit register for signal .
755
11 samiam9512
Found 1-bit register for signal .
756
Summary:
757
inferred 1 Finite State Machine(s).
758
20 samiam9512
inferred 1 ROM(s).
759
inferred 93 D-type flip-flop(s).
760
inferred 8 Adder/Subtractor(s).
761
inferred 1 Multiplier(s).
762
inferred 19 Comparator(s).
763
inferred 2 Multiplexer(s).
764
inferred 21 Tristate(s).
765
11 samiam9512
Unit synthesized.
766
767
768
2 samiam9512
Synthesizing Unit .
769
Related source file is "testbench.v".
770
Unit synthesized.
771
772
INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
773
774
=========================================================================
775
HDL Synthesis Report
776
777
Macro Statistics
778
20 samiam9512
# RAMs : 4
779
2 samiam9512
1024x8-bit single-port block RAM : 1
780
20 samiam9512
1920x5-bit dual-port block RAM : 1
781
11 samiam9512
1920x8-bit dual-port distributed RAM : 1
782
18 samiam9512
1920x8-bit single-port block RAM : 1
783
20 samiam9512
# ROMs : 4
784
24 samiam9512
2048x8-bit ROM : 2
785
4x1-bit ROM : 1
786
4x16-bit ROM : 1
787
20 samiam9512
# Multipliers : 2
788
11 samiam9512
9x6-bit multiplier : 1
789
20 samiam9512
9x8-bit multiplier : 1
790
28 samiam9512
# Adders/Subtractors : 55
791
20 samiam9512
10-bit subtractor : 1
792
18 samiam9512
11-bit adder : 5
793
11-bit adder carry out : 1
794
11-bit addsub : 1
795
13-bit adder : 1
796
11 samiam9512
16-bit adder : 7
797
2 samiam9512
16-bit addsub : 1
798
16-bit subtractor : 1
799
17-bit adder : 8
800
32-bit adder : 6
801
32-bit subtractor : 3
802
28 samiam9512
4-bit adder carry out : 1
803
2 samiam9512
5-bit adder : 1
804
20 samiam9512
5-bit subtractor : 1
805
2 samiam9512
6-bit adder : 1
806
6-bit subtractor : 2
807
8-bit adder : 1
808
8-bit adder carry out : 3
809
8-bit addsub : 3
810
9-bit adder : 3
811
20 samiam9512
9-bit subtractor : 4
812
# Counters : 6
813
32-bit up counter : 1
814
18 samiam9512
4-bit up counter : 1
815
11 samiam9512
5-bit up counter : 2
816
7-bit up counter : 1
817
18 samiam9512
8-bit up counter : 1
818
11 samiam9512
# Accumulators : 1
819
11-bit up accumulator : 1
820
20 samiam9512
# Registers : 104
821
1-bit register : 51
822
18 samiam9512
10-bit register : 1
823
11-bit register : 3
824
13-bit register : 1
825
11 samiam9512
16-bit register : 9
826
2 samiam9512
2-bit register : 1
827
11 samiam9512
3-bit register : 4
828
2 samiam9512
4-bit register : 1
829
20 samiam9512
5-bit register : 2
830
2 samiam9512
6-bit register : 1
831
20 samiam9512
8-bit register : 29
832
11 samiam9512
9-bit register : 1
833
2 samiam9512
# Latches : 12
834
6-bit latch : 4
835
8-bit latch : 8
836
20 samiam9512
# Comparators : 33
837
18 samiam9512
11-bit comparator equal : 1
838
11-bit comparator greatequal : 1
839
11-bit comparator greater : 1
840
11-bit comparator less : 5
841
12-bit comparator greater : 2
842
20 samiam9512
32-bit comparator greatequal : 1
843
2 samiam9512
4-bit comparator equal : 1
844
4-bit comparator greater : 2
845
11 samiam9512
5-bit comparator greatequal : 1
846
5-bit comparator less : 1
847
2 samiam9512
6-bit comparator equal : 4
848
11 samiam9512
7-bit comparator greatequal : 1
849
7-bit comparator less : 1
850
20 samiam9512
8-bit comparator greatequal : 4
851
8-bit comparator greater : 1
852
8-bit comparator less : 2
853
8-bit comparator lessequal : 4
854
28 samiam9512
# Multiplexers : 29
855
20 samiam9512
1-bit 4-to-1 multiplexer : 17
856
1-bit 8-to-1 multiplexer : 3
857
16-bit 4-to-1 multiplexer : 1
858
28 samiam9512
3-bit 4-to-1 multiplexer : 2
859
8-bit 4-to-1 multiplexer : 3
860
2 samiam9512
8-bit 8-to-1 multiplexer : 3
861
20 samiam9512
# Tristates : 14
862
5-bit tristate buffer : 2
863
18 samiam9512
8-bit tristate buffer : 12
864
20 samiam9512
# Xors : 3
865
1-bit xor2 : 1
866
2 samiam9512
1-bit xor8 : 1
867
8-bit xor2 : 1
868
869
=========================================================================
870
871
=========================================================================
872
* Advanced HDL Synthesis *
873
=========================================================================
874
875
11 samiam9512
Analyzing FSM for best encoding.
876
20 samiam9512
Optimizing FSM on signal with one-hot encoding.
877
-------------------------------
878
18 samiam9512
State | Encoding
879
20 samiam9512
-------------------------------
880
00000 | 00000000000000100000
881
00001 | 00000000000000000010
882
00010 | 00000000000001000000
883
00011 | 00000000000010000000
884
00100 | 00000000000000000001
885
00101 | 00000000000100000000
886
00110 | 00000000001000000000
887
00111 | 00000000010000000000
888
01000 | 00000000000000001000
889
01001 | 00000000000000000100
890
01010 | 00000000100000000000
891
01011 | 00000010000000000000
892
01100 | 00000100000000000000
893
01101 | 00001000000000000000
894
01110 | 00000001000000000000
895
01111 | 00010000000000000000
896
10000 | 00000000000000010000
897
10001 | 00100000000000000000
898
10010 | 10000000000000000000
899
10011 | 01000000000000000000
900
-------------------------------
901
11 samiam9512
Analyzing FSM for best encoding.
902
Optimizing FSM on signal with gray encoding.
903
-------------------
904
State | Encoding
905
-------------------
906
00 | 00
907
01 | 01
908
10 | 11
909
11 | 10
910
-------------------
911
9 samiam9512
Analyzing FSM for best encoding.
912
28 samiam9512
Optimizing FSM on signal with speed1 encoding.
913
-----------------------------------------------------
914
18 samiam9512
State | Encoding
915
28 samiam9512
-----------------------------------------------------
916
000001 | 10000000000000000000000000000000000000000
917
000010 | 01000000000000000000000000000000000000000
918
000011 | 00100000000000000000000000000000000000000
919
000100 | 00010000000000000000000000000000000000000
920
000101 | 00000000100000000000000000000000000000000
921
000110 | 00000000010000000000000000000000000000001
922
000111 | 00000010000000000000000000000000000000001
923
001000 | 00000000000000001000000000000000000000001
924
001001 | 00000000000000000010000000000000000000001
925
001010 | 00000000000000000000100000000000000000001
926
001011 | 00000000000000000000010000000000000000001
927
001100 | 00000000001000000001000000000000000000000
928
001101 | 00000000000000000000000000100000000000001
929
001110 | 00000001000000000000000000000000000000000
930
001111 | 00000000000010000000000000000000000000000
931
010000 | 00000000000001000000000000000000000000000
932
010001 | 00000000001000100000000000000000000000000
933
010010 | 00000100000000000000000000000000000000000
934
010011 | 00000000000000000000000000000000100000000
935
010100 | 00000000001100000000000000000000000000000
936
010101 | 00000000000000000000001000000000000000001
937
010110 | 00000000000000000000000000000010000000000
938
010111 | 00000000000000000000000000000000000100000
939
011000 | 00000000000000000000000000000000000010001
940
011001 | 00000000000000000000000000000001000000000
941
011010 | 00000000000000000000000000000000000001000
942
011011 | 00000000000000000000000000000000000000100
943
011100 | 00000000000000000000000000000000000000011
944
011101 | 00000000001000010000000000000000000000000
945
011110 | 00000000001000000000000100000000000000000
946
011111 | 00000000001000000000000001000000000000000
947
18 samiam9512
0XXXXX | unreached
948
28 samiam9512
100000 | 00000000001000000100000000000000000000000
949
100001 | 00000000000000000000000010000000000000000
950
100010 | 00001000000000000000000000000000000000001
951
100011 | 00000000000000000000000000001000000000001
952
100100 | 00000000000000000000000000000000010000001
953
100101 | 00000000001000000000000000010000000000000
954
100110 | 00000000001000000000000000000000001000000
955
100111 | 00000000001000000000000000000100000000000
956
-----------------------------------------------------
957
9 samiam9512
Analyzing FSM for best encoding.
958
Optimizing FSM on signal with gray encoding.
959
-------------------
960
State | Encoding
961
-------------------
962
0000 | 00
963
0001 | 01
964
0010 | 11
965
-------------------
966
11 samiam9512
Loading device for application Rf_Device from file '3s1000.nph' in environment C:\Xilinx.
967
18 samiam9512
WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block .
968
11 samiam9512
WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block .
969
20 samiam9512
WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block .
970
24 samiam9512
INFO:Xst:1651 - Address input of ROM is tied to register .
971
9 samiam9512
INFO:Xst:1650 - The register is removed and the ROM is implemented as read-only block RAM.
972
2 samiam9512
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block .
973
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .
974
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .
975
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .
976
18 samiam9512
INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 8 FFs/Latches, which will be removed :
977
20 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
978
WARNING:Xst:1291 - FF/Latch is unconnected in block .
979
WARNING:Xst:1291 - FF/Latch is unconnected in block .
980
11 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
981
2 samiam9512
982
=========================================================================
983
Advanced HDL Synthesis Report
984
985
Macro Statistics
986
11 samiam9512
# FSMs : 4
987
20 samiam9512
# RAMs : 5
988
2 samiam9512
1024x8-bit single-port block RAM : 1
989
20 samiam9512
1920x5-bit dual-port block RAM : 1
990
11 samiam9512
1920x8-bit dual-port distributed RAM : 1
991
18 samiam9512
1920x8-bit single-port block RAM : 1
992
24 samiam9512
2048x8-bit single-port block RAM : 1
993
20 samiam9512
# ROMs : 3
994
11 samiam9512
2048x8-bit ROM : 1
995
24 samiam9512
4x1-bit ROM : 1
996
4x16-bit ROM : 1
997
20 samiam9512
# Multipliers : 2
998
11 samiam9512
9x6-bit multiplier : 1
999
20 samiam9512
9x8-bit multiplier : 1
1000
28 samiam9512
# Adders/Subtractors : 55
1001
20 samiam9512
10-bit subtractor : 1
1002
18 samiam9512
11-bit adder : 5
1003
11-bit adder carry out : 1
1004
11-bit addsub : 1
1005
13-bit adder : 1
1006
11 samiam9512
16-bit adder : 7
1007
2 samiam9512
16-bit addsub : 1
1008
16-bit subtractor : 1
1009
17-bit adder : 8
1010
32-bit adder : 6
1011
32-bit subtractor : 3
1012
28 samiam9512
4-bit adder carry out : 1
1013
2 samiam9512
5-bit adder : 1
1014
20 samiam9512
5-bit subtractor : 1
1015
2 samiam9512
6-bit adder : 1
1016
6-bit subtractor : 2
1017
8-bit adder : 1
1018
8-bit adder carry out : 3
1019
8-bit addsub : 3
1020
9-bit adder : 3
1021
20 samiam9512
9-bit subtractor : 4
1022
# Counters : 6
1023
32-bit up counter : 1
1024
18 samiam9512
4-bit up counter : 1
1025
11 samiam9512
5-bit up counter : 2
1026
7-bit up counter : 1
1027
18 samiam9512
8-bit up counter : 1
1028
11 samiam9512
# Accumulators : 1
1029
11-bit up accumulator : 1
1030
28 samiam9512
# Registers : 580
1031
Flip-Flops : 580
1032
2 samiam9512
# Latches : 12
1033
6-bit latch : 4
1034
8-bit latch : 8
1035
20 samiam9512
# Comparators : 33
1036
18 samiam9512
11-bit comparator equal : 1
1037
11-bit comparator greatequal : 1
1038
11-bit comparator greater : 1
1039
11-bit comparator less : 5
1040
12-bit comparator greater : 2
1041
20 samiam9512
32-bit comparator greatequal : 1
1042
2 samiam9512
4-bit comparator equal : 1
1043
4-bit comparator greater : 2
1044
11 samiam9512
5-bit comparator greatequal : 1
1045
5-bit comparator less : 1
1046
2 samiam9512
6-bit comparator equal : 4
1047
11 samiam9512
7-bit comparator greatequal : 1
1048
7-bit comparator less : 1
1049
20 samiam9512
8-bit comparator greatequal : 4
1050
8-bit comparator greater : 1
1051
8-bit comparator less : 2
1052
8-bit comparator lessequal : 4
1053
28 samiam9512
# Multiplexers : 29
1054
20 samiam9512
1-bit 4-to-1 multiplexer : 17
1055
1-bit 8-to-1 multiplexer : 3
1056
16-bit 4-to-1 multiplexer : 1
1057
28 samiam9512
3-bit 4-to-1 multiplexer : 2
1058
8-bit 4-to-1 multiplexer : 3
1059
2 samiam9512
8-bit 8-to-1 multiplexer : 3
1060
20 samiam9512
# Xors : 3
1061
1-bit xor2 : 1
1062
2 samiam9512
1-bit xor8 : 1
1063
8-bit xor2 : 1
1064
1065
=========================================================================
1066
1067
=========================================================================
1068
* Low Level Synthesis *
1069
=========================================================================
1070
20 samiam9512
WARNING:Xst:1988 - Unit : instances , of unit and unit are dual, second instance is removed
1071
WARNING:Xst:1988 - Unit : instances , of unit and unit are dual, second instance is removed
1072
WARNING:Xst:1989 - Unit : instances , of unit are equivalent, second instance is removed
1073
11 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1074
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1075
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1076
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1077
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1078
20 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1079
11 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1080
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1081
20 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1082
11 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1083
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1084
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1085
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1086
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1087
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1088
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1089
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1090
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1091
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1092
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1093
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1094
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1095
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1096
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1097
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1098
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1099
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1100
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1101
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1102
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1103
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1104
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1105
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1106
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1107
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1108
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1109
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1110
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1111
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1112
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1113
20 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1114
11 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1115
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1116
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1117
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1118
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1119
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1120
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1121
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1122
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1123
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1124
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1125
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1126
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1127
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1128
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1129
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1130
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1131
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1132
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1133
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1134
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1135
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1136
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1137
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1138
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1139
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1140
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1141
20 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1142
11 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1143
20 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1144
11 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1145
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1146
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1147
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1148
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1149
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1150
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1151
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1152
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1153
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1154
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1155
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1156
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1157
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1158
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1159
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1160
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1161
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1162
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1163
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1164
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1165
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1166
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1167
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1168
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1169
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1170
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1171
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1172
20 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1173
11 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1174
20 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1175
11 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1176
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1177
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1178
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1179
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1180
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1181
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1182
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1183
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1184
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1185
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1186
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1187
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1188
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1189
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1190
20 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1191
11 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1192
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1193
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1194
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1195
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1196
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1197
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1198
18 samiam9512
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block .
1199
11 samiam9512
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .
1200
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .
1201
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .
1202
28 samiam9512
WARNING:Xst:2040 - Unit testbench: 21 multi-source signals are replaced by logic (pull-up yes): adm3a/cmattr<0>, adm3a/cmattr<1>, adm3a/cmattr<2>, adm3a/cmattr<3>, adm3a/cmattr<4>, adm3a/cmdata<0>, adm3a/cmdata<1>, adm3a/cmdata<2>, adm3a/cmdata<3>, adm3a/cmdata<4>, adm3a/cmdata<5>, adm3a/cmdata<6>, adm3a/cmdata<7>, N180, N182, N184, N186, N188, N190, N192, N194.
1203
20 samiam9512
WARNING:Xst:2042 - Unit chrmemmap: 13 internal tristates are replaced by logic (pull-up yes): attr<0>, attr<1>, attr<2>, attr<3>, attr<4>, data<0>, data<1>, data<2>, data<3>, data<4>, data<5>, data<6>, data<7>.
1204
2 samiam9512
1205
Optimizing unit ...
1206
1207
18 samiam9512
Optimizing unit ...
1208
1209
Optimizing unit ...
1210
1211
11 samiam9512
Optimizing unit ...
1212
1213
Optimizing unit ...
1214
1215
Optimizing unit ...
1216
1217
2 samiam9512
Mapping all equations...
1218
11 samiam9512
WARNING:Xst:1291 - FF/Latch is unconnected in block .
1219
2 samiam9512
Building and optimizing final netlist ...
1220
24 samiam9512
Found area constraint ratio of 100 (+ 5) on block testbench, actual ratio is 33.
1221
11 samiam9512
FlipFlop adm3a/cmaddr_0 has been replicated 5 time(s)
1222
FlipFlop adm3a/cmaddr_1 has been replicated 5 time(s)
1223
FlipFlop adm3a/cmaddr_2 has been replicated 5 time(s)
1224
FlipFlop adm3a/cmaddr_3 has been replicated 5 time(s)
1225
18 samiam9512
FlipFlop adm3a/display/chrcnt_0 has been replicated 1 time(s)
1226
FlipFlop adm3a/display/chrcnt_1 has been replicated 1 time(s)
1227
FlipFlop adm3a/display/chrcnt_2 has been replicated 1 time(s)
1228
FlipFlop adm3a/display/chrcnt_3 has been replicated 1 time(s)
1229
24 samiam9512
FlipFlop adm3a/display/rowcnt_0 has been replicated 1 time(s)
1230
28 samiam9512
FlipFlop adm3a/vgai/sc_r_5 has been replicated 1 time(s)
1231
18 samiam9512
FlipFlop cpu/addr_0 has been replicated 1 time(s)
1232
20 samiam9512
FlipFlop cpu/addr_1 has been replicated 2 time(s)
1233
18 samiam9512
FlipFlop cpu/addr_2 has been replicated 2 time(s)
1234
9 samiam9512
FlipFlop cpu/addr_3 has been replicated 1 time(s)
1235
20 samiam9512
FlipFlop cpu/readio has been replicated 1 time(s)
1236
2 samiam9512
1237
Final Macro Processing ...
1238
1239
11 samiam9512
Processing Unit :
1240
20 samiam9512
INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
1241
24 samiam9512
INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
1242
INFO:Xst:2387 - HDL ADVISOR - A 3-bit shift register was found for signal and currently occupies 3 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
1243
18 samiam9512
INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
1244
11 samiam9512
INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
1245
INFO:Xst:2387 - HDL ADVISOR - A 3-bit shift register was found for signal and currently occupies 3 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
1246
Unit processed.
1247
1248
2 samiam9512
=========================================================================
1249
Final Register Report
1250
1251
Macro Statistics
1252
28 samiam9512
# Registers : 668
1253
Flip-Flops : 668
1254
2 samiam9512
1255
=========================================================================
1256
1257
=========================================================================
1258
* Partition Report *
1259
=========================================================================
1260
1261
Partition Implementation Status
1262
-------------------------------
1263
1264
No Partitions were found in this design.
1265
1266
-------------------------------
1267
1268
=========================================================================
1269
* Final Report *
1270
=========================================================================
1271
Final Results
1272
RTL Top Level Output File Name : testbench.ngr
1273
Top Level Output File Name : testbench
1274
Output Format : NGC
1275
Optimization Goal : Speed
1276
Keep Hierarchy : NO
1277
1278
Design Statistics
1279
18 samiam9512
# IOs : 54
1280
2 samiam9512
1281
Cell Usage :
1282
28 samiam9512
# BELS : 6513
1283
2 samiam9512
# GND : 1
1284
24 samiam9512
# INV : 101
1285
28 samiam9512
# LUT1 : 231
1286
# LUT2 : 439
1287
# LUT2_D : 36
1288
# LUT2_L : 5
1289
# LUT3 : 1122
1290
# LUT3_D : 37
1291
# LUT3_L : 25
1292
# LUT4 : 2308
1293
# LUT4_D : 82
1294
# LUT4_L : 236
1295
2 samiam9512
# MULT_AND : 28
1296
28 samiam9512
# MUXCY : 655
1297
# MUXF5 : 612
1298
# MUXF6 : 175
1299
20 samiam9512
# MUXF7 : 59
1300
11 samiam9512
# MUXF8 : 23
1301
2 samiam9512
# VCC : 1
1302
28 samiam9512
# XORCY : 337
1303
# FlipFlops/Latches : 756
1304
18 samiam9512
# FD : 7
1305
# FDC : 23
1306
28 samiam9512
# FDCE : 56
1307
20 samiam9512
# FDE : 324
1308
18 samiam9512
# FDE_1 : 8
1309
# FDP : 6
1310
# FDPE : 21
1311
28 samiam9512
# FDR : 81
1312
24 samiam9512
# FDRE : 40
1313
18 samiam9512
# FDRE_1 : 42
1314
28 samiam9512
# FDRS : 46
1315
20 samiam9512
# FDRSE : 10
1316
18 samiam9512
# FDS : 3
1317
9 samiam9512
# FDSE : 1
1318
11 samiam9512
# LDCE : 56
1319
# LDE_1 : 32
1320
20 samiam9512
# RAMS : 844
1321
11 samiam9512
# RAM16X1D : 840
1322
18 samiam9512
# RAMB16_S9 : 3
1323
20 samiam9512
# RAMB16_S9_S9 : 1
1324
18 samiam9512
# Clock Buffers : 2
1325
2 samiam9512
# BUFGP : 2
1326
18 samiam9512
# IO Buffers : 52
1327
# IBUF : 2
1328
2 samiam9512
# IOBUF : 8
1329
18 samiam9512
# OBUF : 42
1330
20 samiam9512
# MULTs : 2
1331
# MULT18X18 : 2
1332
2 samiam9512
=========================================================================
1333
1334
Device utilization summary:
1335
---------------------------
1336
1337
11 samiam9512
Selected Device : 3s1000ft256-4
1338
2 samiam9512
1339
28 samiam9512
Number of Slices: 2416 out of 7680 31%
1340
Number of Slice Flip Flops: 756 out of 15360 4%
1341
Number of 4 input LUTs: 6302 out of 15360 41%
1342
Number used as logic: 4622
1343
11 samiam9512
Number used as RAMs: 1680
1344
18 samiam9512
Number of IOs: 54
1345
Number of bonded IOBs: 54 out of 173 31%
1346
20 samiam9512
Number of BRAMs: 4 out of 24 16%
1347
Number of MULT18X18s: 2 out of 24 8%
1348
18 samiam9512
Number of GCLKs: 2 out of 8 25%
1349
2 samiam9512
1350
1351
=========================================================================
1352
TIMING REPORT
1353
1354
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
1355
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
1356
GENERATED AFTER PLACE-and-ROUTE.
1357
1358
Clock Information:
1359
------------------
1360
-----------------------------------------------------+--------------------------------+-------+
1361
Clock Signal | Clock buffer(FF name) | Load |
1362
-----------------------------------------------------+--------------------------------+-------+
1363
28 samiam9512
clock | BUFGP | 1509 |
1364
11 samiam9512
reset_n | BUFGP | 32 |
1365
28 samiam9512
select1/selectd/_and0000(select1/selectd/_and00001:O)| NONE(*)(select1/selectd/mask_5)| 14 |
1366
select1/selectc/_and0000(select1/selectc/_and00001:O)| NONE(*)(select1/selectc/comp_2)| 14 |
1367
select1/selectb/_and0000(select1/selectb/_and00001:O)| NONE(*)(select1/selectb/mask_7)| 14 |
1368
select1/selecta/_and0000(select1/selecta/_and00001:O)| NONE(*)(select1/selecta/mask_7)| 14 |
1369
2 samiam9512
-----------------------------------------------------+--------------------------------+-------+
1370
(*) These 4 clock signal(s) are generated by combinatorial logic,
1371
and XST is not able to identify which are the primary clock signals.
1372
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
1373
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
1374
1375
Asynchronous Control Signals Information:
1376
----------------------------------------
1377
28 samiam9512
-----------------------------------+------------------------------------------------------+-------+
1378
Control Signal | Buffer(FF name) | Load |
1379
-----------------------------------+------------------------------------------------------+-------+
1380
reset(reset1_INV_0:O) | NONE(adm3a/display/vgai/gen_syncs_fit.vsync/cnt_r_10)| 162 |
1381
-----------------------------------+------------------------------------------------------+-------+
1382
2 samiam9512
1383
Timing Summary:
1384
---------------
1385
11 samiam9512
Speed Grade: -4
1386
2 samiam9512
1387
28 samiam9512
Minimum period: 21.437ns (Maximum Frequency: 46.649MHz)
1388
Minimum input arrival time before clock: 8.841ns
1389
24 samiam9512
Maximum output required time after clock: 18.905ns
1390
18 samiam9512
Maximum combinational path delay: 7.342ns
1391
2 samiam9512
1392
Timing Detail:
1393
--------------
1394
All values displayed in nanoseconds (ns)
1395
1396
=========================================================================
1397
Timing constraint: Default period analysis for Clock 'clock'
1398
28 samiam9512
Clock period: 21.437ns (frequency: 46.649MHz)
1399
Total number of paths / destination ports: 238171 / 9398
1400
2 samiam9512
-------------------------------------------------------------------------
1401
28 samiam9512
Delay: 21.437ns (Levels of Logic = 15)
1402
Source: adm3a/display/curchr_6 (FF)
1403
Destination: adm3a/display/pixeldata_10 (FF)
1404
2 samiam9512
Source Clock: clock rising
1405
28 samiam9512
Destination Clock: clock rising
1406
2 samiam9512
1407
28 samiam9512
Data Path: adm3a/display/curchr_6 to adm3a/display/pixeldata_10
1408
2 samiam9512
Gate Net
1409
Cell:in->out fanout Delay Delay Logical Name (Net Name)
1410
---------------------------------------- ------------
1411
28 samiam9512
FD:C->Q 2 0.720 0.877 adm3a/display/curchr_6 (adm3a/display/curchr_6)
1412
MULT18X18:A0->P0 39 1.779 2.088 adm3a/display/Mmult__mult0002 (adm3a/display/_mult0002<0>)
1413
LUT2:I1->O 1 0.551 0.000 adm3a/display/Madd__addsub0001_lut<0>_1 (adm3a/display/Madd__addsub0001_lut<0>)
1414
MUXCY:S->O 1 0.500 0.000 adm3a/display/Madd__addsub0001_cy<0> (adm3a/display/Madd__addsub0001_cy<0>)
1415
MUXCY:CI->O 1 0.064 0.000 adm3a/display/Madd__addsub0001_cy<1> (adm3a/display/Madd__addsub0001_cy<1>)
1416
XORCY:CI->O 145 0.904 2.526 adm3a/display/Madd__addsub0001_xor<2> (adm3a/display/_addsub0001<2>)
1417
LUT4_D:I3->O 1 0.551 0.869 adm3a/display/crom/Mrom_data145_SW3 (N16984)
1418
LUT4:I2->O 7 0.551 1.092 adm3a/display/crom/Mrom_data145 (adm3a/display/N149)
1419
LUT4:I3->O 1 0.551 0.827 adm3a/display/chradr<4>173 (adm3a/display/N19411)
1420
LUT4:I3->O 1 0.551 0.000 adm3a/display/chradr<7>1555_G (N17173)
1421
MUXF5:I1->O 1 0.360 0.827 adm3a/display/chradr<7>1555 (adm3a/display/chradr<7>15_map5531)
1422
LUT4:I3->O 1 0.551 0.827 adm3a/display/chradr<7>1557 (adm3a/display/chradr<7>12)
1423
LUT4:I3->O 1 0.551 0.000 adm3a/display/chradr<9>_f5_2_F (N17190)
1424
MUXF5:I0->O 1 0.360 0.827 adm3a/display/chradr<9>_f5_2 (adm3a/display/chradr<9>_f53)
1425
LUT4_D:I3->O 1 0.551 0.827 adm3a/display/chradr<10>111411 (adm3a/display/N2731)
1426
LUT4:I3->O 1 0.551 0.000 adm3a/display/_mux0011<10>1 (adm3a/display/_mux0011<10>)
1427
FDE:D 0.203 adm3a/display/pixeldata_10
1428
2 samiam9512
----------------------------------------
1429
28 samiam9512
Total 21.437ns (9.849ns logic, 11.588ns route)
1430
(45.9% logic, 54.1% route)
1431
2 samiam9512
1432
=========================================================================
1433
Timing constraint: Default OFFSET IN BEFORE for Clock 'clock'
1434
28 samiam9512
Total number of paths / destination ports: 639 / 639
1435
2 samiam9512
-------------------------------------------------------------------------
1436
28 samiam9512
Offset: 8.841ns (Levels of Logic = 2)
1437
11 samiam9512
Source: reset_n (PAD)
1438
18 samiam9512
Destination: cpu/readmem (FF)
1439
2 samiam9512
Destination Clock: clock rising
1440
1441
18 samiam9512
Data Path: reset_n to cpu/readmem
1442
2 samiam9512
Gate Net
1443
Cell:in->out fanout Delay Delay Logical Name (Net Name)
1444
---------------------------------------- ------------
1445
28 samiam9512
BUFGP:I->O 248 0.401 3.090 reset_n_BUFGP (reset_n_BUFGP)
1446
INV:I->O 367 0.551 3.772 reset1_INV_0 (reset)
1447
FDRSE:R 1.026 cpu/writeio
1448
2 samiam9512
----------------------------------------
1449
28 samiam9512
Total 8.841ns (1.978ns logic, 6.863ns route)
1450
(22.4% logic, 77.6% route)
1451
2 samiam9512
1452
=========================================================================
1453
Timing constraint: Default OFFSET IN BEFORE for Clock 'select1/selectd/_and0000'
1454
11 samiam9512
Total number of paths / destination ports: 14 / 14
1455
2 samiam9512
-------------------------------------------------------------------------
1456
11 samiam9512
Offset: 2.474ns (Levels of Logic = 1)
1457
Source: data<6> (PAD)
1458
Destination: select1/selectd/mask_6 (LATCH)
1459
2 samiam9512
Destination Clock: select1/selectd/_and0000 falling
1460
1461
11 samiam9512
Data Path: data<6> to select1/selectd/mask_6
1462
2 samiam9512
Gate Net
1463
Cell:in->out fanout Delay Delay Logical Name (Net Name)
1464
---------------------------------------- ------------
1465
28 samiam9512
IOBUF:IO->O 19 0.821 1.450 data_6_IOBUF (N16300)
1466
11 samiam9512
LDCE:D 0.203 select1/selectd/mask_6
1467
2 samiam9512
----------------------------------------
1468
11 samiam9512
Total 2.474ns (1.024ns logic, 1.450ns route)
1469
(41.4% logic, 58.6% route)
1470
2 samiam9512
1471
=========================================================================
1472
Timing constraint: Default OFFSET IN BEFORE for Clock 'select1/selectc/_and0000'
1473
9 samiam9512
Total number of paths / destination ports: 14 / 14
1474
2 samiam9512
-------------------------------------------------------------------------
1475
11 samiam9512
Offset: 2.474ns (Levels of Logic = 1)
1476
Source: data<6> (PAD)
1477
Destination: select1/selectc/mask_6 (LATCH)
1478
2 samiam9512
Destination Clock: select1/selectc/_and0000 falling
1479
1480
11 samiam9512
Data Path: data<6> to select1/selectc/mask_6
1481
2 samiam9512
Gate Net
1482
Cell:in->out fanout Delay Delay Logical Name (Net Name)
1483
---------------------------------------- ------------
1484
28 samiam9512
IOBUF:IO->O 19 0.821 1.450 data_6_IOBUF (N16300)
1485
11 samiam9512
LDCE:D 0.203 select1/selectc/mask_6
1486
2 samiam9512
----------------------------------------
1487
11 samiam9512
Total 2.474ns (1.024ns logic, 1.450ns route)
1488
(41.4% logic, 58.6% route)
1489
2 samiam9512
1490
=========================================================================
1491
Timing constraint: Default OFFSET IN BEFORE for Clock 'select1/selectb/_and0000'
1492
Total number of paths / destination ports: 14 / 14
1493
-------------------------------------------------------------------------
1494
11 samiam9512
Offset: 2.474ns (Levels of Logic = 1)
1495
Source: data<6> (PAD)
1496
Destination: select1/selectb/mask_6 (LATCH)
1497
2 samiam9512
Destination Clock: select1/selectb/_and0000 falling
1498
1499
11 samiam9512
Data Path: data<6> to select1/selectb/mask_6
1500
2 samiam9512
Gate Net
1501
Cell:in->out fanout Delay Delay Logical Name (Net Name)
1502
---------------------------------------- ------------
1503
28 samiam9512
IOBUF:IO->O 19 0.821 1.450 data_6_IOBUF (N16300)
1504
11 samiam9512
LDCE:D 0.203 select1/selectb/mask_6
1505
2 samiam9512
----------------------------------------
1506
11 samiam9512
Total 2.474ns (1.024ns logic, 1.450ns route)
1507
(41.4% logic, 58.6% route)
1508
2 samiam9512
1509
=========================================================================
1510
Timing constraint: Default OFFSET IN BEFORE for Clock 'select1/selecta/_and0000'
1511
Total number of paths / destination ports: 14 / 14
1512
-------------------------------------------------------------------------
1513
11 samiam9512
Offset: 2.474ns (Levels of Logic = 1)
1514
Source: data<6> (PAD)
1515
Destination: select1/selecta/mask_6 (LATCH)
1516
2 samiam9512
Destination Clock: select1/selecta/_and0000 falling
1517
1518
11 samiam9512
Data Path: data<6> to select1/selecta/mask_6
1519
2 samiam9512
Gate Net
1520
Cell:in->out fanout Delay Delay Logical Name (Net Name)
1521
---------------------------------------- ------------
1522
28 samiam9512
IOBUF:IO->O 19 0.821 1.450 data_6_IOBUF (N16300)
1523
11 samiam9512
LDCE:D 0.203 select1/selecta/mask_6
1524
2 samiam9512
----------------------------------------
1525
11 samiam9512
Total 2.474ns (1.024ns logic, 1.450ns route)
1526
(41.4% logic, 58.6% route)
1527
2 samiam9512
1528
=========================================================================
1529
18 samiam9512
Timing constraint: Default OFFSET OUT AFTER for Clock 'clock'
1530
24 samiam9512
Total number of paths / destination ports: 2377 / 47
1531
2 samiam9512
-------------------------------------------------------------------------
1532
24 samiam9512
Offset: 18.905ns (Levels of Logic = 8)
1533
Source: cpu/addr_4 (FF)
1534
2 samiam9512
Destination: data<7> (PAD)
1535
18 samiam9512
Source Clock: clock rising
1536
2 samiam9512
1537
24 samiam9512
Data Path: cpu/addr_4 to data<7>
1538
2 samiam9512
Gate Net
1539
Cell:in->out fanout Delay Delay Logical Name (Net Name)
1540
---------------------------------------- ------------
1541
24 samiam9512
FDE:C->Q 8 0.720 1.278 cpu/addr_4 (cpu/addr_4)
1542
28 samiam9512
LUT4:I1->O 3 0.551 1.246 select1/selacc426 (select1/selacc4_map5652)
1543
24 samiam9512
LUT2:I0->O 3 0.551 1.246 select1/selacc454 (select1/selacc)
1544
LUT4:I0->O 9 0.551 1.150 select1/selecta/_and0001_inv1 (select1/selecta/_and0001_inv)
1545
28 samiam9512
LUT4:I3->O 1 0.551 0.996 N186LogicTrst63_SW0 (N17403)
1546
LUT4:I1->O 1 0.551 1.140 N186LogicTrst63 (N186LogicTrst_map6210)
1547
LUT4:I0->O 1 0.551 0.827 N186LogicTrst126_SW0 (N17405)
1548
LUT4:I3->O 1 0.551 0.801 N186LogicTrst126 (data_4_IOBUF)
1549
24 samiam9512
IOBUF:I->IO 5.644 data_4_IOBUF (data<4>)
1550
2 samiam9512
----------------------------------------
1551
24 samiam9512
Total 18.905ns (10.221ns logic, 8.684ns route)
1552
20 samiam9512
(54.1% logic, 45.9% route)
1553
2 samiam9512
1554
=========================================================================
1555
24 samiam9512
Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selecta/_and0000'
1556
Total number of paths / destination ports: 840 / 8
1557
2 samiam9512
-------------------------------------------------------------------------
1558
24 samiam9512
Offset: 18.295ns (Levels of Logic = 8)
1559
Source: select1/selecta/mask_1 (LATCH)
1560
2 samiam9512
Destination: data<7> (PAD)
1561
24 samiam9512
Source Clock: select1/selecta/_and0000 falling
1562
2 samiam9512
1563
24 samiam9512
Data Path: select1/selecta/mask_1 to data<7>
1564
2 samiam9512
Gate Net
1565
Cell:in->out fanout Delay Delay Logical Name (Net Name)
1566
---------------------------------------- ------------
1567
24 samiam9512
LDCE:G->Q 7 0.633 1.405 select1/selecta/mask_1 (select1/selecta/mask_1)
1568
28 samiam9512
LUT4:I0->O 1 0.551 0.000 _and0000_inv181 (N18091)
1569
MUXF5:I1->O 1 0.360 1.140 _and0000_inv18_f5 (_and0000_inv_map5862)
1570
LUT4:I0->O 1 0.551 1.140 _and0000_inv108 (_and0000_inv_map5889)
1571
24 samiam9512
LUT4:I0->O 9 0.551 1.150 _and0000_inv211 (_and0000_inv)
1572
28 samiam9512
LUT4:I3->O 1 0.551 1.140 N180LogicTrst120 (N180LogicTrst1_map5994)
1573
LUT4:I0->O 16 0.551 1.576 N180LogicTrst142 (N269)
1574
LUT3:I0->O 1 0.551 0.801 N194LogicTrst108 (data_0_IOBUF)
1575
24 samiam9512
IOBUF:I->IO 5.644 data_0_IOBUF (data<0>)
1576
2 samiam9512
----------------------------------------
1577
24 samiam9512
Total 18.295ns (9.943ns logic, 8.352ns route)
1578
(54.3% logic, 45.7% route)
1579
2 samiam9512
1580
=========================================================================
1581
24 samiam9512
Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selectd/_and0000'
1582
Total number of paths / destination ports: 624 / 8
1583
2 samiam9512
-------------------------------------------------------------------------
1584
28 samiam9512
Offset: 17.289ns (Levels of Logic = 8)
1585
24 samiam9512
Source: select1/selectd/mask_1 (LATCH)
1586
2 samiam9512
Destination: data<7> (PAD)
1587
24 samiam9512
Source Clock: select1/selectd/_and0000 falling
1588
2 samiam9512
1589
24 samiam9512
Data Path: select1/selectd/mask_1 to data<7>
1590
2 samiam9512
Gate Net
1591
Cell:in->out fanout Delay Delay Logical Name (Net Name)
1592
---------------------------------------- ------------
1593
24 samiam9512
LDCE:G->Q 7 0.633 1.405 select1/selectd/mask_1 (select1/selectd/mask_1)
1594
28 samiam9512
LUT4:I0->O 1 0.551 0.000 select1/selectd/selectout791 (N18071)
1595
MUXF5:I1->O 1 0.360 1.140 select1/selectd/selectout79_f5 (select1/selectd/selectout_map5690)
1596
LUT4_D:I0->O 3 0.551 0.975 select1/selectd/selectout169 (select1/selectd/selectout_map5717)
1597
LUT3:I2->O 17 0.551 1.371 adm3a/_and00001 (adm3a/_and0000)
1598
LUT4:I3->O 1 0.551 0.827 N182LogicTrst113 (N182LogicTrst_map6158)
1599
LUT4:I3->O 1 0.551 0.827 N182LogicTrst126_SW0 (N17397)
1600
LUT4:I3->O 1 0.551 0.801 N182LogicTrst126 (data_6_IOBUF)
1601
24 samiam9512
IOBUF:I->IO 5.644 data_6_IOBUF (data<6>)
1602
2 samiam9512
----------------------------------------
1603
28 samiam9512
Total 17.289ns (9.943ns logic, 7.346ns route)
1604
(57.5% logic, 42.5% route)
1605
2 samiam9512
1606
=========================================================================
1607
24 samiam9512
Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selectb/_and0000'
1608
11 samiam9512
Total number of paths / destination ports: 840 / 8
1609
2 samiam9512
-------------------------------------------------------------------------
1610
24 samiam9512
Offset: 16.855ns (Levels of Logic = 8)
1611
Source: select1/selectb/comp_1 (LATCH)
1612
18 samiam9512
Destination: data<7> (PAD)
1613
24 samiam9512
Source Clock: select1/selectb/_and0000 falling
1614
11 samiam9512
1615
24 samiam9512
Data Path: select1/selectb/comp_1 to data<7>
1616
11 samiam9512
Gate Net
1617
Cell:in->out fanout Delay Delay Logical Name (Net Name)
1618
---------------------------------------- ------------
1619
24 samiam9512
LDCE:G->Q 3 0.633 1.246 select1/selectb/comp_1 (select1/selectb/comp_1)
1620
28 samiam9512
LUT4:I0->O 1 0.551 0.000 select1/select248_SW02 (N18126)
1621
MUXF5:I0->O 2 0.360 1.072 select1/select248_SW0_f5 (N17258)
1622
LUT4:I1->O 1 0.551 0.000 select1/select2482 (N18128)
1623
MUXF5:I0->O 2 0.360 1.216 select1/select248_f5 (select1/select2_map5800)
1624
24 samiam9512
LUT4:I0->O 9 0.551 1.192 ram/_and0000_inv1 (ram/_and0000_inv)
1625
28 samiam9512
LUT4:I2->O 16 0.551 1.576 N180LogicTrst142 (N269)
1626
LUT3:I0->O 1 0.551 0.801 N194LogicTrst108 (data_0_IOBUF)
1627
24 samiam9512
IOBUF:I->IO 5.644 data_0_IOBUF (data<0>)
1628
11 samiam9512
----------------------------------------
1629
24 samiam9512
Total 16.855ns (9.752ns logic, 7.103ns route)
1630
(57.9% logic, 42.1% route)
1631
11 samiam9512
1632
=========================================================================
1633
24 samiam9512
Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selectc/_and0000'
1634
Total number of paths / destination ports: 552 / 8
1635
11 samiam9512
-------------------------------------------------------------------------
1636
24 samiam9512
Offset: 18.172ns (Levels of Logic = 8)
1637
Source: select1/selectc/mask_1 (LATCH)
1638
9 samiam9512
Destination: data<7> (PAD)
1639
24 samiam9512
Source Clock: select1/selectc/_and0000 falling
1640
2 samiam9512
1641
24 samiam9512
Data Path: select1/selectc/mask_1 to data<7>
1642
2 samiam9512
Gate Net
1643
Cell:in->out fanout Delay Delay Logical Name (Net Name)
1644
---------------------------------------- ------------
1645
24 samiam9512
LDCE:G->Q 7 0.633 1.405 select1/selectc/mask_1 (select1/selectc/mask_1)
1646
28 samiam9512
LUT4:I0->O 1 0.551 0.000 select1/selectc/selectout1511 (N18101)
1647
MUXF5:I1->O 2 0.360 1.216 select1/selectc/selectout151_f5 (select1/selectc/selectout_map6331)
1648
24 samiam9512
LUT4_D:I0->O 1 0.551 0.827 select1/selectc/selectout169_1 (select1/selectc/selectout169)
1649
LUT4_D:I3->O 12 0.551 1.457 intc/_not0027_SW0 (intc/_and0009)
1650
LUT2:I0->O 5 0.551 0.947 intc/_or0000_inv1 (intc/_or0000_inv)
1651
28 samiam9512
LUT4:I3->O 16 0.551 1.576 N180LogicTrst142 (N269)
1652
LUT3:I0->O 1 0.551 0.801 N194LogicTrst108 (data_0_IOBUF)
1653
24 samiam9512
IOBUF:I->IO 5.644 data_0_IOBUF (data<0>)
1654
2 samiam9512
----------------------------------------
1655
24 samiam9512
Total 18.172ns (9.943ns logic, 8.229ns route)
1656
(54.7% logic, 45.3% route)
1657
2 samiam9512
1658
=========================================================================
1659
18 samiam9512
Timing constraint: Default OFFSET OUT AFTER for Clock 'reset_n'
1660
Total number of paths / destination ports: 32 / 8
1661
9 samiam9512
-------------------------------------------------------------------------
1662
24 samiam9512
Offset: 15.954ns (Levels of Logic = 7)
1663
18 samiam9512
Source: select1/selectb/datai_3 (LATCH)
1664
Destination: data<3> (PAD)
1665
Source Clock: reset_n falling
1666
9 samiam9512
1667
18 samiam9512
Data Path: select1/selectb/datai_3 to data<3>
1668
9 samiam9512
Gate Net
1669
Cell:in->out fanout Delay Delay Logical Name (Net Name)
1670
---------------------------------------- ------------
1671
18 samiam9512
LDE_1:G->Q 1 0.633 0.869 select1/selectb/datai_3 (select1/selectb/datai_3)
1672
28 samiam9512
LUT4:I2->O 1 0.551 0.996 N188LogicTrst26 (N188LogicTrst_map6009)
1673
LUT4:I1->O 1 0.551 0.827 N188LogicTrst34 (N188LogicTrst_map6011)
1674
LUT4:I3->O 1 0.551 0.869 N188LogicTrst61 (N188LogicTrst_map6017)
1675
LUT3:I2->O 1 0.551 1.140 N188LogicTrst95_SW0 (N17625)
1676
LUT4:I0->O 1 0.551 0.869 N188LogicTrst95 (N188LogicTrst_map6023)
1677
LUT3:I2->O 1 0.551 0.801 N188LogicTrst108 (data_3_IOBUF)
1678
18 samiam9512
IOBUF:I->IO 5.644 data_3_IOBUF (data<3>)
1679
9 samiam9512
----------------------------------------
1680
24 samiam9512
Total 15.954ns (9.583ns logic, 6.371ns route)
1681
(60.1% logic, 39.9% route)
1682
9 samiam9512
1683
=========================================================================
1684
18 samiam9512
Timing constraint: Default path analysis
1685
Total number of paths / destination ports: 2 / 2
1686
11 samiam9512
-------------------------------------------------------------------------
1687
18 samiam9512
Delay: 7.342ns (Levels of Logic = 2)
1688
Source: ps2_data (PAD)
1689
Destination: diag<4> (PAD)
1690
11 samiam9512
1691
18 samiam9512
Data Path: ps2_data to diag<4>
1692
11 samiam9512
Gate Net
1693
Cell:in->out fanout Delay Delay Logical Name (Net Name)
1694
---------------------------------------- ------------
1695
18 samiam9512
IBUF:I->O 2 0.821 0.877 ps2_data_IBUF (ps2_data_IBUF)
1696
OBUF:I->O 5.644 diag_4_OBUF (diag<4>)
1697
11 samiam9512
----------------------------------------
1698
18 samiam9512
Total 7.342ns (6.465ns logic, 0.877ns route)
1699
(88.1% logic, 11.9% route)
1700
11 samiam9512
1701
=========================================================================
1702
28 samiam9512
CPU : 243.39 / 243.99 s | Elapsed : 243.00 / 244.00 s
1703
2 samiam9512
1704
-->
1705
1706
28 samiam9512
Total memory usage is 241168 kilobytes
1707
2 samiam9512
1708
Number of errors : 0 ( 0 filtered)
1709
20 samiam9512
Number of warnings : 162 ( 0 filtered)
1710
Number of infos : 14 ( 0 filtered)
1711
2 samiam9512
