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Release 8.2.02i - xst I.33
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Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
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--> Parameter TMPDIR set to ./xst/projnav.tmp
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CPU : 0.00 / 0.20 s | Elapsed : 0.00 / 0.00 s
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--> Parameter xsthdpdir set to ./xst
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CPU : 0.00 / 0.20 s | Elapsed : 0.00 / 0.00 s
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--> Reading design: testbench.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Compilation
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3) Design Hierarchy Analysis
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4) HDL Analysis
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5) HDL Synthesis
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5.1) HDL Synthesis Report
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6) Advanced HDL Synthesis
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6.1) Advanced HDL Synthesis Report
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7) Low Level Synthesis
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8) Partition Report
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9) Final Report
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9.1) Device utilization summary
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9.2) TIMING REPORT
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "testbench.prj"
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "testbench"
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Output Format : NGC
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Target Device : xc3s200-5-pq208
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---- Source Options
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Top Module Name : testbench
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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FSM Style : lut
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RAM Extraction : Yes
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RAM Style : Auto
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ROM Extraction : Yes
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Mux Style : Auto
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Decoder Extraction : YES
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Priority Encoder Extraction : YES
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Shift Register Extraction : YES
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Logical Shifter Extraction : YES
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XOR Collapsing : YES
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ROM Style : Auto
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Mux Extraction : YES
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Resource Sharing : YES
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Multiplier Style : auto
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Automatic Register Balancing : No
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---- Target Options
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Add IO Buffers : YES
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Global Maximum Fanout : 500
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Add Generic Clock Buffer(BUFG) : 8
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Register Duplication : YES
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Slice Packing : YES
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Pack IO Registers into IOBs : auto
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 1
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Keep Hierarchy : NO
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RTL Output : Yes
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Global Optimization : AllClockNets
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Write Timing Constraints : NO
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : maintain
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Slice Utilization Ratio : 100
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Slice Utilization Ratio Delta : 5
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---- Other Options
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lso : testbench.lso
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Read Cores : YES
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cross_clock_analysis : NO
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verilog2001 : YES
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safe_implementation : No
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Optimize Instantiated Primitives : NO
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use_clock_enable : Yes
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use_sync_set : Yes
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use_sync_reset : Yes
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=========================================================================
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling verilog file "cpu8080.v" in library work
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Module compiled
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Compiling verilog file "testbench.v" in library work
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Module compiled
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Module compiled
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Module compiled
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Module compiled
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Module compiled
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Compiling verilog include file "test.lst"
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Module compiled
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Module compiled
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No errors in compilation
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Analysis of file <"testbench.prj"> succeeded.
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=========================================================================
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* Design Hierarchy Analysis *
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=========================================================================
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Building hierarchy successfully finished.
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=========================================================================
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* HDL Analysis *
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=========================================================================
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Analyzing top module .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Performing bidirectional port resolution...
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INFO:Xst:1304 - Contents of register in unit never changes during circuit operation. The register is replaced by logic.
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Synthesizing Unit .
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Related source file is "testbench.v".
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Found 512x8-bit ROM for signal <$mux0000>.
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Found 8-bit tristate buffer for signal .
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Summary:
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inferred 1 ROM(s).
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inferred 8 Tristate(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "testbench.v".
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Found 1024x8-bit single-port block RAM for signal .
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-----------------------------------------------------------------------
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| ram_style | Auto | |
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-----------------------------------------------------------------------
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| Port A |
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| aspect ratio | 1024-word x 8-bit | |
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| mode | read-first | |
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| clkA | connected to signal | fall |
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| enA | connected to signal | high |
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| weA | connected to signal | high |
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| addrA | connected to signal | |
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| diA | connected to signal | |
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| doA | connected to signal | |
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-----------------------------------------------------------------------
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Found 8-bit tristate buffer for signal .
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Summary:
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inferred 1 RAM(s).
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inferred 8 Tristate(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "testbench.v".
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Found finite state machine for signal .
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-----------------------------------------------------------------------
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| States | 3 |
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| Transitions | 3 |
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| Inputs | 0 |
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| Outputs | 4 |
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| Clock | clock (falling_edge) |
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| Clock enable | $not0004 (positive) |
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| Reset | reset (positive) |
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| Reset type | synchronous |
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| Reset State | 0000 |
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| Encoding | automatic |
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| Implementation | LUT |
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-----------------------------------------------------------------------
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Found 8-bit tristate buffer for signal .
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Found 1-bit 4-to-1 multiplexer for signal <$mux0000>.
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Found 1-bit 4-to-1 multiplexer for signal <$mux0001>.
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Found 1-bit 4-to-1 multiplexer for signal <$mux0002>.
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Found 1-bit 4-to-1 multiplexer for signal <$mux0003>.
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Found 1-bit 4-to-1 multiplexer for signal <$mux0004>.
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Found 1-bit 4-to-1 multiplexer for signal <$mux0005>.
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Found 1-bit 4-to-1 multiplexer for signal <$mux0006>.
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Found 1-bit 4-to-1 multiplexer for signal <$mux0007>.
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Found 8-bit register for signal .
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Found 8-bit register for signal .
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Found 8-bit register for signal .
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Found 8-bit register for signal .
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Found 8-bit register for signal .
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Found 8-bit register for signal .
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Summary:
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inferred 1 Finite State Machine(s).
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inferred 48 D-type flip-flop(s).
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inferred 8 Multiplexer(s).
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inferred 8 Tristate(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "testbench.v".
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WARNING:Xst:647 - Input > is never used.
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WARNING:Xst:647 - Input > is never used.
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WARNING:Xst:737 - Found 6-bit latch for signal .
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WARNING:Xst:737 - Found 8-bit latch for signal .
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WARNING:Xst:737 - Found 8-bit latch for signal .
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Found 8-bit tristate buffer for signal .
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Found 6-bit comparator equal for signal <$cmp_eq0000> created at line 264.
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Summary:
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inferred 1 Comparator(s).
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inferred 8 Tristate(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "cpu8080.v".
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WARNING:Xst:646 - Signal is assigned but never used.
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Found 1-bit 8-to-1 multiplexer for signal .
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Found 1-bit 8-to-1 multiplexer for signal .
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Found 5-bit adder for signal <$add0001> created at line 1476.
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Found 8-bit adder carry out for signal <$addsub0000> created at line 1469.
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Found 4-bit adder carry out for signal <$addsub0001> created at line 1470.
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Found 6-bit subtractor for signal <$sub0000> created at line 1482.
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Found 6-bit subtractor for signal <$sub0001> created at line 1488.
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Found 9-bit subtractor for signal <$sub0002> created at line 1481.
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Found 8-bit xor2 for signal <$xor0000> created at line 1499.
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Found 1-bit xor8 for signal <$xor0002>.
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Summary:
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inferred 8 Adder/Subtractor(s).
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inferred 10 Multiplexer(s).
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inferred 1 Xor(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "testbench.v".
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Found 1-bit register for signal .
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Found 8-bit tristate buffer for signal .
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Found 8-bit register for signal .
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Found 4-bit comparator equal for signal .
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Found 4-bit register for signal .
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Summary:
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inferred 13 D-type flip-flop(s).
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inferred 1 Comparator(s).
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inferred 8 Tristate(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "cpu8080.v".
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Found finite state machine for signal .
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-----------------------------------------------------------------------
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| States | 30 |
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| Transitions | 899 |
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| Inputs | 140 |
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| Outputs | 31 |
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| Clock | clock (rising_edge) |
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| Reset | reset (positive) |
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| Reset type | synchronous |
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| Reset State | 00001 |
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| Encoding | automatic |
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| Implementation | LUT |
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-----------------------------------------------------------------------
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Found 4x1-bit ROM for signal <$mux0042> created at line 293.
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Found 16-bit register for signal .
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Found 1-bit register for signal .
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Found 1-bit register for signal .
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Found 1-bit register for signal .
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Found 1-bit register for signal .
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Found 1-bit register for signal .
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Found 8-bit tristate buffer for signal .
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Found 32-bit adder for signal <$add0001> created at line 475.
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Found 32-bit adder for signal <$add0002> created at line 487.
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Found 32-bit adder for signal <$add0003> created at line 499.
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Found 16-bit adder for signal <$add0004> created at line 959.
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Found 16-bit adder for signal <$add0005> created at line 870.
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Found 32-bit adder for signal <$add0006> created at line 544.
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Found 32-bit adder for signal <$add0007> created at line 532.
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Found 32-bit adder for signal <$add0008> created at line 520.
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Found 17-bit adder for signal <$add0009> created at line 465.
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Found 17-bit adder for signal <$addsub0000>.
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Found 17-bit adder for signal <$addsub0001>.
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Found 17-bit adder for signal <$addsub0002>.
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Found 8-bit adder for signal <$addsub0003>.
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Found 8-bit addsub for signal <$addsub0004>.
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Found 8-bit addsub for signal <$addsub0005>.
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Found 8-bit addsub for signal <$addsub0006>.
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Found 16-bit adder for signal <$addsub0007> created at line 1030.
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Found 16-bit adder for signal <$addsub0008> created at line 1071.
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Found 8-bit adder carry out for signal <$addsub0009>.
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Found 4-bit adder carry out for signal <$addsub0010> created at line 340.
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Found 8-bit adder carry out for signal <$addsub0011>.
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Found 4-bit comparator greater for signal <$cmp_gt0000> created at line 337.
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Found 4-bit comparator greater for signal <$cmp_gt0001> created at line 1286.
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Found 3-bit 4-to-1 multiplexer for signal <$mux0021> created at line 293.
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Found 8-bit 4-to-1 multiplexer for signal <$mux0022> created at line 293.
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Found 3-bit 4-to-1 multiplexer for signal <$mux0024> created at line 293.
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Found 8-bit 4-to-1 multiplexer for signal <$mux0030> created at line 293.
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Found 3-bit 4-to-1 multiplexer for signal <$mux0044>.
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Found 3-bit 4-to-1 multiplexer for signal <$mux0049> created at line 297.
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Found 8-bit 4-to-1 multiplexer for signal <$mux0050>.
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Found 16-bit adder for signal <$share0000> created at line 293.
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Found 6-bit adder for signal <$share0005> created at line 260.
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Found 16-bit addsub for signal <$share0006> created at line 293.
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Found 32-bit subtractor for signal <$sub0000> created at line 520.
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Found 32-bit subtractor for signal <$sub0001> created at line 532.
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Found 32-bit subtractor for signal <$sub0002> created at line 544.
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Found 16-bit subtractor for signal <$sub0003> created at line 741.
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Found 1-bit register for signal .
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Found 8-bit register for signal .
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Found 8-bit register for signal .
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Found 3-bit register for signal .
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Found 1-bit register for signal .
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Found 1-bit register for signal .
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Found 1-bit register for signal .
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Found 8-bit register for signal .
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Found 1-bit register for signal .
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Found 1-bit register for signal .
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Found 1-bit register for signal .
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Found 16-bit register for signal .
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Found 2-bit register for signal .
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Found 16-bit register for signal .
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Found 8-bit register for signal .
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Found 8-bit register for signal .
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Found 3-bit register for signal .
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Found 64-bit register for signal .
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Found 1-bit register for signal .
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Found 16-bit register for signal .
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Found 6-bit register for signal .
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Found 16-bit register for signal .
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Found 8-bit register for signal .
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Found 8-bit register for signal .
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Found 1-bit register for signal .
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Summary:
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inferred 1 Finite State Machine(s).
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inferred 1 ROM(s).
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inferred 228 D-type flip-flop(s).
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inferred 34 Adder/Subtractor(s).
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inferred 2 Comparator(s).
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inferred 52 Multiplexer(s).
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inferred 8 Tristate(s).
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Unit synthesized.
385
386
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Synthesizing Unit .
388
Related source file is "testbench.v".
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WARNING:Xst:646 - Signal is assigned but never used.
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Found 8-bit tristate buffer for signal .
391
Summary:
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inferred 8 Tristate(s).
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Unit synthesized.
394
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INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
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=========================================================================
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HDL Synthesis Report
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Macro Statistics
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# RAMs : 1
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1024x8-bit single-port block RAM : 1
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# ROMs : 2
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4x1-bit ROM : 1
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512x8-bit ROM : 1
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# Adders/Subtractors : 42
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16-bit adder : 5
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16-bit addsub : 1
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16-bit subtractor : 1
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17-bit adder : 8
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32-bit adder : 6
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32-bit subtractor : 3
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4-bit adder carry out : 2
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5-bit adder : 1
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6-bit adder : 1
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6-bit subtractor : 2
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8-bit adder : 1
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8-bit adder carry out : 3
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8-bit addsub : 3
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9-bit adder : 3
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9-bit subtractor : 2
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# Registers : 54
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1-bit register : 23
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16-bit register : 5
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2-bit register : 1
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3-bit register : 2
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4-bit register : 1
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6-bit register : 1
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8-bit register : 21
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# Latches : 12
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6-bit latch : 4
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8-bit latch : 8
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# Comparators : 7
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4-bit comparator equal : 1
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4-bit comparator greater : 2
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6-bit comparator equal : 4
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# Multiplexers : 20
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1-bit 4-to-1 multiplexer : 8
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1-bit 8-to-1 multiplexer : 2
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3-bit 4-to-1 multiplexer : 4
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8-bit 4-to-1 multiplexer : 3
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8-bit 8-to-1 multiplexer : 3
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# Tristates : 10
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8-bit tristate buffer : 10
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# Xors : 2
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1-bit xor8 : 1
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8-bit xor2 : 1
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=========================================================================
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=========================================================================
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* Advanced HDL Synthesis *
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=========================================================================
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Analyzing FSM for best encoding.
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Optimizing FSM on signal with speed1 encoding.
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-------------------------------------------
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State | Encoding
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-------------------------------------------
460
00001 | 10000000000000000000000000000000
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00010 | 01000000000000000000000000000000
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00011 | 00000010000000000000000000000000
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00100 | 00000001001000000000000000000000
464
00101 | 00010000001000000000000000000000
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00110 | 00000000001001000000000000000000
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00111 | 00000000001000100000000000000000
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01000 | 00000000001000010000000000000000
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01001 | 00000000001000001000000000000000
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01010 | 00000000000000000000000010000001
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01011 | 00000000001000000000010000000000
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01100 | 00001000000000000000000000000000
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01101 | 00000000100000000000000000000000
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01110 | 00000000010000000000000000000000
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01111 | 00000000000100000000000000000001
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10000 | 00000100000000000000000000000000
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10001 | 00000000000000000000000000100000
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10010 | 00000000001000000100000000000000
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10011 | 00000000000000000000000100000000
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10100 | 00000000001000000000000000010000
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10101 | 00000000000000000000000001000000
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10110 | 00000000000000000000000000001000
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10111 | 00000000000000000000000000000100
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11000 | 00000000001000000000000000000010
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11001 | 00000000000010000000000000000001
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11010 | 00000000000000000010000000000001
486
11011 | 00000000000000000000100000000001
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11100 | 00000000000000000000001000000001
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11101 | 00000000000000000001000000000000
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11110 | 00100000001000000000000000000000
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-------------------------------------------
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Analyzing FSM for best encoding.
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Optimizing FSM on signal with gray encoding.
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-------------------
494
State | Encoding
495
-------------------
496
0000 | 00
497
0001 | 01
498
0010 | 11
499
-------------------
500
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Loading device for application Rf_Device from file '3s200.nph' in environment C:\Xilinx.
501
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INFO:Xst:1651 - Address input of ROM is tied to register .
502
INFO:Xst:1650 - The register is removed and the ROM is implemented as read-only block RAM.
503
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WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block .
504
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .
505
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .
506
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block .
507
508
=========================================================================
509
Advanced HDL Synthesis Report
510
511
Macro Statistics
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# FSMs : 2
513
# RAMs : 2
514
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1024x8-bit single-port block RAM : 1
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512x8-bit single-port block RAM : 1
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# ROMs : 1
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4x1-bit ROM : 1
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# Adders/Subtractors : 42
519
16-bit adder : 5
520
16-bit addsub : 1
521
16-bit subtractor : 1
522
17-bit adder : 8
523
32-bit adder : 6
524
32-bit subtractor : 3
525
4-bit adder carry out : 2
526
5-bit adder : 1
527
6-bit adder : 1
528
6-bit subtractor : 2
529
8-bit adder : 1
530
8-bit adder carry out : 3
531
8-bit addsub : 3
532
9-bit adder : 3
533
9-bit subtractor : 2
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# Registers : 319
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Flip-Flops : 319
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# Latches : 12
537
6-bit latch : 4
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8-bit latch : 8
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# Comparators : 7
540
4-bit comparator equal : 1
541
4-bit comparator greater : 2
542
6-bit comparator equal : 4
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# Multiplexers : 20
544
1-bit 4-to-1 multiplexer : 8
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1-bit 8-to-1 multiplexer : 2
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3-bit 4-to-1 multiplexer : 4
547
8-bit 4-to-1 multiplexer : 3
548
8-bit 8-to-1 multiplexer : 3
549
# Xors : 2
550
1-bit xor8 : 1
551
8-bit xor2 : 1
552
553
=========================================================================
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555
=========================================================================
556
* Low Level Synthesis *
557
=========================================================================
558
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WARNING:Xst:2040 - Unit testbench: 8 multi-source signals are replaced by logic (pull-up yes): N185, N187, N189, N1911, N193, N195, N197, N199.
559
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560
Optimizing unit ...
561
562
Optimizing unit ...
563
564
Mapping all equations...
565
Building and optimizing final netlist ...
566
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Found area constraint ratio of 100 (+ 5) on block testbench, actual ratio is 69.
567
FlipFlop cpu/addr_0 has been replicated 2 time(s)
568
FlipFlop cpu/addr_1 has been replicated 2 time(s)
569
FlipFlop cpu/addr_2 has been replicated 2 time(s)
570
FlipFlop cpu/addr_3 has been replicated 1 time(s)
571
FlipFlop cpu/readio has been replicated 1 time(s)
572
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573
Final Macro Processing ...
574
575
=========================================================================
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Final Register Report
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578
Macro Statistics
579
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# Registers : 326
580
Flip-Flops : 326
581
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582
=========================================================================
583
584
=========================================================================
585
* Partition Report *
586
=========================================================================
587
588
Partition Implementation Status
589
-------------------------------
590
591
No Partitions were found in this design.
592
593
-------------------------------
594
595
=========================================================================
596
* Final Report *
597
=========================================================================
598
Final Results
599
RTL Top Level Output File Name : testbench.ngr
600
Top Level Output File Name : testbench
601
Output Format : NGC
602
Optimization Goal : Speed
603
Keep Hierarchy : NO
604
605
Design Statistics
606
# IOs : 33
607
608
Cell Usage :
609
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# BELS : 3000
610
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# GND : 1
611
9 samiam9512
# INV : 83
612
2 samiam9512
# LUT1 : 139
613
9 samiam9512
# LUT2 : 152
614
# LUT2_D : 1
615
# LUT2_L : 13
616
# LUT3 : 408
617
# LUT3_D : 9
618
# LUT3_L : 11
619
# LUT4 : 1358
620
# LUT4_D : 13
621
# LUT4_L : 66
622
2 samiam9512
# MULT_AND : 28
623
# MUXCY : 279
624
9 samiam9512
# MUXF5 : 176
625
2 samiam9512
# MUXF6 : 24
626
# VCC : 1
627
# XORCY : 238
628
9 samiam9512
# FlipFlops/Latches : 403
629
# FDE : 214
630
# FDE_1 : 8
631
# FDR : 22
632
2 samiam9512
# FDRE : 5
633
9 samiam9512
# FDRE_1 : 42
634
# FDRS : 29
635
# FDRSE : 3
636
# FDS : 2
637
# FDSE : 1
638
# LDCE : 53
639
2 samiam9512
# LDE_1 : 24
640
9 samiam9512
# RAMS : 2
641
# RAMB16_S9 : 2
642
2 samiam9512
# Clock Buffers : 2
643
# BUFGP : 2
644
# IO Buffers : 31
645
9 samiam9512
# IBUF : 1
646
2 samiam9512
# IOBUF : 8
647
9 samiam9512
# OBUF : 22
648
2 samiam9512
=========================================================================
649
650
Device utilization summary:
651
---------------------------
652
653
Selected Device : 3s200pq208-5
654
655
9 samiam9512
Number of Slices: 1196 out of 1920 62%
656
Number of Slice Flip Flops: 403 out of 3840 10%
657
Number of 4 input LUTs: 2253 out of 3840 58%
658
2 samiam9512
Number of IOs: 33
659
Number of bonded IOBs: 33 out of 141 23%
660
9 samiam9512
Number of BRAMs: 2 out of 12 16%
661
2 samiam9512
Number of GCLKs: 2 out of 8 25%
662
663
664
=========================================================================
665
TIMING REPORT
666
667
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
668
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
669
GENERATED AFTER PLACE-and-ROUTE.
670
671
Clock Information:
672
------------------
673
-----------------------------------------------------+--------------------------------+-------+
674
Clock Signal | Clock buffer(FF name) | Load |
675
-----------------------------------------------------+--------------------------------+-------+
676
9 samiam9512
clock | BUFGP | 326 |
677
2 samiam9512
reset | BUFGP | 24 |
678
9 samiam9512
select1/selectd/_and0000(select1/selectd/_and00001:O)| NONE(*)(select1/selectd/mask_5)| 11 |
679
select1/selectc/_and0000(select1/selectc/_and00001:O)| NONE(*)(select1/selectc/comp_0)| 14 |
680
2 samiam9512
select1/selectb/_and0000(select1/selectb/_and00001:O)| NONE(*)(select1/selectb/mask_2)| 14 |
681
9 samiam9512
select1/selecta/_and0000(select1/selecta/_and00001:O)| NONE(*)(select1/selecta/comp_4)| 14 |
682
2 samiam9512
-----------------------------------------------------+--------------------------------+-------+
683
(*) These 4 clock signal(s) are generated by combinatorial logic,
684
and XST is not able to identify which are the primary clock signals.
685
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
686
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
687
688
Asynchronous Control Signals Information:
689
----------------------------------------
690
-----------------------------------+------------------------+-------+
691
Control Signal | Buffer(FF name) | Load |
692
-----------------------------------+------------------------+-------+
693
9 samiam9512
reset | BUFGP | 53 |
694
2 samiam9512
-----------------------------------+------------------------+-------+
695
696
Timing Summary:
697
---------------
698
Speed Grade: -5
699
700
9 samiam9512
Minimum period: 18.139ns (Maximum Frequency: 55.130MHz)
701
Minimum input arrival time before clock: 15.913ns
702
Maximum output required time after clock: 18.039ns
703
2 samiam9512
Maximum combinational path delay: No path found
704
705
Timing Detail:
706
--------------
707
All values displayed in nanoseconds (ns)
708
709
=========================================================================
710
Timing constraint: Default period analysis for Clock 'clock'
711
9 samiam9512
Clock period: 18.139ns (frequency: 55.130MHz)
712
Total number of paths / destination ports: 22435 / 411
713
2 samiam9512
-------------------------------------------------------------------------
714
9 samiam9512
Delay: 9.069ns (Levels of Logic = 6)
715
Source: cpu/addr_10 (FF)
716
Destination: intc/active_7 (FF)
717
2 samiam9512
Source Clock: clock rising
718
9 samiam9512
Destination Clock: clock falling
719
2 samiam9512
720
9 samiam9512
Data Path: cpu/addr_10 to intc/active_7
721
2 samiam9512
Gate Net
722
Cell:in->out fanout Delay Delay Logical Name (Net Name)
723
---------------------------------------- ------------
724
9 samiam9512
FDE:C->Q 5 0.626 0.842 cpu/addr_10 (cpu/addr_10)
725
LUT4:I2->O 1 0.479 0.000 select1/selectc/selectout1511 (N12307)
726
MUXF5:I1->O 2 0.314 1.040 select1/selectc/selectout151_f5 (select1/selectc/selectout_map4308)
727
LUT4_D:I0->O 1 0.479 0.704 select1/selectc/selectout169_1 (select1/selectc/selectout169)
728
LUT4:I3->O 9 0.479 1.014 intc/_and00011 (intc/_and0001)
729
LUT4_D:I2->O 7 0.479 0.929 intc/_not00162 (N202)
730
LUT4:I3->O 1 0.479 0.681 intc/_not0016 (intc/_not0016)
731
FDRE_1:CE 0.524 intc/active_7
732
2 samiam9512
----------------------------------------
733
9 samiam9512
Total 9.069ns (3.859ns logic, 5.211ns route)
734
(42.5% logic, 57.5% route)
735
2 samiam9512
736
=========================================================================
737
Timing constraint: Default OFFSET IN BEFORE for Clock 'clock'
738
9 samiam9512
Total number of paths / destination ports: 13926 / 607
739
2 samiam9512
-------------------------------------------------------------------------
740
9 samiam9512
Offset: 15.913ns (Levels of Logic = 11)
741
2 samiam9512
Source: data<4> (PAD)
742
9 samiam9512
Destination: cpu/regfil_5_7 (FF)
743
2 samiam9512
Destination Clock: clock rising
744
745
9 samiam9512
Data Path: data<4> to cpu/regfil_5_7
746
2 samiam9512
Gate Net
747
Cell:in->out fanout Delay Delay Logical Name (Net Name)
748
---------------------------------------- ------------
749
9 samiam9512
IOBUF:IO->O 164 0.715 2.513 data_4_IOBUF (N11201)
750
LUT2:I0->O 23 0.479 1.469 cpu/state_FFd1-In3282 (cpu/_cmp_eq0211)
751
LUT4:I3->O 11 0.479 0.995 cpu/_cmp_eq00651 (cpu/_cmp_eq0065)
752
LUT4:I3->O 8 0.479 0.980 cpu/_mux0012<0>311 (N447)
753
LUT4:I2->O 1 0.479 0.851 cpu/_mux0013<7>1117_SW0 (N12113)
754
LUT3_D:I1->O 2 0.479 1.040 cpu/_mux0013<7>1117 (N411)
755
LUT4_D:I0->LO 1 0.479 0.159 cpu/_mux0013<7>1281 (N12420)
756
LUT4:I2->O 8 0.479 1.216 cpu/_mux0013<7>120 (N410)
757
LUT3:I0->O 1 0.479 0.851 cpu/_mux0013<7>8_SW0 (N11497)
758
LUT4_L:I1->LO 1 0.479 0.159 cpu/_mux0013<7>22 (cpu/_mux0013<7>_map4164)
759
LUT4:I2->O 1 0.479 0.000 cpu/_mux0013<7>172 (cpu/_mux0013<7>)
760
FDE:D 0.176 cpu/regfil_5_7
761
2 samiam9512
----------------------------------------
762
9 samiam9512
Total 15.913ns (5.681ns logic, 10.232ns route)
763
(35.7% logic, 64.3% route)
764
2 samiam9512
765
=========================================================================
766
Timing constraint: Default OFFSET IN BEFORE for Clock 'select1/selectd/_and0000'
767
Total number of paths / destination ports: 11 / 11
768
-------------------------------------------------------------------------
769
9 samiam9512
Offset: 3.372ns (Levels of Logic = 1)
770
2 samiam9512
Source: data<3> (PAD)
771
Destination: select1/selectd/mask_3 (LATCH)
772
Destination Clock: select1/selectd/_and0000 falling
773
774
Data Path: data<3> to select1/selectd/mask_3
775
Gate Net
776
Cell:in->out fanout Delay Delay Logical Name (Net Name)
777
---------------------------------------- ------------
778
9 samiam9512
IOBUF:IO->O 218 0.715 2.481 data_3_IOBUF (N11202)
779
LDCE:D 0.176 select1/selectd/comp_1
780
2 samiam9512
----------------------------------------
781
9 samiam9512
Total 3.372ns (0.891ns logic, 2.481ns route)
782
(26.4% logic, 73.6% route)
783
2 samiam9512
784
=========================================================================
785
Timing constraint: Default OFFSET IN BEFORE for Clock 'select1/selectc/_and0000'
786
9 samiam9512
Total number of paths / destination ports: 14 / 14
787
2 samiam9512
-------------------------------------------------------------------------
788
9 samiam9512
Offset: 3.372ns (Levels of Logic = 1)
789
2 samiam9512
Source: data<3> (PAD)
790
Destination: select1/selectc/mask_3 (LATCH)
791
Destination Clock: select1/selectc/_and0000 falling
792
793
Data Path: data<3> to select1/selectc/mask_3
794
Gate Net
795
Cell:in->out fanout Delay Delay Logical Name (Net Name)
796
---------------------------------------- ------------
797
9 samiam9512
IOBUF:IO->O 218 0.715 2.481 data_3_IOBUF (N11202)
798
2 samiam9512
LDCE:D 0.176 select1/selectc/mask_3
799
----------------------------------------
800
9 samiam9512
Total 3.372ns (0.891ns logic, 2.481ns route)
801
(26.4% logic, 73.6% route)
802
2 samiam9512
803
=========================================================================
804
Timing constraint: Default OFFSET IN BEFORE for Clock 'select1/selectb/_and0000'
805
Total number of paths / destination ports: 14 / 14
806
-------------------------------------------------------------------------
807
9 samiam9512
Offset: 3.372ns (Levels of Logic = 1)
808
2 samiam9512
Source: data<3> (PAD)
809
Destination: select1/selectb/mask_3 (LATCH)
810
Destination Clock: select1/selectb/_and0000 falling
811
812
Data Path: data<3> to select1/selectb/mask_3
813
Gate Net
814
Cell:in->out fanout Delay Delay Logical Name (Net Name)
815
---------------------------------------- ------------
816
9 samiam9512
IOBUF:IO->O 218 0.715 2.481 data_3_IOBUF (N11202)
817
LDCE:D 0.176 select1/selectb/comp_1
818
2 samiam9512
----------------------------------------
819
9 samiam9512
Total 3.372ns (0.891ns logic, 2.481ns route)
820
(26.4% logic, 73.6% route)
821
2 samiam9512
822
=========================================================================
823
Timing constraint: Default OFFSET IN BEFORE for Clock 'select1/selecta/_and0000'
824
Total number of paths / destination ports: 14 / 14
825
-------------------------------------------------------------------------
826
9 samiam9512
Offset: 3.372ns (Levels of Logic = 1)
827
2 samiam9512
Source: data<3> (PAD)
828
Destination: select1/selecta/mask_3 (LATCH)
829
Destination Clock: select1/selecta/_and0000 falling
830
831
Data Path: data<3> to select1/selecta/mask_3
832
Gate Net
833
Cell:in->out fanout Delay Delay Logical Name (Net Name)
834
---------------------------------------- ------------
835
9 samiam9512
IOBUF:IO->O 218 0.715 2.481 data_3_IOBUF (N11202)
836
2 samiam9512
LDCE:D 0.176 select1/selecta/mask_3
837
----------------------------------------
838
9 samiam9512
Total 3.372ns (0.891ns logic, 2.481ns route)
839
(26.4% logic, 73.6% route)
840
2 samiam9512
841
=========================================================================
842
Timing constraint: Default OFFSET OUT AFTER for Clock 'clock'
843
9 samiam9512
Total number of paths / destination ports: 1340 / 30
844
2 samiam9512
-------------------------------------------------------------------------
845
9 samiam9512
Offset: 17.890ns (Levels of Logic = 10)
846
Source: cpu/addr_10 (FF)
847
2 samiam9512
Destination: data<7> (PAD)
848
Source Clock: clock rising
849
850
9 samiam9512
Data Path: cpu/addr_10 to data<7>
851
2 samiam9512
Gate Net
852
Cell:in->out fanout Delay Delay Logical Name (Net Name)
853
---------------------------------------- ------------
854
9 samiam9512
FDE:C->Q 5 0.626 0.842 cpu/addr_10 (cpu/addr_10)
855
LUT4:I2->O 1 0.479 0.000 select1/selectc/selectout1511 (N12307)
856
MUXF5:I1->O 2 0.314 1.040 select1/selectc/selectout151_f5 (select1/selectc/selectout_map4308)
857
LUT4_D:I0->O 1 0.479 0.704 select1/selectc/selectout169_1 (select1/selectc/selectout169)
858
LUT4:I3->O 9 0.479 1.250 intc/_and00011 (intc/_and0001)
859
LUT2:I0->O 8 0.479 1.216 intc/_or0000_inv1 (intc/_or0000_inv)
860
LUT4:I0->O 1 0.479 0.704 N185LogicTrst1_SW0 (N4909)
861
LUT4:I3->O 14 0.479 1.032 N185LogicTrst1 (N1913)
862
LUT4:I3->O 1 0.479 0.740 N185LogicTrst136_SW1 (N12137)
863
LUT4:I2->O 1 0.479 0.681 N185LogicTrst136 (data_7_IOBUF)
864
IOBUF:I->IO 4.909 data_7_IOBUF (data<7>)
865
2 samiam9512
----------------------------------------
866
9 samiam9512
Total 17.890ns (9.681ns logic, 8.209ns route)
867
(54.1% logic, 45.9% route)
868
2 samiam9512
869
=========================================================================
870
9 samiam9512
Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selectc/_and0000'
871
Total number of paths / destination ports: 552 / 8
872
2 samiam9512
-------------------------------------------------------------------------
873
9 samiam9512
Offset: 18.039ns (Levels of Logic = 10)
874
Source: select1/selectc/comp_0 (LATCH)
875
2 samiam9512
Destination: data<7> (PAD)
876
9 samiam9512
Source Clock: select1/selectc/_and0000 falling
877
2 samiam9512
878
9 samiam9512
Data Path: select1/selectc/comp_0 to data<7>
879
2 samiam9512
Gate Net
880
Cell:in->out fanout Delay Delay Logical Name (Net Name)
881
---------------------------------------- ------------
882
9 samiam9512
LDCE:G->Q 3 0.551 1.066 select1/selectc/comp_0 (select1/selectc/comp_0)
883
LUT4:I0->O 1 0.479 0.000 select1/selectc/selectout1511 (N12307)
884
MUXF5:I1->O 2 0.314 1.040 select1/selectc/selectout151_f5 (select1/selectc/selectout_map4308)
885
LUT4_D:I0->O 1 0.479 0.704 select1/selectc/selectout169_1 (select1/selectc/selectout169)
886
LUT4:I3->O 9 0.479 1.250 intc/_and00011 (intc/_and0001)
887
LUT2:I0->O 8 0.479 1.216 intc/_or0000_inv1 (intc/_or0000_inv)
888
LUT4:I0->O 1 0.479 0.704 N185LogicTrst1_SW0 (N4909)
889
LUT4:I3->O 14 0.479 1.032 N185LogicTrst1 (N1913)
890
LUT4:I3->O 1 0.479 0.740 N185LogicTrst136_SW1 (N12137)
891
LUT4:I2->O 1 0.479 0.681 N185LogicTrst136 (data_7_IOBUF)
892
IOBUF:I->IO 4.909 data_7_IOBUF (data<7>)
893
2 samiam9512
----------------------------------------
894
9 samiam9512
Total 18.039ns (9.606ns logic, 8.433ns route)
895
(53.3% logic, 46.7% route)
896
2 samiam9512
897
=========================================================================
898
Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selectb/_and0000'
899
9 samiam9512
Total number of paths / destination ports: 648 / 8
900
2 samiam9512
-------------------------------------------------------------------------
901
9 samiam9512
Offset: 15.904ns (Levels of Logic = 9)
902
Source: select1/selectb/comp_2 (LATCH)
903
2 samiam9512
Destination: data<7> (PAD)
904
Source Clock: select1/selectb/_and0000 falling
905
906
9 samiam9512
Data Path: select1/selectb/comp_2 to data<7>
907
2 samiam9512
Gate Net
908
Cell:in->out fanout Delay Delay Logical Name (Net Name)
909
---------------------------------------- ------------
910
9 samiam9512
LDCE:G->Q 3 0.551 1.066 select1/selectb/comp_2 (select1/selectb/comp_2)
911
LUT4:I0->O 1 0.479 0.000 select1/select2791 (N12279)
912
MUXF5:I1->O 1 0.314 0.976 select1/select279_f5 (select1/select2_map1830)
913
LUT4:I0->O 1 0.479 0.740 select1/select2169 (select1/select2_map1857)
914
LUT4:I2->O 4 0.479 0.838 select1/select2195 (ramsel)
915
LUT4:I2->O 1 0.479 0.704 N185LogicTrst1_SW0 (N4909)
916
LUT4:I3->O 14 0.479 1.032 N185LogicTrst1 (N1913)
917
LUT4:I3->O 1 0.479 0.740 N185LogicTrst136_SW1 (N12137)
918
LUT4:I2->O 1 0.479 0.681 N185LogicTrst136 (data_7_IOBUF)
919
IOBUF:I->IO 4.909 data_7_IOBUF (data<7>)
920
2 samiam9512
----------------------------------------
921
9 samiam9512
Total 15.904ns (9.127ns logic, 6.777ns route)
922
2 samiam9512
(57.4% logic, 42.6% route)
923
924
=========================================================================
925
Timing constraint: Default OFFSET OUT AFTER for Clock 'reset'
926
9 samiam9512
Total number of paths / destination ports: 24 / 6
927
2 samiam9512
-------------------------------------------------------------------------
928
9 samiam9512
Offset: 13.765ns (Levels of Logic = 7)
929
Source: select1/selectd/datai_7 (LATCH)
930
Destination: data<7> (PAD)
931
2 samiam9512
Source Clock: reset rising
932
933
9 samiam9512
Data Path: select1/selectd/datai_7 to data<7>
934
2 samiam9512
Gate Net
935
Cell:in->out fanout Delay Delay Logical Name (Net Name)
936
---------------------------------------- ------------
937
9 samiam9512
LDE_1:G->Q 1 0.551 0.704 select1/selectd/datai_7 (select1/selectd/datai_7)
938
LUT4:I3->O 1 0.479 0.851 N185LogicTrst29_SW0 (N11753)
939
LUT4:I1->O 1 0.479 0.740 N185LogicTrst29 (N185LogicTrst_map3906)
940
LUT4:I2->O 1 0.479 0.976 N185LogicTrst60 (N185LogicTrst_map3910)
941
LUT4:I0->O 1 0.479 0.740 N185LogicTrst93 (N185LogicTrst_map3916)
942
LUT4:I2->O 1 0.479 0.740 N185LogicTrst136_SW1 (N12137)
943
LUT4:I2->O 1 0.479 0.681 N185LogicTrst136 (data_7_IOBUF)
944
IOBUF:I->IO 4.909 data_7_IOBUF (data<7>)
945
2 samiam9512
----------------------------------------
946
9 samiam9512
Total 13.765ns (8.334ns logic, 5.431ns route)
947
(60.5% logic, 39.5% route)
948
2 samiam9512
949
=========================================================================
950
9 samiam9512
Timing constraint: Default OFFSET OUT AFTER for Clock 'select1/selecta/_and0000'
951
Total number of paths / destination ports: 840 / 8
952
-------------------------------------------------------------------------
953
Offset: 16.261ns (Levels of Logic = 9)
954
Source: select1/selecta/mask_1 (LATCH)
955
Destination: data<7> (PAD)
956
Source Clock: select1/selecta/_and0000 falling
957
958
Data Path: select1/selecta/mask_1 to data<7>
959
Gate Net
960
Cell:in->out fanout Delay Delay Logical Name (Net Name)
961
---------------------------------------- ------------
962
LDCE:G->Q 6 0.551 1.148 select1/selecta/mask_1 (select1/selecta/mask_1)
963
LUT4:I0->O 1 0.479 0.000 _and0000_inv181 (N12287)
964
MUXF5:I1->O 1 0.314 0.976 _and0000_inv18_f5 (_and0000_inv_map1867)
965
LUT4:I0->O 1 0.479 0.976 _and0000_inv108 (_and0000_inv_map1894)
966
LUT4:I0->O 10 0.479 1.023 _and0000_inv211 (_and0000_inv)
967
LUT3:I2->O 1 0.479 0.851 N185LogicTrst93_SW0 (N11757)
968
LUT4:I1->O 1 0.479 0.740 N185LogicTrst93 (N185LogicTrst_map3916)
969
LUT4:I2->O 1 0.479 0.740 N185LogicTrst136_SW1 (N12137)
970
LUT4:I2->O 1 0.479 0.681 N185LogicTrst136 (data_7_IOBUF)
971
IOBUF:I->IO 4.909 data_7_IOBUF (data<7>)
972
----------------------------------------
973
Total 16.261ns (9.127ns logic, 7.134ns route)
974
(56.1% logic, 43.9% route)
975
976
=========================================================================
977
CPU : 113.61 / 113.84 s | Elapsed : 114.00 / 114.00 s
978
2 samiam9512
979
-->
980
981
9 samiam9512
Total memory usage is 200528 kilobytes
982
2 samiam9512
983
Number of errors : 0 ( 0 filtered)
984
9 samiam9512
Number of warnings : 12 ( 0 filtered)
985
Number of infos : 5 ( 0 filtered)
986
2 samiam9512
