OpenCores
URL https://opencores.org/ocsvn/cpu8080/cpu8080/trunk

Subversion Repositories cpu8080

[/] [cpu8080/] [trunk/] [project/] [testbench.twr] - Blame information for rev 33

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 11 samiam9512
--------------------------------------------------------------------------------
2
Release 8.2.02i Trace
3
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
4
 
5
C:\Xilinx\bin\nt\trce.exe -ise C:/Xilinx/ISEexamples/cpu8080/cpu8080.ise
6
-intstyle ise -e 3 -l 3 -s 4 -xml testbench testbench.ncd -o testbench.twr
7
testbench.pcf -ucf cpu8080.ucf
8
 
9
Design file:              testbench.ncd
10
Physical constraint file: testbench.pcf
11
Device,speed:             xc3s1000,-4 (PRODUCTION 1.39 2006-07-07)
12
Report level:             error report
13
 
14
Environment Variable      Effect
15
--------------------      ------
16
NONE                      No environment variables were set
17
--------------------------------------------------------------------------------
18
 
19
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
20
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
21
   option. All paths that are not constrained will be reported in the
22
   unconstrained paths section(s) of the report.
23
 
24
 
25
 
26
Data Sheet report:
27
-----------------
28
All values displayed in nanoseconds (ns)
29
 
30
Setup/Hold to clock clock
31
------------+------------+------------+------------------+--------+
32
            |  Setup to  |  Hold to   |                  | Clock  |
33
Source      | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
34
------------+------------+------------+------------------+--------+
35 28 samiam9512
data<0>     |    3.965(R)|   -0.309(R)|clock_BUFGP       |   0.000|
36
            |    3.199(F)|   -0.202(F)|clock_BUFGP       |   0.000|
37
data<1>     |    3.965(R)|   -0.033(R)|clock_BUFGP       |   0.000|
38
            |    3.694(F)|   -0.028(F)|clock_BUFGP       |   0.000|
39
data<2>     |    3.806(R)|   -0.275(R)|clock_BUFGP       |   0.000|
40
            |    3.822(F)|   -0.542(F)|clock_BUFGP       |   0.000|
41
data<3>     |    4.663(R)|   -0.401(R)|clock_BUFGP       |   0.000|
42
            |    4.530(F)|    0.157(F)|clock_BUFGP       |   0.000|
43
data<4>     |    3.888(R)|   -0.848(R)|clock_BUFGP       |   0.000|
44
            |    4.667(F)|   -0.763(F)|clock_BUFGP       |   0.000|
45
data<5>     |    5.123(R)|   -0.710(R)|clock_BUFGP       |   0.000|
46
            |    2.118(F)|    0.337(F)|clock_BUFGP       |   0.000|
47
data<6>     |    4.367(R)|   -0.691(R)|clock_BUFGP       |   0.000|
48
            |    3.737(F)|    0.118(F)|clock_BUFGP       |   0.000|
49
data<7>     |    4.557(R)|    0.085(R)|clock_BUFGP       |   0.000|
50
            |    2.327(F)|    0.669(F)|clock_BUFGP       |   0.000|
51 18 samiam9512
ps2_clk     |    3.956(R)|   -1.538(R)|clock_BUFGP       |   0.000|
52
ps2_data    |    3.986(R)|   -1.572(R)|clock_BUFGP       |   0.000|
53 11 samiam9512
------------+------------+------------+------------------+--------+
54
 
55
Clock clock to Pad
56
------------+------------+------------------+--------+
57
            | clk (edge) |                  | Clock  |
58
Destination |   to PAD   |Internal Clock(s) | Phase  |
59
------------+------------+------------------+--------+
60 28 samiam9512
addr<0>     |   11.887(R)|clock_BUFGP       |   0.000|
61
addr<1>     |   11.680(R)|clock_BUFGP       |   0.000|
62
addr<2>     |   12.448(R)|clock_BUFGP       |   0.000|
63
addr<3>     |   12.087(R)|clock_BUFGP       |   0.000|
64
addr<4>     |   11.631(R)|clock_BUFGP       |   0.000|
65
addr<5>     |   11.367(R)|clock_BUFGP       |   0.000|
66
addr<6>     |   11.240(R)|clock_BUFGP       |   0.000|
67
addr<7>     |   11.104(R)|clock_BUFGP       |   0.000|
68
addr<8>     |   13.222(R)|clock_BUFGP       |   0.000|
69
addr<9>     |   13.102(R)|clock_BUFGP       |   0.000|
70
addr<10>    |   11.433(R)|clock_BUFGP       |   0.000|
71
addr<11>    |   11.752(R)|clock_BUFGP       |   0.000|
72
addr<12>    |   11.557(R)|clock_BUFGP       |   0.000|
73
addr<13>    |   11.823(R)|clock_BUFGP       |   0.000|
74
addr<14>    |   12.086(R)|clock_BUFGP       |   0.000|
75
addr<15>    |   10.479(R)|clock_BUFGP       |   0.000|
76
b<0>        |   11.912(R)|clock_BUFGP       |   0.000|
77
b<1>        |   13.348(R)|clock_BUFGP       |   0.000|
78
b<2>        |   13.713(R)|clock_BUFGP       |   0.000|
79
data<0>     |   21.980(R)|clock_BUFGP       |   0.000|
80
            |   15.405(F)|clock_BUFGP       |   0.000|
81
data<1>     |   21.150(R)|clock_BUFGP       |   0.000|
82
            |   14.607(F)|clock_BUFGP       |   0.000|
83
data<2>     |   22.440(R)|clock_BUFGP       |   0.000|
84
            |   14.185(F)|clock_BUFGP       |   0.000|
85
data<3>     |   21.021(R)|clock_BUFGP       |   0.000|
86
            |   14.202(F)|clock_BUFGP       |   0.000|
87
data<4>     |   21.733(R)|clock_BUFGP       |   0.000|
88
            |   13.899(F)|clock_BUFGP       |   0.000|
89
data<5>     |   23.040(R)|clock_BUFGP       |   0.000|
90
            |   14.577(F)|clock_BUFGP       |   0.000|
91
data<6>     |   21.711(R)|clock_BUFGP       |   0.000|
92
            |   14.012(F)|clock_BUFGP       |   0.000|
93
data<7>     |   20.985(R)|clock_BUFGP       |   0.000|
94
            |   13.492(F)|clock_BUFGP       |   0.000|
95
diag<0>     |   12.417(R)|clock_BUFGP       |   0.000|
96
diag<1>     |   13.438(R)|clock_BUFGP       |   0.000|
97
diag<2>     |   11.244(R)|clock_BUFGP       |   0.000|
98
diag<5>     |   12.405(R)|clock_BUFGP       |   0.000|
99
diag<6>     |   10.522(R)|clock_BUFGP       |   0.000|
100
diag<7>     |   11.767(R)|clock_BUFGP       |   0.000|
101
g<0>        |   12.302(R)|clock_BUFGP       |   0.000|
102
g<1>        |   13.004(R)|clock_BUFGP       |   0.000|
103
g<2>        |   16.784(R)|clock_BUFGP       |   0.000|
104 11 samiam9512
hsync_n     |    7.261(R)|clock_BUFGP       |   0.000|
105 28 samiam9512
inta        |   15.668(R)|clock_BUFGP       |   0.000|
106
intr        |   15.964(F)|clock_BUFGP       |   0.000|
107
r<0>        |   12.282(R)|clock_BUFGP       |   0.000|
108
r<1>        |   13.004(R)|clock_BUFGP       |   0.000|
109
r<2>        |   16.890(R)|clock_BUFGP       |   0.000|
110
readio      |   11.788(R)|clock_BUFGP       |   0.000|
111
readmem     |   11.248(R)|clock_BUFGP       |   0.000|
112
vsync_n     |   12.408(R)|clock_BUFGP       |   0.000|
113
writeio     |   12.165(R)|clock_BUFGP       |   0.000|
114
writemem    |    9.619(R)|clock_BUFGP       |   0.000|
115 11 samiam9512
------------+------------+------------------+--------+
116
 
117
Clock reset_n to Pad
118
------------+------------+------------------+--------+
119
            | clk (edge) |                  | Clock  |
120
Destination |   to PAD   |Internal Clock(s) | Phase  |
121
------------+------------+------------------+--------+
122 28 samiam9512
data<0>     |   18.520(F)|reset_n_BUFGP     |   0.000|
123
data<1>     |   17.029(F)|reset_n_BUFGP     |   0.000|
124
data<2>     |   19.000(F)|reset_n_BUFGP     |   0.000|
125
data<3>     |   18.089(F)|reset_n_BUFGP     |   0.000|
126
data<4>     |   16.333(F)|reset_n_BUFGP     |   0.000|
127
data<5>     |   17.180(F)|reset_n_BUFGP     |   0.000|
128
data<6>     |   15.601(F)|reset_n_BUFGP     |   0.000|
129
data<7>     |   15.365(F)|reset_n_BUFGP     |   0.000|
130 11 samiam9512
------------+------------+------------------+--------+
131
 
132
Clock to Setup on destination clock clock
133
---------------+---------+---------+---------+---------+
134
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
135
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
136
---------------+---------+---------+---------+---------+
137 28 samiam9512
clock          |   19.080|    8.157|    9.474|    9.681|
138
reset_n        |   14.538|   14.538|    8.148|    8.148|
139 11 samiam9512
---------------+---------+---------+---------+---------+
140
 
141 18 samiam9512
Clock to Setup on destination clock reset_n
142
---------------+---------+---------+---------+---------+
143
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
144
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
145
---------------+---------+---------+---------+---------+
146 28 samiam9512
clock          |         |         |    9.853|         |
147 18 samiam9512
---------------+---------+---------+---------+---------+
148 11 samiam9512
 
149 18 samiam9512
Pad to Pad
150
---------------+---------------+---------+
151
Source Pad     |Destination Pad|  Delay  |
152
---------------+---------------+---------+
153 24 samiam9512
ps2_clk        |diag<3>        |    6.287|
154
ps2_data       |diag<4>        |    6.287|
155 18 samiam9512
---------------+---------------+---------+
156
 
157
 
158 28 samiam9512
Analysis completed Sat Nov 18 17:16:24 2006
159 11 samiam9512
--------------------------------------------------------------------------------
160
 
161
Trace Settings:
162
-------------------------
163
Trace Settings
164
 
165 20 samiam9512
Peak Memory Usage: 183 MB
166 11 samiam9512
 
167
 
168
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.