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Release 8.2.02i Map I.33
Xilinx Mapping Report File for Design 'testbench'
 
Design Information
------------------
Command Line   : C:\Xilinx\bin\nt\map.exe -ise
C:/Xilinx/ISEexamples/cpu8080/cpu8080.ise -intstyle ise -p xc3s1000-ft256-4 -cm
area -pr b -k 4 -c 100 -o testbench_map.ncd testbench.ngd testbench.pcf
Target Device  : xc3s1000
Target Package : ft256
Target Speed   : -4
Mapper Version : spartan3 -- $Revision: 1.1.1.1 $
Mapped Date    : Wed Nov 01 08:45:26 2006
 
Design Summary
--------------
Number of errors:      0
Number of warnings:    9
Logic Utilization:
  Total Number Slice Registers:       890 out of  15,360    5%
    Number used as Flip Flops:                   802
    Number used as Latches:                       88
  Number of 4 input LUTs:           3,884 out of  15,360   25%
Logic Distribution:
  Number of occupied Slices:                        3,425 out of   7,680   44%
    Number of Slices containing only related logic:   3,425 out of   3,425  100%
    Number of Slices containing unrelated logic:          0 out of   3,425    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          5,760 out of  15,360   37%
  Number used as logic:              3,884
  Number used as a route-thru:         196
  Number used for Dual Port RAMs:    1,680
    (Two LUTs used per Dual Port RAM)
  Number of bonded IOBs:               44 out of     173   25%
    IOB Flip Flops:                     9
  Number of Block RAMs:                2 out of      24    8%
  Number of MULT18X18s:                1 out of      24    4%
  Number of GCLKs:                     3 out of       8   37%
 
Total equivalent gate count for design:  278,010
Additional JTAG gate count for IOBs:  2,112
Peak Memory Usage:  194 MB
 
NOTES:
 
   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.
 
   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.
 
   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.
 
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
 
Section 1 - Errors
------------------
 
Section 2 - Warnings
--------------------
WARNING:LIT:243 - Logical network adm3a/display/inst_Mram_mem960/SPO has no
   load.
WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 839
   more times for the following (max. 5 shown):
   adm3a/display/inst_Mram_mem1100/SPO,
   adm3a/display/inst_Mram_mem2100/SPO,
   adm3a/display/inst_Mram_mem3100/SPO,
   adm3a/display/inst_Mram_mem4100/SPO,
   adm3a/display/inst_Mram_mem5100/SPO
   To see the details of these warning messages, please use the -detail switch.
WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFGMUX
   symbol "physical_group_clkdiv<3>/clkdiv_3_BUFG" (output signal=clkdiv<3>) has
   a mix of clock and non-clock loads. The non-clock loads are:
   Pin LI of Mcount_clkdiv_xor<3>
WARNING:LIT:175 - Clock buffer is designated to drive clock loads. BUFGMUX
   symbol "physical_group_reset_n_BUFGP/reset_n_BUFGP/BUFG" (output
   signal=reset_n_BUFGP) has a mix of clock and non-clock loads. Some of the
   non-clock loads are (maximum of 5 listed):
   Pin PRE of cpu/ei
   Pin CE of cpu/carry
   Pin CE of cpu/addr_0
   Pin CE of cpu/addr_1
   Pin CE of cpu/addr_2
WARNING:Pack:266 - The function generator adm3a/display/chradr<4>8 failed to
   merge with F5 multiplexer adm3a/display/chradr<5>_f5_35.  There is a conflict
   for the FXMUX.  The design will exhibit suboptimal timing.
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectd/_and0000 is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selecta/_and0000 is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectb/_and0000 is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectc/_and0000 is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
 
Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
   Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
   BUFG symbol "clkdiv_3_BUFG" (output signal=clkdiv<3>),
   BUFGP symbol "clock_BUFGP" (output signal=clock_BUFGP),
   BUFGP symbol "reset_n_BUFGP" (output signal=reset_n_BUFGP)
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs in the
   schematic.
 
Section 4 - Removed Logic Summary
---------------------------------
   1 block(s) removed
   3 block(s) optimized away
   1 signal(s) removed
 
Section 5 - Removed Logic
-------------------------
 
The trimmed logic reported below is either:
   1. part of a cycle
   2. part of disabled logic
   3. a side-effect of other trimmed logic
 
The signal "cpu/regfil_5_1_rt1" is unused and has been removed.
 Unused block "cpu/regfil_5_1_rt1" (ROM) removed.
 
Optimized Block(s):
TYPE            BLOCK
GND             XST_GND
VCC             XST_VCC
MUXCY           cpu/Madd__AUX_12_Madd_cy<2>
 
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
 
Section 6 - IOB Properties
--------------------------
 
+------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   |
|                                    |         |           |             | Strength | Rate |          |          | Delay |
+------------------------------------------------------------------------------------------------------------------------+
| addr<0>                            | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| addr<1>                            | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| addr<2>                            | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| addr<3>                            | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| addr<4>                            | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| addr<5>                            | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| addr<6>                            | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| addr<7>                            | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| addr<8>                            | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| addr<9>                            | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| addr<10>                           | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| addr<11>                           | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| addr<12>                           | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| addr<13>                           | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| addr<14>                           | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| addr<15>                           | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| b<0>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| b<1>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| b<2>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| clock                              | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| data<0>                            | IOB     | BIDIR     | LVCMOS25    | 12       | SLOW | INFF1    |          | IFD   |
| data<1>                            | IOB     | BIDIR     | LVCMOS25    | 12       | SLOW | INFF1    |          | IFD   |
| data<2>                            | IOB     | BIDIR     | LVCMOS25    | 12       | SLOW | INFF1    |          | IFD   |
| data<3>                            | IOB     | BIDIR     | LVCMOS25    | 12       | SLOW | INFF1    |          | IFD   |
| data<4>                            | IOB     | BIDIR     | LVCMOS25    | 12       | SLOW | INFF1    |          | IFD   |
| data<5>                            | IOB     | BIDIR     | LVCMOS25    | 12       | SLOW | INFF1    |          | IFD   |
| data<6>                            | IOB     | BIDIR     | LVCMOS25    | 12       | SLOW | INFF1    |          | IFD   |
| data<7>                            | IOB     | BIDIR     | LVCMOS25    | 12       | SLOW | INFF1    |          | IFD   |
| g<0>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| g<1>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| g<2>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| hsync_n                            | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     |          |       |
| inta                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| intr                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| r<0>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| r<1>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| r<2>                               | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| readio                             | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| readmem                            | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| reset_n                            | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| vsync_n                            | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| waitr                              | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| writeio                            | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| writemem                           | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
+------------------------------------------------------------------------------------------------------------------------+
 
Section 7 - RPMs
----------------
 
Section 8 - Guide Report
------------------------
Guide not run on this design.
 
Section 9 - Area Group and Partition Summary
--------------------------------------------
 
Partition Implementation Status
-------------------------------
 
  No Partitions were found in this design.
 
-------------------------------
 
Area Group Information
----------------------
 
  No area groups were found in this design.
 
----------------------
 
Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.
 
Section 11 - Timing Report
--------------------------
This design was not run using timing mode.
 
Section 12 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings

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Subversion Repositories cpu8080

[/] [cpu8080/] [trunk/] [project/] [testbench_map.mrp] - Blame information for rev 11

Line No.	Rev	Author	Line
1	11	samiam9512	`Release 8.2.02i Map I.33`
2			`Xilinx Mapping Report File for Design 'testbench'`
3
4			`Design Information`
5			`------------------`
6			`Command Line : C:\Xilinx\bin\nt\map.exe -ise`
7			`C:/Xilinx/ISEexamples/cpu8080/cpu8080.ise -intstyle ise -p xc3s1000-ft256-4 -cm`
8			`area -pr b -k 4 -c 100 -o testbench_map.ncd testbench.ngd testbench.pcf`
9			`Target Device : xc3s1000`
10			`Target Package : ft256`
11			`Target Speed : -4`
12			`Mapper Version : spartan3 -- $Revision: 1.1.1.1 $`
13			`Mapped Date : Wed Nov 01 08:45:26 2006`
14
15			`Design Summary`
16			`--------------`
17			`Number of errors: 0`
18			`Number of warnings: 9`
19			`Logic Utilization:`
20			`Total Number Slice Registers: 890 out of 15,360 5%`
21			`Number used as Flip Flops: 802`
22			`Number used as Latches: 88`
23			`Number of 4 input LUTs: 3,884 out of 15,360 25%`
24			`Logic Distribution:`
25			`Number of occupied Slices: 3,425 out of 7,680 44%`
26			`Number of Slices containing only related logic: 3,425 out of 3,425 100%`
27			`Number of Slices containing unrelated logic: 0 out of 3,425 0%`
28			`*See NOTES below for an explanation of the effects of unrelated logic`
29			`Total Number 4 input LUTs: 5,760 out of 15,360 37%`
30			`Number used as logic: 3,884`
31			`Number used as a route-thru: 196`
32			`Number used for Dual Port RAMs: 1,680`
33			`(Two LUTs used per Dual Port RAM)`
34			`Number of bonded IOBs: 44 out of 173 25%`
35			`IOB Flip Flops: 9`
36			`Number of Block RAMs: 2 out of 24 8%`
37			`Number of MULT18X18s: 1 out of 24 4%`
38			`Number of GCLKs: 3 out of 8 37%`
39
40			`Total equivalent gate count for design: 278,010`
41			`Additional JTAG gate count for IOBs: 2,112`
42			`Peak Memory Usage: 194 MB`
43
44			`NOTES:`
45
46			`Related logic is defined as being logic that shares connectivity - e.g. two`
47			`LUTs are "related" if they share common inputs. When assembling slices,`
48			`Map gives priority to combine logic that is related. Doing so results in`
49			`the best timing performance.`
50
51			`Unrelated logic shares no connectivity. Map will only begin packing`
52			`unrelated logic into a slice once 99% of the slices are occupied through`
53			`related logic packing.`
54
55			`Note that once logic distribution reaches the 99% level through related`
56			`logic packing, this does not mean the device is completely utilized.`
57			`Unrelated logic packing will then begin, continuing until all usable LUTs`
58			`and FFs are occupied. Depending on your timing budget, increased levels of`
59			`unrelated logic packing may adversely affect the overall timing performance`
60			`of your design.`
61
62			`Table of Contents`
63			`-----------------`
64			`Section 1 - Errors`
65			`Section 2 - Warnings`
66			`Section 3 - Informational`
67			`Section 4 - Removed Logic Summary`
68			`Section 5 - Removed Logic`
69			`Section 6 - IOB Properties`
70			`Section 7 - RPMs`
71			`Section 8 - Guide Report`
72			`Section 9 - Area Group and Partition Summary`
73			`Section 10 - Modular Design Summary`
74			`Section 11 - Timing Report`
75			`Section 12 - Configuration String Information`
76
77			`Section 1 - Errors`
78			`------------------`
79
80			`Section 2 - Warnings`
81			`--------------------`
82			`WARNING:LIT:243 - Logical network adm3a/display/inst_Mram_mem960/SPO has no`
83			`load.`
84			`WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 839`
85			`more times for the following (max. 5 shown):`
86			`adm3a/display/inst_Mram_mem1100/SPO,`
87			`adm3a/display/inst_Mram_mem2100/SPO,`
88			`adm3a/display/inst_Mram_mem3100/SPO,`
89			`adm3a/display/inst_Mram_mem4100/SPO,`
90			`adm3a/display/inst_Mram_mem5100/SPO`
91			`To see the details of these warning messages, please use the -detail switch.`
92			`WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFGMUX`
93			`symbol "physical_group_clkdiv<3>/clkdiv_3_BUFG" (output signal=clkdiv<3>) has`
94			`a mix of clock and non-clock loads. The non-clock loads are:`
95			`Pin LI of Mcount_clkdiv_xor<3>`
96			`WARNING:LIT:175 - Clock buffer is designated to drive clock loads. BUFGMUX`
97			`symbol "physical_group_reset_n_BUFGP/reset_n_BUFGP/BUFG" (output`
98			`signal=reset_n_BUFGP) has a mix of clock and non-clock loads. Some of the`
99			`non-clock loads are (maximum of 5 listed):`
100			`Pin PRE of cpu/ei`
101			`Pin CE of cpu/carry`
102			`Pin CE of cpu/addr_0`
103			`Pin CE of cpu/addr_1`
104			`Pin CE of cpu/addr_2`
105			`WARNING:Pack:266 - The function generator adm3a/display/chradr<4>8 failed to`
106			`merge with F5 multiplexer adm3a/display/chradr<5>_f5_35. There is a conflict`
107			`for the FXMUX. The design will exhibit suboptimal timing.`
108			`WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectd/_and0000 is`
109			`sourced by a combinatorial pin. This is not good design practice. Use the CE`
110			`pin to control the loading of data into the flip-flop.`
111			`WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selecta/_and0000 is`
112			`sourced by a combinatorial pin. This is not good design practice. Use the CE`
113			`pin to control the loading of data into the flip-flop.`
114			`WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectb/_and0000 is`
115			`sourced by a combinatorial pin. This is not good design practice. Use the CE`
116			`pin to control the loading of data into the flip-flop.`
117			`WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectc/_and0000 is`
118			`sourced by a combinatorial pin. This is not good design practice. Use the CE`
119			`pin to control the loading of data into the flip-flop.`
120
121			`Section 3 - Informational`
122			`-------------------------`
123			`INFO:MapLib:562 - No environment variables are currently set.`
124			`INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to`
125			`Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:`
126			`BUFG symbol "clkdiv_3_BUFG" (output signal=clkdiv<3>),`
127			`BUFGP symbol "clock_BUFGP" (output signal=clock_BUFGP),`
128			`BUFGP symbol "reset_n_BUFGP" (output signal=reset_n_BUFGP)`
129			`INFO:LIT:244 - All of the single ended outputs in this design are using slew`
130			`rate limited output drivers. The delay on speed critical single ended outputs`
131			`can be dramatically reduced by designating them as fast outputs in the`
132			`schematic.`
133
134			`Section 4 - Removed Logic Summary`
135			`---------------------------------`
136			`1 block(s) removed`
137			`3 block(s) optimized away`
138			`1 signal(s) removed`
139
140			`Section 5 - Removed Logic`
141			`-------------------------`
142
143			`The trimmed logic reported below is either:`
144			`1. part of a cycle`
145			`2. part of disabled logic`
146			`3. a side-effect of other trimmed logic`
147
148			`The signal "cpu/regfil_5_1_rt1" is unused and has been removed.`
149			`Unused block "cpu/regfil_5_1_rt1" (ROM) removed.`
150
151			`Optimized Block(s):`
152			`TYPE BLOCK`
153			`GND XST_GND`
154			`VCC XST_VCC`
155			`MUXCY cpu/Madd__AUX_12_Madd_cy<2>`
156
157			`To enable printing of redundant blocks removed and signals merged, set the`
158			`detailed map report option and rerun map.`
159
160			`Section 6 - IOB Properties`
161			`--------------------------`
162
163			`+------------------------------------------------------------------------------------------------------------------------+`
164			`\| IOB Name \| Type \| Direction \| IO Standard \| Drive \| Slew \| Reg (s) \| Resistor \| IOB \|`
165			`\| \| \| \| \| Strength \| Rate \| \| \| Delay \|`
166			`+------------------------------------------------------------------------------------------------------------------------+`
167			`\| addr<0> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
168			`\| addr<1> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
169			`\| addr<2> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
170			`\| addr<3> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
171			`\| addr<4> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
172			`\| addr<5> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
173			`\| addr<6> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
174			`\| addr<7> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
175			`\| addr<8> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
176			`\| addr<9> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
177			`\| addr<10> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
178			`\| addr<11> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
179			`\| addr<12> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
180			`\| addr<13> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
181			`\| addr<14> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
182			`\| addr<15> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
183			`\| b<0> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
184			`\| b<1> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
185			`\| b<2> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
186			`\| clock \| IOB \| INPUT \| LVCMOS25 \| \| \| \| \| \|`
187			`\| data<0> \| IOB \| BIDIR \| LVCMOS25 \| 12 \| SLOW \| INFF1 \| \| IFD \|`
188			`\| data<1> \| IOB \| BIDIR \| LVCMOS25 \| 12 \| SLOW \| INFF1 \| \| IFD \|`
189			`\| data<2> \| IOB \| BIDIR \| LVCMOS25 \| 12 \| SLOW \| INFF1 \| \| IFD \|`
190			`\| data<3> \| IOB \| BIDIR \| LVCMOS25 \| 12 \| SLOW \| INFF1 \| \| IFD \|`
191			`\| data<4> \| IOB \| BIDIR \| LVCMOS25 \| 12 \| SLOW \| INFF1 \| \| IFD \|`
192			`\| data<5> \| IOB \| BIDIR \| LVCMOS25 \| 12 \| SLOW \| INFF1 \| \| IFD \|`
193			`\| data<6> \| IOB \| BIDIR \| LVCMOS25 \| 12 \| SLOW \| INFF1 \| \| IFD \|`
194			`\| data<7> \| IOB \| BIDIR \| LVCMOS25 \| 12 \| SLOW \| INFF1 \| \| IFD \|`
195			`\| g<0> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
196			`\| g<1> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
197			`\| g<2> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
198			`\| hsync_n \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| OFF1 \| \| \|`
199			`\| inta \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
200			`\| intr \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
201			`\| r<0> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
202			`\| r<1> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
203			`\| r<2> \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
204			`\| readio \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
205			`\| readmem \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
206			`\| reset_n \| IOB \| INPUT \| LVCMOS25 \| \| \| \| \| \|`
207			`\| vsync_n \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
208			`\| waitr \| IOB \| INPUT \| LVCMOS25 \| \| \| \| \| \|`
209			`\| writeio \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
210			`\| writemem \| IOB \| OUTPUT \| LVCMOS25 \| 12 \| SLOW \| \| \| \|`
211			`+------------------------------------------------------------------------------------------------------------------------+`
212
213			`Section 7 - RPMs`
214			`----------------`
215
216			`Section 8 - Guide Report`
217			`------------------------`
218			`Guide not run on this design.`
219
220			`Section 9 - Area Group and Partition Summary`
221			`--------------------------------------------`
222
223			`Partition Implementation Status`
224			`-------------------------------`
225
226			`No Partitions were found in this design.`
227
228			`-------------------------------`
229
230			`Area Group Information`
231			`----------------------`
232
233			`No area groups were found in this design.`
234
235			`----------------------`
236
237			`Section 10 - Modular Design Summary`
238			`-----------------------------------`
239			`Modular Design not used for this design.`
240
241			`Section 11 - Timing Report`
242			`--------------------------`
243			`This design was not run using timing mode.`
244
245			`Section 12 - Configuration String Details`
246			`-----------------------------------------`
247			`Use the "-detail" map option to print out Configuration Strings`