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Release 8.2.02i Map I.33
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Xilinx Mapping Report File for Design 'testbench'
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Design Information
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------------------
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Command Line : C:\Xilinx\bin\nt\map.exe -ise
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C:/Xilinx/ISEexamples/cpu8080/cpu8080.ise -intstyle ise -p xc3s1000-ft256-4 -cm
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area -pr b -k 4 -c 100 -o testbench_map.ncd testbench.ngd testbench.pcf
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Target Device : xc3s1000
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Target Package : ft256
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Target Speed : -4
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Mapper Version : spartan3 -- $Revision: 1.1.1.5 $
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Mapped Date : Sat Nov 18 17:11:52 2006
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Design Summary
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--------------
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Number of errors: 0
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Number of warnings: 13
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Logic Utilization:
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Total Number Slice Registers: 745 out of 15,360 4%
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Number used as Flip Flops: 657
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Number used as Latches: 88
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Number of 4 input LUTs: 4,379 out of 15,360 28%
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Logic Distribution:
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Number of occupied Slices: 3,447 out of 7,680 44%
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Number of Slices containing only related logic: 3,447 out of 3,447 100%
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Number of Slices containing unrelated logic: 0 out of 3,447 0%
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*See NOTES below for an explanation of the effects of unrelated logic
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Total Number 4 input LUTs: 6,300 out of 15,360 41%
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Number used as logic: 4,379
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Number used as a route-thru: 241
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Number used for Dual Port RAMs: 1,680
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(Two LUTs used per Dual Port RAM)
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Number of bonded IOBs: 54 out of 173 31%
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IOB Flip Flops: 11
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Number of Block RAMs: 4 out of 24 16%
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Number of MULT18X18s: 2 out of 24 8%
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Number of GCLKs: 2 out of 8 25%
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Total equivalent gate count for design: 415,388
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Additional JTAG gate count for IOBs: 2,592
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Peak Memory Usage: 199 MB
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NOTES:
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Related logic is defined as being logic that shares connectivity - e.g. two
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LUTs are "related" if they share common inputs. When assembling slices,
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Map gives priority to combine logic that is related. Doing so results in
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the best timing performance.
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Unrelated logic shares no connectivity. Map will only begin packing
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unrelated logic into a slice once 99% of the slices are occupied through
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related logic packing.
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Note that once logic distribution reaches the 99% level through related
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logic packing, this does not mean the device is completely utilized.
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Unrelated logic packing will then begin, continuing until all usable LUTs
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and FFs are occupied. Depending on your timing budget, increased levels of
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unrelated logic packing may adversely affect the overall timing performance
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of your design.
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Table of Contents
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-----------------
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Section 1 - Errors
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Section 2 - Warnings
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Section 3 - Informational
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Section 4 - Removed Logic Summary
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Section 5 - Removed Logic
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Section 6 - IOB Properties
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Section 7 - RPMs
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Section 8 - Guide Report
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Section 9 - Area Group and Partition Summary
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Section 10 - Modular Design Summary
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Section 11 - Timing Report
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Section 12 - Configuration String Information
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Section 1 - Errors
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------------------
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Section 2 - Warnings
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--------------------
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WARNING:LIT:243 - Logical network adm3a/display/inst_Mram_mem960/SPO has no
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load.
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WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 839
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more times for the following (max. 5 shown):
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adm3a/display/inst_Mram_mem1100/SPO,
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adm3a/display/inst_Mram_mem2100/SPO,
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adm3a/display/inst_Mram_mem3100/SPO,
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adm3a/display/inst_Mram_mem4100/SPO,
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adm3a/display/inst_Mram_mem5100/SPO
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To see the details of these warning messages, please use the -detail switch.
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WARNING:LIT:175 - Clock buffer is designated to drive clock loads. BUFGMUX
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symbol "physical_group_reset_n_BUFGP/reset_n_BUFGP/BUFG" (output
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signal=reset_n_BUFGP) has a mix of clock and non-clock loads. Some of the
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non-clock loads are (maximum of 5 listed):
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Pin CLR of cpu/readmem
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Pin CLR of cpu/inta
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Pin CE of cpu/addr_0
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Pin CE of cpu/addr_1
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Pin CE of cpu/addr_2
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WARNING:Pack:266 - The function generator adm3a/display/chradr<5>35 failed to
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merge with F5 multiplexer adm3a/display/chradr<6>_f5_3. There is a conflict
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for the FXMUX. The design will exhibit suboptimal timing.
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WARNING:Pack:266 - The function generator cpu/_mux0003_SW1 failed to merge with
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F5 multiplexer cpu/_mux0007. There is a conflict for the FXMUX. The design
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will exhibit suboptimal timing.
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WARNING:Pack:266 - The function generator cpu/_mux0003_SW1 failed to merge with
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F5 multiplexer cpu/_mux00031_f5. There is a conflict for the FXMUX. The
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design will exhibit suboptimal timing.
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WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectc/_and0000 is
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sourced by a combinatorial pin. This is not good design practice. Use the CE
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pin to control the loading of data into the flip-flop.
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WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selecta/_and0000 is
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sourced by a combinatorial pin. This is not good design practice. Use the CE
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pin to control the loading of data into the flip-flop.
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WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectd/_and0000 is
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sourced by a combinatorial pin. This is not good design practice. Use the CE
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pin to control the loading of data into the flip-flop.
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WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectb/_and0000 is
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sourced by a combinatorial pin. This is not good design practice. Use the CE
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pin to control the loading of data into the flip-flop.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block::
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6A>.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block::
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6A>.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block::
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6A>.
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Section 3 - Informational
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-------------------------
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INFO:MapLib:562 - No environment variables are currently set.
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INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
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Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
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BUFGP symbol "clock_BUFGP" (output signal=clock_BUFGP),
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BUFGP symbol "reset_n_BUFGP" (output signal=reset_n_BUFGP)
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INFO:LIT:244 - All of the single ended outputs in this design are using slew
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rate limited output drivers. The delay on speed critical single ended outputs
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can be dramatically reduced by designating them as fast outputs in the
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schematic.
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Section 4 - Removed Logic Summary
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---------------------------------
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1 block(s) removed
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3 block(s) optimized away
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1 signal(s) removed
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Section 5 - Removed Logic
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-------------------------
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The trimmed logic reported below is either:
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1. part of a cycle
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2. part of disabled logic
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3. a side-effect of other trimmed logic
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The signal "cpu/regfil_5_1_rt1" is unused and has been removed.
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Unused block "cpu/regfil_5_1_rt1" (ROM) removed.
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Optimized Block(s):
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TYPE BLOCK
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GND XST_GND
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VCC XST_VCC
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MUXCY cpu/Madd__AUX_13_Madd_cy<2>
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To enable printing of redundant blocks removed and signals merged, set the
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detailed map report option and rerun map.
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Section 6 - IOB Properties
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--------------------------
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+------------------------------------------------------------------------------------------------------------------------+
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| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB |
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| | | | | Strength | Rate | | | Delay |
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+------------------------------------------------------------------------------------------------------------------------+
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| addr<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| addr<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| addr<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| addr<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| addr<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| addr<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| addr<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| addr<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| addr<8> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| addr<9> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| addr<10> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| addr<11> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| addr<12> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| addr<13> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| addr<14> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| addr<15> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| b<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| b<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| b<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| clock | IOB | INPUT | LVCMOS25 | | | | | |
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| data<0> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD |
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| data<1> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD |
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| data<2> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD |
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| data<3> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD |
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| data<4> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD |
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| data<5> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD |
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| data<6> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD |
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| data<7> | IOB | BIDIR | LVCMOS25 | 12 | SLOW | INFF1 | | IFD |
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| diag<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| diag<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| diag<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| diag<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| diag<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| diag<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| diag<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| diag<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| g<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| g<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| g<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| hsync_n | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | |
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| inta | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| intr | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| ps2_clk | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD |
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| ps2_data | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD |
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| r<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| r<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| r<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| readio | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| readmem | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| reset_n | IOB | INPUT | LVCMOS25 | | | | | |
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| vsync_n | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| waitr | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| writeio | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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| writemem | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |
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+------------------------------------------------------------------------------------------------------------------------+
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Section 7 - RPMs
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----------------
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Section 8 - Guide Report
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------------------------
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Guide not run on this design.
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Section 9 - Area Group and Partition Summary
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--------------------------------------------
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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Area Group Information
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----------------------
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No area groups were found in this design.
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----------------------
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Section 10 - Modular Design Summary
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-----------------------------------
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Modular Design not used for this design.
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Section 11 - Timing Report
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--------------------------
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This design was not run using timing mode.
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Section 12 - Configuration String Details
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-----------------------------------------
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Use the "-detail" map option to print out Configuration Strings
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