OpenCores
URL https://opencores.org/ocsvn/cpu8080/cpu8080/trunk

Subversion Repositories cpu8080

[/] [cpu8080/] [trunk/] [project/] [testbench_summary.html] - Blame information for rev 24

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 samiam9512 
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
2 
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
3 
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
4 
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
5 
<TD COLSPAN='4'><B>CPU8080 Project Status</B></TD></TR>
6 
<TR ALIGN=LEFT>
7 
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
8 
<TD>cpu8080.ise</TD>
9 
<TD BGCOLOR='#FFFF99'><B>Current State:</B></TD>
10 11 samiam9512 
<TD>Programming File Generated</TD>
11 2 samiam9512 
</TR>
12 
<TR ALIGN=LEFT>
13 
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
14 
<TD>testbench</TD>
15 
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
16 
<TD ALIGN=LEFT>No Errors</TD>
17 
</TR>
18 
<TR ALIGN=LEFT>
19 
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
20 11 samiam9512 
<TD>xc3s1000-4ft256</TD>
21 2 samiam9512 
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
22 24 samiam9512 
<TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/*.xmsgs'>182 Warnings (0 filtered)</A></TD>
23 2 samiam9512 
</TR>
24 
<TR ALIGN=LEFT>
25 
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD>
26 
<TD>ISE 8.2.02i</TD>
27 
<TD BGCOLOR='#FFFF99'><UL><LI><B>Updated:</B></LI></UL></TD>
28 24 samiam9512 
<TD>Thu Nov 16 20:16:53 2006</TD>
29 2 samiam9512 
</TR>
30 
</TABLE>
31 
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
32 
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='4'><B>CPU8080 Partition Summary</B></TD></TR>
33 
<TR><TD COLSPAN='4'>No partition information was found.</TD></TR>
34 
</TABLE>
35 
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
36 11 samiam9512 
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='5'><B>Device Utilization Summary</B></TD></TR>
37 2 samiam9512 
<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
38 11 samiam9512 
<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD><B>Note(s)</B></TD>
39 2 samiam9512 
</TR>
40 11 samiam9512 
<TR ALIGN=RIGHT BGCOLOR='#FFFF99'><TD ALIGN=LEFT><B>Total Number Slice Registers</B></TD>
41 24 samiam9512 
<TD ALIGN=RIGHT>744</TD>
42 11 samiam9512 
<TD ALIGN=RIGHT>15,360</TD>
43 18 samiam9512 
<TD ALIGN=RIGHT>4%</TD>
44 11 samiam9512 
<TD>&nbsp;</TD>
45 2 samiam9512 
</TR>
46 11 samiam9512 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Flip Flops</TD>
47 24 samiam9512 
<TD ALIGN=RIGHT>656</TD>
48 11 samiam9512 
<TD>&nbsp;</TD>
49 
<TD>&nbsp;</TD>
50 
<TD>&nbsp;</TD>
51 
</TR>
52 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Latches</TD>
53 
<TD ALIGN=RIGHT>88</TD>
54 
<TD>&nbsp;</TD>
55 
<TD>&nbsp;</TD>
56 
<TD>&nbsp;</TD>
57 
</TR>
58 2 samiam9512 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of 4 input LUTs</TD>
59 24 samiam9512 
<TD ALIGN=RIGHT>4,397</TD>
60 11 samiam9512 
<TD ALIGN=RIGHT>15,360</TD>
61 20 samiam9512 
<TD ALIGN=RIGHT>28%</TD>
62 11 samiam9512 
<TD>&nbsp;</TD>
63 2 samiam9512 
</TR>
64 11 samiam9512 
<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
65 
<TD ALIGN=LEFT><B>Logic Distribution </B></TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD>
66 2 samiam9512 
</TR>
67 11 samiam9512 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
68 24 samiam9512 
<TD ALIGN=RIGHT>3,445</TD>
69 11 samiam9512 
<TD ALIGN=RIGHT>7,680</TD>
70 24 samiam9512 
<TD ALIGN=RIGHT>44%</TD>
71 11 samiam9512 
<TD>&nbsp;</TD>
72 
</TR>
73 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of Slices containing only related logic</TD>
74 24 samiam9512 
<TD ALIGN=RIGHT>3,445</TD>
75 
<TD ALIGN=RIGHT>3,445</TD>
76 11 samiam9512 
<TD ALIGN=RIGHT>100%</TD>
77 
<TD>&nbsp;</TD>
78 
</TR>
79 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of Slices containing unrelated logic</TD>
80 
<TD ALIGN=RIGHT>0</TD>
81 24 samiam9512 
<TD ALIGN=RIGHT>3,445</TD>
82 11 samiam9512 
<TD ALIGN=RIGHT>0%</TD>
83 
<TD>&nbsp;</TD>
84 
</TR>
85 
<TR ALIGN=RIGHT BGCOLOR='#FFFF99'><TD ALIGN=LEFT><B>Total Number 4 input LUTs</B></TD>
86 24 samiam9512 
<TD ALIGN=RIGHT>6,317</TD>
87 11 samiam9512 
<TD ALIGN=RIGHT>15,360</TD>
88 20 samiam9512 
<TD ALIGN=RIGHT>41%</TD>
89 11 samiam9512 
<TD>&nbsp;</TD>
90 
</TR>
91 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number used as logic</TD>
92 24 samiam9512 
<TD ALIGN=RIGHT>4,397</TD>
93 11 samiam9512 
<TD>&nbsp;</TD>
94 
<TD>&nbsp;</TD>
95 
<TD>&nbsp;</TD>
96 
</TR>
97 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number used as a route-thru</TD>
98 24 samiam9512 
<TD ALIGN=RIGHT>240</TD>
99 11 samiam9512 
<TD>&nbsp;</TD>
100 
<TD>&nbsp;</TD>
101 
<TD>&nbsp;</TD>
102 
</TR>
103 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number used for Dual Port RAMs</TD>
104 
<TD ALIGN=RIGHT>1,680</TD>
105 
<TD>&nbsp;</TD>
106 
<TD>&nbsp;</TD>
107 
<TD>&nbsp;</TD>
108 
</TR>
109 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='testbench_map.mrp?&DataKey=IOBProperties'>IOBs</A></TD>
110 18 samiam9512 
<TD ALIGN=RIGHT>54</TD>
111 11 samiam9512 
<TD ALIGN=RIGHT>173</TD>
112 18 samiam9512 
<TD ALIGN=RIGHT>31%</TD>
113 11 samiam9512 
<TD>&nbsp;</TD>
114 
</TR>
115 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;IOB Flip Flops</TD>
116 18 samiam9512 
<TD ALIGN=RIGHT>11</TD>
117 11 samiam9512 
<TD>&nbsp;</TD>
118 
<TD>&nbsp;</TD>
119 
<TD>&nbsp;</TD>
120 
</TR>
121 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Block RAMs</TD>
122 20 samiam9512 
<TD ALIGN=RIGHT>4</TD>
123 11 samiam9512 
<TD ALIGN=RIGHT>24</TD>
124 20 samiam9512 
<TD ALIGN=RIGHT>16%</TD>
125 11 samiam9512 
<TD>&nbsp;</TD>
126 2 samiam9512 
</TR>
127 11 samiam9512 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MULT18X18s</TD>
128 20 samiam9512 
<TD ALIGN=RIGHT>2</TD>
129 11 samiam9512 
<TD ALIGN=RIGHT>24</TD>
130 20 samiam9512 
<TD ALIGN=RIGHT>8%</TD>
131 11 samiam9512 
<TD>&nbsp;</TD>
132 
</TR>
133 2 samiam9512 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of GCLKs</TD>
134 18 samiam9512 
<TD ALIGN=RIGHT>2</TD>
135 2 samiam9512 
<TD ALIGN=RIGHT>8</TD>
136 18 samiam9512 
<TD ALIGN=RIGHT>25%</TD>
137 11 samiam9512 
<TD>&nbsp;</TD>
138 2 samiam9512 
</TR>
139 11 samiam9512 
<TR ALIGN=RIGHT BGCOLOR='#FFFF99'><TD ALIGN=LEFT><B>Total equivalent gate count for design</B></TD>
140 24 samiam9512 
<TD ALIGN=RIGHT>415,467</TD>
141 11 samiam9512 
<TD>&nbsp;</TD>
142 
<TD>&nbsp;</TD>
143 
<TD>&nbsp;</TD>
144 
</TR>
145 
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Additional JTAG gate count for IOBs</TD>
146 18 samiam9512 
<TD ALIGN=RIGHT>2,592</TD>
147 11 samiam9512 
<TD>&nbsp;</TD>
148 
<TD>&nbsp;</TD>
149 
<TD>&nbsp;</TD>
150 
</TR>
151 2 samiam9512 
</TABLE>
152 
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
153 11 samiam9512 
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='4'><B>Performance Summary</B></TD></TR>
154 
<TR ALIGN=LEFT>
155 
<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
156 
<TD>0</TD>
157 
<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
158 
<TD><A HREF_DISABLED='testbench.pad?&DataKey=PinoutData'>Pinout Report</A></TD>
159 
</TR>
160 
<TR ALIGN=LEFT>
161 
<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD>
162 
<TD><A HREF_DISABLED='testbench.unroutes'>All Signals Completely Routed</A></TD>
163 
<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
164 
<TD><A HREF_DISABLED='testbench.par?&DataKey=ClocksData'>Clock Report</A></TD>
165 
</TR>
166 
<TR ALIGN=LEFT>
167 
<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
168 
<TD><A HREF_DISABLED='testbench.par?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
169 
<TD BGCOLOR='#FFFF99'><B>&nbsp;</B></TD>
170 
<TD>&nbsp;</TD>
171 
</TR>
172 
</TABLE>
173 
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
174 2 samiam9512 
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='6'><B>Detailed Reports</B></TD></TR>
175 
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
176 
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT><B>Infos</B></TD></TR>
177 24 samiam9512 
<TR ALIGN=LEFT><TD><A HREF_DISABLED='testbench.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Thu Nov 16 20:11:26 2006</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/xst.xmsgs'>162 Warnings (0 filtered)</A></TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/xst.xmsgs'>14 Infos (0 filtered)</A></TD></TR>
178 
<TR ALIGN=LEFT><TD><A HREF_DISABLED='testbench.bld'>Translation Report</A></TD><TD>Current</TD><TD>Thu Nov 16 20:11:34 2006</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD></TR>
179 
<TR ALIGN=LEFT><TD><A HREF_DISABLED='testbench_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Thu Nov 16 20:11:54 2006</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/map.xmsgs'>10 Warnings (0 filtered)</A></TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/map.xmsgs'>3 Infos (0 filtered)</A></TD></TR>
180 
<TR ALIGN=LEFT><TD><A HREF_DISABLED='testbench.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Thu Nov 16 20:16:20 2006</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/par.xmsgs'>3 Warnings (0 filtered)</A></TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/par.xmsgs'>3 Infos (0 filtered)</A></TD></TR>
181 
<TR ALIGN=LEFT><TD><A HREF_DISABLED='testbench.twr'>Static Timing Report</A></TD><TD>Current</TD><TD>Thu Nov 16 20:16:34 2006</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/trce.xmsgs'>2 Infos (0 filtered)</A></TD></TR>
182 
<TR ALIGN=LEFT><TD><A HREF_DISABLED='testbench.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Thu Nov 16 20:16:54 2006</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/bitgen.xmsgs'>7 Warnings (0 filtered)</A></TD><TD ALIGN=LEFT>0</TD></TR>
183 2 samiam9512 
</TABLE>
184 
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
185 
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='3'><B>Secondary Reports</B></TD></TR>
186 
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD></TR>
187 
<TR ALIGN=LEFT><TD>Xplorer Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD></TR>
188 
</TABLE>
189 
</BODY></HTML>

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.