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`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company: 

// Engineer: 

// 

// Create Date:    12:02:03 10/22/2006 

// Design Name: 

// Module Name:    vgachr 

// Project Name: 

// Target Devices: 

// Tool versions: 

// Description: 

//

// Dependencies: 

//

// Revision: 

// Revision 0.01 - File Created

// Additional Comments: 

//

//////////////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////////////

//

// TERMINAL EMULATOR

//

// Emulates an ADM 3A dumb terminal, with a MITS serial I/O board interface.

// Two ports are emulated:

//

// 0: Control

// 1: Data

//

// The MITS serial card has all of its configuration performed by jumpers on the

// card, which means there is no programming configuration required. The data

// to the terminal is sent out of the data port, while the data from the 

// keyboard, which is not yet implemented, is read from the same data port.

// The parity is ignored on output, and set to 0 on input.

//

// The control register ignores all writes, and returns $80 if the terminal is

// busy, otherwise $00. This is the output ready to send bit. The busy bit

// reflects if the state machine is processing an operation. This is a cheat

// that only works with our emulated terminal/serial board pair, because 

// normally there is no way for the local CPU to know that the remote terminal

// is busy. This can lead to problems in the real world, and it's why Unix

// "termcap" terminal descriptions commonly have waiting periods perscribed

// time consuming operations like screen clear. This emulated terminal is

// "ideal" in that it accounts for all of this automatically, but it does not

// hurt the realisim of the emulation. An application that performs delays based

// on real terminal operations won't be incorrect because it performs a delay,

// but a stupid application that relies on this "smart" implementation might

// fail to run on the real thing.

//

//

// Terminal height and width

//

`define scnchrs 80 // width

`define scnlins 24 // height

//

// Terminal states

//

`define term_idle    6'h00 // idle

`define term_wrtstd2 6'h01 // write standard character #2

`define term_wrtstd3 6'h02 // write standard character #3

`define term_clear   6'h03 // clear screen and home cursor

`define term_clear2  6'h04 // clear screen and home cursor #2

`define term_clear3  6'h05 // clear screen and home cursor #3

`define term_clear4  6'h06 // clear screen and home cursor #4

module terminal(addr, data, write, read, select, r, g, b, hsync_n, vsync_n,

                reset, clock);

   input        addr;    // control reg/data reg address

   inout [7:0]  data;    // CPU data

   input        write;   // CPU write

   input        read;    // CPU read

   input        select;  // controller select

   input        reset;   // CPU reset

   input        clock;   // CPU clock

   output [2:0] r, g, b; // R,G,B color output buses

   output       hsync_n; // horizontal sync pulse

   output       vsync_n; // vertical sync pulse

   reg [5:0]   state;   // terminal state machine

   reg [10:0]  cursor;  // cursor address

   reg [7:0]   chrdatw; // character write data

   reg         outrdy;  // output ready to send

   reg         wrtchr;  // character ready to write

   reg  [7:0]  datao;   // intermediate for data output

   // character map communication bus

   reg  [10:0] cmaddr;  // character map address to read or write

   reg         cmread;  // character map read from address

   reg         cmwrite; // character map write from address

   wire  [7:0] cmdata;  // character map data to be written/read

   reg   [7:0] cmdatai; // character map data to be written

   reg         cmdatae; // character map data enable

   // instantiate memory mapped character display

   chrmemmap display(!reset, clock, r, g, b, hsync_n, vsync_n, cmaddr, cmread,

                     cmwrite, cmdata);

   // instantiate ps/2 keyboard

   ps2_kbd vgai(.clk(clock), .rst(reset), .ps2_clk(ps2_clk), .ps2_data(ps2_data),

                .scancode(scancode), .parity(parity), .busy(busy), .rdy(rdy),

                .error(error));

//   always @(posedge clock)

   always @(negedge clock)

      if (reset) begin // reset

         // on reset, we set the state machine to perform a screen clear and

         // home cursor

         state <= `term_clear; // set to clear screen

         cursor <= 0; // set cursor to home

         outrdy <= 0; // set not ready to send

         wrtchr <= 0; // set no character to write

         cmread <= 0; // clear read character

         cmwrite <= 0; // clear write character

         cmdatae <= 0; // no enable character map data

   end else if (write&select) begin // CPU write

      if (addr) begin

         chrdatw <= data & 8'h7f; // set character write data without parity

         wrtchr <= 1; // character ready to write

         outrdy <= 0; // remove ready to send

      end

   end else if (read&select) begin // CPU read

      if (addr) datao <= 0; // no keyboard data implemented yet

      else datao <= !outrdy << 7; // return output ready status

   end else case (state) // run output state

      `term_idle: begin // idle waiting for character

         // We wait for the cpu cycle to end before running the state machine

         // write procedure. This allows this module to run at full speed, while

         // the rest of the CPU logic runs slow. The vga logic must run at a 

         // fixed speed because it has the display to run, but the rest can be

         // slow to allow debugging.

         if (wrtchr&!select) begin // process character after CPU goes away

            if (chrdatw >= 8'h20 && chrdatw != 8'h7f) begin

               // write standard (non-control) character

               cmaddr <= cursor; // set address at cursor

               cmdatai <= chrdatw; // place character data to write

               cmdatae <= 1; // enable data to memory

               outrdy <= 0; // set not ready to send

               state <= `term_wrtstd2; // continue

            end else begin // control character, just dump it for now

               wrtchr <= 0; // remove ready to write

               outrdy <= 1; // set ready to send

            end

         end

      end

      `term_wrtstd2: begin // write standard character #2

         cmwrite <= 1; // set write to memory

         state <= `term_wrtstd3; // continue

      end

      `term_wrtstd3: begin // write standard character #3

         cmwrite <= 0; // remove write to memory

         cmdatae <= 0; // release data enable to memory

         outrdy <= 1; // set ready to send

         cursor <= cursor+1; // advance cursor

         wrtchr <= 0; // remove ready to write

         state <= `term_idle; // continue

      end

      `term_clear: begin // clear screen and home cursor

         cmaddr <= 0; // clear buffer address

         cmdatai <= 8'h20; // clear to spaces

         cmdatae <= 1; // enable data to memory

         state <= `term_clear2; // continue

      end

      `term_clear2: begin // clear screen and home cursor #2

         cmwrite <= 1; // set write to memory

         state <= `term_clear3; // continue

      end

      `term_clear3: begin // clear screen and home cursor #2

         cmwrite <= 0; // reset write to memory

         state <= `term_clear4; // continue

      end

      `term_clear4: begin // clear screen and home cursor #4

         if (cmaddr < `scnchrs*`scnlins) begin

            cmaddr <= cmaddr+1; // next character

            // Uncomment the next to put an incrementing pattern instead of

            // spaces.

            //cmdatai <= cmdatai+1;

            state <= `term_clear2; // continue

         end else begin // done

            outrdy <= 1; // set ready to send

            cursor <= 0; // set cursor to home position

            cmdatae <= 0; // release data enable to memory

            state <= `term_idle; // continue

         end

      end

      default: state <= 6'bx;

   endcase

   // Enable drive to character memory

   assign cmdata = cmdatae ? cmdatai: 8'bz;

   // Enable drive for data output

   assign data = read&select ? datao: 8'bz;

endmodule

////////////////////////////////////////////////////////////////////////////////

//

// MEMORY MAPPED CHARACTER DISPLAY

//

// Contains the 20x8 characters used in a 640x480, 25 lines of 80 characters

// display. This display is accessed vi a 1920 character memory, which can be 

// written and read. It is dual port, so has no restrictions on read and write.

//

// This block can either be directly mapped to CPU main memory, or can be run

// via a terminal emulator.

//

module chrmemmap(rst_n, clk, r, g, b, hsync_n, vsync_n, addr, read, write,

                 data);

      input         rst_n;   // reset

      input         clk;     // master clock

      output [2:0]  r, g, b; // R,G,B color output buses

      output        hsync_n; // horizontal sync pulse

      output        vsync_n; // vertical sync pulse

      input  [10:0] addr;    // address to read or write

      input         read;    // read from address

      input         write;   // write from address

      inout  [7:0]  data;    // data to be written/read

   reg [15:0] pixeldata; // 16 bit pixel feed

   reg  [6:0]  chrcnt;  // character counter

   reg  [4:0]  rowcnt;  // character row counter

   reg  [4:0]  lincnt;  // line counter

   reg  [10:0] scnadr;  // screen character buffer address

   reg  [7:0]  curchr;  // current character indexed by scnadr

   reg  [1:0]  fchsta;  // character fetch state, 0 = load high, 1 = load low

   wire [10:0] chradr;  // character generator address

   wire [7:0]  chrdata; // character generator data

   reg  [7:0]  datao;   // intermediate for data output

   // storage for character based screen

   reg [7:0] scnbuf[1919:0];

   assign rst = ~rst_n; // change reset polarity

   vga vgai(.rst(rst), .clk(clk), .pixel_data_in(pixeldata), .rd(rd), .eof(eof),

            .r(r), .g(g), .b(b), .hsync_n(hsync_n), .vsync_n(vsync_n),

            .blank(blank));

   chrrom crom(chradr, chrdata); // place character generator

   // run the character to screen scan

   always @(posedge clk)

      if (rst|eof) begin // if reset or end of frame

      chrcnt <= 7'h0; // clear counters

      rowcnt <= 5'h0;

      lincnt <= 5'h0;

      scnadr <= 11'h0;

      fchsta <= 0;

   end else if (rd || fchsta) begin

      if (fchsta == 1 || fchsta == 3) begin

         // advance counters

         if (chrcnt < 79) chrcnt <= chrcnt+1; // next character count

         else begin // next row

            chrcnt <= 0; // reset character

            if (rowcnt < 19) rowcnt <= rowcnt+1; // next character row

            else begin // next line

               rowcnt <= 0; // reset row

               lincnt <= lincnt+1; // next line

               scnadr <= scnadr+80; // advance character fetch

            end

         end

      end

      // Choose high or low character, and next state. Note we have to flip the

      // characters left to right to be correct.

      case (fchsta)

         0: fchsta <= 1; // delay until rd cycle is over

         1: begin

            // set low bits of pixel register

            pixeldata <=  { chrdata[0], chrdata[1], chrdata[2], chrdata[3],

                            chrdata[4], chrdata[5], chrdata[6], chrdata[7] };

            fchsta <= 2; // next state

         end

         2: fchsta <= 3; // delay a cycle for ROM read time

         3: begin

            // set just high bits of pixel register

            pixeldata <=

               pixeldata & 16'h00ff |

               { chrdata[0], chrdata[1], chrdata[2], chrdata[3],

                 chrdata[4], chrdata[5], chrdata[6], chrdata[7] } << 8;

            fchsta <= 0; // back to start

         end

      endcase

   end

   // operate dual port screen character RAM

   always @(posedge clk) begin

      // set current indexed character without parity

      assign curchr = scnbuf[scnadr+chrcnt] & 8'h7f;

      if (write) scnbuf[addr] <= data;

      datao <= scnbuf[addr];

   end

   // create character address from character in buffer and current row

   assign chradr =

      (curchr < 8'h20 || curchr == 8'h7f) ? 11'h0: (curchr-8'h20)*20+rowcnt;

   // Enable drive for data output

   assign data = read ? datao: 8'bz;

endmodule

////////////////////////////////////////////////////////////////////////////////

//

// CHARACTER ROM

//

// Contains the 20x8 characters used in a 640x480, 25 lines of 80 characters

// display.

//

module chrrom(addr, data);

   input  [10:0] addr;

   output [7:0]  data;

   reg [7:0]  data;

   always @(addr) case (addr)

      // character set starting with space, and ending with '~'

      11'h000: data = 8'b00000000; // ' '

      11'h001: data = 8'b00000000;

      11'h002: data = 8'b00000000;

      11'h003: data = 8'b00000000;

      11'h004: data = 8'b00000000;

      11'h005: data = 8'b00000000;

      11'h006: data = 8'b00000000;

      11'h007: data = 8'b00000000;

      11'h008: data = 8'b00000000;

      11'h009: data = 8'b00000000;

      11'h00A: data = 8'b00000000;

      11'h00B: data = 8'b00000000;

      11'h00C: data = 8'b00000000;

      11'h00D: data = 8'b00000000;

      11'h00E: data = 8'b00000000;

      11'h00F: data = 8'b00000000;

      11'h010: data = 8'b00000000;

      11'h011: data = 8'b00000000;

      11'h012: data = 8'b00000000;

      11'h013: data = 8'b00000000;

      11'h014: data = 8'b00000000; // '!'

      11'h015: data = 8'b00010000;

      11'h016: data = 8'b00010000;

      11'h017: data = 8'b00010000;

      11'h018: data = 8'b00010000;

      11'h019: data = 8'b00010000;

      11'h01A: data = 8'b00010000;

      11'h01B: data = 8'b00010000;

      11'h01C: data = 8'b00010000;

      11'h01D: data = 8'b00010000;

      11'h01E: data = 8'b00010000;

      11'h01F: data = 8'b00000000;

      11'h020: data = 8'b00000000;

      11'h021: data = 8'b00010000;

      11'h022: data = 8'b00010000;

      11'h023: data = 8'b00000000;

      11'h024: data = 8'b00000000;

      11'h025: data = 8'b00000000;

      11'h026: data = 8'b00000000;

      11'h027: data = 8'b00000000;

      11'h028: data = 8'b00000000; // '"'

      11'h029: data = 8'b00101000;

      11'h02A: data = 8'b00101000;

      11'h02B: data = 8'b00000000;

      11'h02C: data = 8'b00000000;

      11'h02D: data = 8'b00000000;

      11'h02E: data = 8'b00000000;

      11'h02F: data = 8'b00000000;

      11'h030: data = 8'b00000000;

      11'h031: data = 8'b00000000;

      11'h032: data = 8'b00000000;

      11'h033: data = 8'b00000000;

      11'h034: data = 8'b00000000;

      11'h035: data = 8'b00000000;

      11'h036: data = 8'b00000000;

      11'h037: data = 8'b00000000;

      11'h038: data = 8'b00000000;

      11'h039: data = 8'b00000000;

      11'h03A: data = 8'b00000000;

      11'h03B: data = 8'b00000000;

      11'h03C: data = 8'b00000000; // '#'

      11'h03D: data = 8'b00100100;

      11'h03E: data = 8'b00100100;

      11'h03F: data = 8'b00100100;

      11'h040: data = 8'b00100100;

      11'h041: data = 8'b01111110;

      11'h042: data = 8'b00100100;

      11'h043: data = 8'b00100100;

      11'h044: data = 8'b00100100;

      11'h045: data = 8'b00100100;

      11'h046: data = 8'b01111110;

      11'h047: data = 8'b00100100;

      11'h048: data = 8'b00100100;

      11'h049: data = 8'b00100100;

      11'h04A: data = 8'b00100100;

      11'h04B: data = 8'b00000000;

      11'h04C: data = 8'b00000000;

      11'h04D: data = 8'b00000000;

      11'h04E: data = 8'b00000000;

      11'h04F: data = 8'b00000000;

      11'h050: data = 8'b00000000; // '$'

      11'h051: data = 8'b00010000;

      11'h052: data = 8'b00111100;

      11'h053: data = 8'b01010010;

      11'h054: data = 8'b01010000;

      11'h055: data = 8'b01010000;

      11'h056: data = 8'b00110000;

      11'h057: data = 8'b00011000;

      11'h058: data = 8'b00010100;

      11'h059: data = 8'b00010010;

      11'h05A: data = 8'b00010010;

      11'h05B: data = 8'b00010010;

      11'h05C: data = 8'b01010100;

      11'h05D: data = 8'b00111000;

      11'h05E: data = 8'b00010000;

      11'h05F: data = 8'b00000000;

      11'h060: data = 8'b00000000;

      11'h061: data = 8'b00000000;

      11'h062: data = 8'b00000000;

      11'h063: data = 8'b00000000;

      11'h064: data = 8'b00000000; // '%'

      11'h065: data = 8'b01110010;

      11'h066: data = 8'b01010010;

      11'h067: data = 8'b01110100;

      11'h068: data = 8'b00000100;

      11'h069: data = 8'b00001000;

      11'h06A: data = 8'b00001000;

      11'h06B: data = 8'b00001000;

      11'h06C: data = 8'b00010000;

      11'h06D: data = 8'b00010000;

      11'h06E: data = 8'b00010000;

      11'h06F: data = 8'b00100000;

      11'h070: data = 8'b00101110;

      11'h071: data = 8'b01001010;

      11'h072: data = 8'b01001110;

      11'h073: data = 8'b00000000;

      11'h074: data = 8'b00000000;

      11'h075: data = 8'b00000000;

      11'h076: data = 8'b00000000;

      11'h077: data = 8'b00000000;

      11'h078: data = 8'b00000000; // '&'

      11'h079: data = 8'b00110000;

      11'h07A: data = 8'b01001000;

      11'h07B: data = 8'b01001000;

      11'h07C: data = 8'b01010000;

      11'h07D: data = 8'b00100000;

      11'h07E: data = 8'b00100000;

      11'h07F: data = 8'b01100000;

      11'h080: data = 8'b01010000;

      11'h081: data = 8'b01010000;

      11'h082: data = 8'b01001000;

      11'h083: data = 8'b01001000;

      11'h084: data = 8'b01000100;

      11'h085: data = 8'b00100100;

      11'h086: data = 8'b00011010;

      11'h087: data = 8'b00000000;

      11'h088: data = 8'b00000000;

      11'h089: data = 8'b00000000;

      11'h08A: data = 8'b00000000;

      11'h08B: data = 8'b00000000;

      11'h08C: data = 8'b00000000; // '''

      11'h08D: data = 8'b00010000;

      11'h08E: data = 8'b00010000;

      11'h08F: data = 8'b00000000;

      11'h090: data = 8'b00000000;

      11'h091: data = 8'b00000000;

      11'h092: data = 8'b00000000;

      11'h093: data = 8'b00000000;

      11'h094: data = 8'b00000000;

      11'h095: data = 8'b00000000;

      11'h096: data = 8'b00000000;

      11'h097: data = 8'b00000000;

      11'h098: data = 8'b00000000;

      11'h099: data = 8'b00000000;

      11'h09A: data = 8'b00000000;

      11'h09B: data = 8'b00000000;

      11'h09C: data = 8'b00000000;

      11'h09D: data = 8'b00000000;

      11'h09E: data = 8'b00000000;

      11'h09F: data = 8'b00000000;

      11'h0A0: data = 8'b00000000; // '('

      11'h0A1: data = 8'b00000010;

      11'h0A2: data = 8'b00000100;

      11'h0A3: data = 8'b00001000;

      11'h0A4: data = 8'b00010000;

      11'h0A5: data = 8'b00100000;

      11'h0A6: data = 8'b01000000;

      11'h0A7: data = 8'b01000000;

      11'h0A8: data = 8'b01000000;

      11'h0A9: data = 8'b01000000;

      11'h0AA: data = 8'b00100000;

      11'h0AB: data = 8'b00010000;

      11'h0AC: data = 8'b00001000;

      11'h0AD: data = 8'b00000100;

      11'h0AE: data = 8'b00000010;

      11'h0AF: data = 8'b00000000;

      11'h0B0: data = 8'b00000000;

      11'h0B1: data = 8'b00000000;

      11'h0B2: data = 8'b00000000;