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<P><table class="ttop"><th class="ttop"></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="02_Top_Level.html">Next Lesson</a></th></table>
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<hr>
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<H1><A NAME="section_1">1 INTRODUCTION AND OVERVIEW</A></H1>
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<P>This lecture describes in detail how you can design a CPU (actually
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an embedded system) in VHDL.
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<P>The CPU has an instruction set similar to the instruction set of the
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popular 8-bit CPUs made by <STRONG>Atmel</STRONG>. The instruction set is described in
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<A HREF="http://www.atmel.com/dyn/resources/prod_documents/doc0856.pdf">http://www.atmel.com/dyn/resources/prod_documents/doc0856.pdf</A>. We use
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an existing CPU so that we can reuse a software tool chain (<STRONG>avr-gcc</STRONG>)
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for this kind of CPU and focus on the hardware aspects of the design.
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At the end of the lecture, however, you will be able to design your own
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CPU with a different instruction set.
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<P>We will not implement the full instruction set; only the fraction needed
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to explain the principles, and to run a simple "Hello world" program (and
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probably most C programs) will be described.
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<H2><A NAME="section_1_1">1.1 Prerequisites</A></H2>
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<P>Initially you will need two programs:
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<UL>
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<LI><STRONG>ghdl</STRONG> from <A HREF="http://ghdl.free.fr">http://ghdl.free.fr</A> (a free VHDL compiler and simulator) and
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<LI><STRONG>gtkwave</STRONG> from <A HREF="http://gtkwave.sourceforge.net">http://gtkwave.sourceforge.net</A> (a free visualization tool
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for the output of ghdl).
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</UL>
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<P>These two programs allow you to design the CPU and simulate its functions.
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<P>Later on, you will need a FPGA toolchain for creating FPGA design files
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and to perform timing simulations. For this lecture we assume that the
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free <STRONG>Xilinx Webpack</STRONG> tool chain is used (<A HREF="http://www.xilinx.com">http://www.xilinx.com</A>).
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The latest version of the Xilinx Webpack provides ISE 11 (as of Nov. 2009)
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but we used ISE 10.1 because we used an FPGA board providing a good old
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Spartan 2E FPGA (actually an xc2s300e device) which is no longer supported
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in ISE 11.
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<P>Once the CPU design is finished, you need a C compiler that generates code
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for the AVR CPU. For downloading <STRONG>avr-gcc</STRONG>, start here:
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<P><A HREF="http://www.avrfreaks.net/wiki/index.php/Documentation:AVR_GCC#AVR-GCC_on_Unix_and_Linux">http://www.avrfreaks.net/wiki/index.php/Documentation:AVR_GCC#AVR-GCC_on_Unix_and_Linux</A>
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<P>In order to try out the CPU, you will need some FPGA board
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and a programming cable. We used a Memec "Spartan-IIE LC Development Kit"
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board and an Avnet "Parallel Cable 3" for this purpose.
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These days you will want to use a more recent development environment.
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When the hardware runs, the final thing to get is a software toolchain,
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for example <STRONG>avr-gcc</STRONG> for the instruction set and memory layout
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used in this lecture. Optional, but rather helpful, is <STRONG>eclipse</STRONG>
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(<A HREF="http://www.eclipse.org">http://www.eclipse.org</A>) with the AVR plugin.
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<P>Another important prerequisite is that the reader is familiar with
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VHDL to some extent. You do not need to be a VHDL expert in order
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to follow this lecture, but you should not be a VHDL novice either.
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<H2><A NAME="section_1_2">1.2 Other useful links.</A></H2>
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<P>A good introduction into VHDL design with open source tools can
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be found here:
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<P><A HREF="http://www.armadeus.com/wiki/index.php?title=How_to_make_a_VHDL_design_in_Ubuntu/Debian">http://www.armadeus.com/wiki/index.php?title=How_to_make_a_VHDL_design_in_Ubuntu/Debian</A>
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<H2><A NAME="section_1_3">1.3 Structure of this Lecture</A></H2>
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<P>This lecture is organized as a sequence of lessons. The first lessons will
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describe the VHDL files of the CPU design in a top-down fashion.
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<P>Then follows a lesson on how to compile, simulate and build the design.
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<P>Finally there is a listing of all design files with line numbers.
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Pieces of these design files will be spread over
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the different lessons and explained there in detail. In the end, all code
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lines in the appendix should have been explained, with the exception of
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comments, empty lines and the like. Repetitions such as the structure
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of VHDL files or different opcodes that are implemented in the same way,
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will only be described once.
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<P>All source files are provided (without line numbers) in a tar file
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that is stored next to this lecture.
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<H2><A NAME="section_1_4">1.4 Naming Conventions</A></H2>
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<P>In all lessons and in the VHDL source files, the following conventions
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are used:
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<P>VHDL entities and components and VHDL keywords are written in <STRONG>lowercase</STRONG>.
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Signal names and variables are written in <STRONG>UPPERCASE</STRONG>.
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Each signal has a prefix according to the following rules:
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<TABLE>
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<TR><TD>I_</TD><TD>for inputs of a VHDL entity.
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</TD></TR><TR><TD>Q_</TD><TD>for outputs of a VHDL entity.
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</TD></TR><TR><TD>L_</TD><TD>for local signals that are generated by a VHDL construct (e.g. by a signal assignment).
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</TD></TR><TR><TD>x_</TD><TD>with an uppercase x for signals <STRONG>generated</STRONG> by an instantiated entity.
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</TD></TR>
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</TABLE>
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<P>For every instantiated component we choose an uppercase letter x (other than
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I, L, or Q). All signals driven by the component then get the prefix <STRONG>Q_</STRONG>
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(if the instantiated component drives an output of the entity being defined)
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or the prefix <STRONG>x_</STRONG> (if the component drives an internal signal).
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<P>Apart from the prefix, we try to keep the name of a signal the
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same across different VHDL files. Unless the prefix matters, we will
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use the signal name <STRONG>without its prefix</STRONG> in our descriptions.
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<P>Another convention is that we use one VHLD source file for every
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entity that we define and that the name of the file (less the
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.vhd extension) matches the entity name.
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<H2><A NAME="section_1_5">1.5 Directory Structure</A></H2>
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<P>Create a directory of your choice. In that directory, <STRONG>mkdir</STRONG> the following
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sub-directories:
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<TABLE>
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<TR><TD>app</TD><TD>for building the program that will run on the CPU (i.e. <STRONG>hello.c</STRONG>)
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</TD></TR><TR><TD>simu</TD><TD>for object files generated by <STRONG>ghdl</STRONG>
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</TD></TR><TR><TD>src</TD><TD>for VHDL source files of the CPU and <STRONG>avr_fpga.ucf</STRONG>
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</TD></TR><TR><TD>test</TD><TD>for a VHDL testbench
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</TD></TR><TR><TD>tools</TD><TD>for tools <STRONG>end_conv</STRONG> and <STRONG>make_mem</STRONG>
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</TD></TR><TR><TD>work</TD><TD>working directory for <STRONG>ghdl</STRONG>
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</TD></TR>
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</TABLE>
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<P>Initially the directory should look like this:
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<pre class="cmd">
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# ls -R .
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./app:
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hello.c
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./simu:
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./src:
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alu.vhd
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avr_fpga.ucf
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avr_fpga.vhd
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baudgen.vhd
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common.vhd
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COPYING
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cpu_core.vhd
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data_mem.vhd
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data_path.vhd
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io.vhd
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opc_deco.vhd
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opc_fetch.vhd
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prog_mem_content.vhd
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prog_mem.vhd
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reg_16.vhd
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register_file.vhd
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segment7.vhd
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status_reg.vhd
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uart_rx.vhd
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uart_tx.vhd
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uart.vhd
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./test:
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RAMB4_S4_S4.vhd
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test_tb.vhd
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./tools:
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end_conv.cc
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make_mem.cc
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./work:
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</pre>
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<P>
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<H2><A NAME="section_1_6">1.6 Other Useful Tools</A></H2>
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<P>This lecture was prepared with 3 excellent tools:
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<UL>
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<LI><STRONG>vim</STRONG> 7.1.38 for preparing the text of the lecture,
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<LI><STRONG>txt2html</STRONG> 2.46 for converting the text into html, and
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<LI><STRONG>dia</STRONG> 0.5 for drawing the figures.
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</UL>
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<P><hr><BR>
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<table class="ttop"><th class="ttop"></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="02_Top_Level.html">Next Lesson</a></th></table>
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