1 |
2 |
jsauermann |
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN"
|
2 |
|
|
"http://www.w3.org/TR/html4/strict.dtd">
|
3 |
|
|
<HTML>
|
4 |
|
|
<HEAD>
|
5 |
|
|
<TITLE>html/Listing_of_avr_fpga.vhd</TITLE>
|
6 |
|
|
<META NAME="generator" CONTENT="HTML::TextToHTML v2.46">
|
7 |
|
|
<LINK REL="stylesheet" TYPE="text/css" HREF="lecture.css">
|
8 |
|
|
</HEAD>
|
9 |
|
|
<BODY>
|
10 |
|
|
<P><table class="ttop"><th class="tpre"><a href="10_Listing_of_alu_vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="12_Listing_of_baudgen.vhd.html">Next Lesson</a></th></table>
|
11 |
|
|
<hr>
|
12 |
|
|
|
13 |
|
|
<H1><A NAME="section_1">11 LISTING OF avr_fpga.vhd</A></H1>
|
14 |
|
|
|
15 |
|
|
<pre class="vhdl">
|
16 |
|
|
|
17 |
|
|
1 -------------------------------------------------------------------------------
|
18 |
|
|
2 --
|
19 |
|
|
3 -- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
|
20 |
|
|
4 --
|
21 |
|
|
5 -- This code is free software: you can redistribute it and/or modify
|
22 |
|
|
6 -- it under the terms of the GNU General Public License as published by
|
23 |
|
|
7 -- the Free Software Foundation, either version 3 of the License, or
|
24 |
|
|
8 -- (at your option) any later version.
|
25 |
|
|
9 --
|
26 |
|
|
10 -- This code is distributed in the hope that it will be useful,
|
27 |
|
|
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
28 |
|
|
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
29 |
|
|
13 -- GNU General Public License for more details.
|
30 |
|
|
14 --
|
31 |
|
|
15 -- You should have received a copy of the GNU General Public License
|
32 |
|
|
16 -- along with this code (see the file named COPYING).
|
33 |
|
|
17 -- If not, see http://www.gnu.org/licenses/.
|
34 |
|
|
18 --
|
35 |
|
|
19 -------------------------------------------------------------------------------
|
36 |
|
|
20 -------------------------------------------------------------------------------
|
37 |
|
|
21 --
|
38 |
|
|
22 -- Module Name: avr_fpga - Behavioral
|
39 |
|
|
23 -- Create Date: 13:51:24 11/07/2009
|
40 |
|
|
24 -- Description: top level of a CPU
|
41 |
|
|
25 --
|
42 |
|
|
26 -------------------------------------------------------------------------------
|
43 |
|
|
27
|
44 |
|
|
28 library IEEE;
|
45 |
|
|
29 use IEEE.STD_LOGIC_1164.ALL;
|
46 |
|
|
30 use IEEE.STD_LOGIC_ARITH.ALL;
|
47 |
|
|
31 use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
48 |
|
|
32
|
49 |
|
|
33 entity avr_fpga is
|
50 |
|
|
34 port ( I_CLK_100 : in std_logic;
|
51 |
|
|
35 I_SWITCH : in std_logic_vector(9 downto 0);
|
52 |
|
|
36 I_RX : in std_logic;
|
53 |
|
|
37
|
54 |
|
|
38 Q_LEDS : out std_logic_vector(3 downto 0);
|
55 |
|
|
39 Q_7_SEGMENT : out std_logic_vector(6 downto 0);
|
56 |
|
|
40 Q_TX : out std_logic);
|
57 |
|
|
41 end avr_fpga;
|
58 |
|
|
42
|
59 |
|
|
43 architecture Behavioral of avr_fpga is
|
60 |
|
|
44
|
61 |
|
|
45 component cpu_core
|
62 |
|
|
46 port ( I_CLK : in std_logic;
|
63 |
|
|
47 I_CLR : in std_logic;
|
64 |
|
|
48 I_INTVEC : in std_logic_vector( 5 downto 0);
|
65 |
|
|
49 I_DIN : in std_logic_vector( 7 downto 0);
|
66 |
|
|
50
|
67 |
|
|
51 Q_OPC : out std_logic_vector(15 downto 0);
|
68 |
|
|
52 Q_PC : out std_logic_vector(15 downto 0);
|
69 |
|
|
53 Q_DOUT : out std_logic_vector( 7 downto 0);
|
70 |
|
|
54 Q_ADR_IO : out std_logic_vector( 7 downto 0);
|
71 |
|
|
55 Q_RD_IO : out std_logic;
|
72 |
|
|
56 Q_WE_IO : out std_logic);
|
73 |
|
|
57 end component;
|
74 |
|
|
58
|
75 |
|
|
59 signal C_PC : std_logic_vector(15 downto 0);
|
76 |
|
|
60 signal C_OPC : std_logic_vector(15 downto 0);
|
77 |
|
|
61 signal C_ADR_IO : std_logic_vector( 7 downto 0);
|
78 |
|
|
62 signal C_DOUT : std_logic_vector( 7 downto 0);
|
79 |
|
|
63 signal C_RD_IO : std_logic;
|
80 |
|
|
64 signal C_WE_IO : std_logic;
|
81 |
|
|
65
|
82 |
|
|
66 component io
|
83 |
|
|
67 port ( I_CLK : in std_logic;
|
84 |
|
|
68 I_CLR : in std_logic;
|
85 |
|
|
69 I_ADR_IO : in std_logic_vector( 7 downto 0);
|
86 |
|
|
70 I_DIN : in std_logic_vector( 7 downto 0);
|
87 |
|
|
71 I_RD_IO : in std_logic;
|
88 |
|
|
72 I_WE_IO : in std_logic;
|
89 |
|
|
73 I_SWITCH : in std_logic_vector( 7 downto 0);
|
90 |
|
|
74 I_RX : in std_logic;
|
91 |
|
|
75
|
92 |
|
|
76 Q_7_SEGMENT : out std_logic_vector( 6 downto 0);
|
93 |
|
|
77 Q_DOUT : out std_logic_vector( 7 downto 0);
|
94 |
|
|
78 Q_INTVEC : out std_logic_vector(5 downto 0);
|
95 |
|
|
79 Q_LEDS : out std_logic_vector( 1 downto 0);
|
96 |
|
|
80 Q_TX : out std_logic);
|
97 |
|
|
81
|
98 |
|
|
82 end component;
|
99 |
|
|
83
|
100 |
|
|
84 signal N_INTVEC : std_logic_vector( 5 downto 0);
|
101 |
|
|
85 signal N_DOUT : std_logic_vector( 7 downto 0);
|
102 |
|
|
86 signal N_TX : std_logic;
|
103 |
|
|
87 signal N_7_SEGMENT : std_logic_vector( 6 downto 0);
|
104 |
|
|
88
|
105 |
|
|
89 component segment7
|
106 |
|
|
90 port ( I_CLK : in std_logic;
|
107 |
|
|
91
|
108 |
|
|
92 I_CLR : in std_logic;
|
109 |
|
|
93 I_OPC : in std_logic_vector(15 downto 0);
|
110 |
|
|
94 I_PC : in std_logic_vector(15 downto 0);
|
111 |
|
|
95
|
112 |
|
|
96 Q_7_SEGMENT : out std_logic_vector( 6 downto 0));
|
113 |
|
|
97 end component;
|
114 |
|
|
98
|
115 |
|
|
99 signal S_7_SEGMENT : std_logic_vector( 6 downto 0);
|
116 |
|
|
100
|
117 |
|
|
101 signal L_CLK : std_logic := '0';
|
118 |
|
|
102 signal L_CLK_CNT : std_logic_vector( 2 downto 0) := "000";
|
119 |
|
|
103 signal L_CLR : std_logic; -- reset, active low
|
120 |
|
|
104 signal L_CLR_N : std_logic := '0'; -- reset, active low
|
121 |
|
|
105 signal L_C1_N : std_logic := '0'; -- switch debounce, active low
|
122 |
|
|
106 signal L_C2_N : std_logic := '0'; -- switch debounce, active low
|
123 |
|
|
107
|
124 |
|
|
108 begin
|
125 |
|
|
109
|
126 |
|
|
110 cpu : cpu_core
|
127 |
|
|
111 port map( I_CLK => L_CLK,
|
128 |
|
|
112 I_CLR => L_CLR,
|
129 |
|
|
113 I_DIN => N_DOUT,
|
130 |
|
|
114 I_INTVEC => N_INTVEC,
|
131 |
|
|
115
|
132 |
|
|
116 Q_ADR_IO => C_ADR_IO,
|
133 |
|
|
117 Q_DOUT => C_DOUT,
|
134 |
|
|
118 Q_OPC => C_OPC,
|
135 |
|
|
119 Q_PC => C_PC,
|
136 |
|
|
120 Q_RD_IO => C_RD_IO,
|
137 |
|
|
121 Q_WE_IO => C_WE_IO);
|
138 |
|
|
122
|
139 |
|
|
123 ino : io
|
140 |
|
|
124 port map( I_CLK => L_CLK,
|
141 |
|
|
125 I_CLR => L_CLR,
|
142 |
|
|
126 I_ADR_IO => C_ADR_IO,
|
143 |
|
|
127 I_DIN => C_DOUT,
|
144 |
|
|
128 I_RD_IO => C_RD_IO,
|
145 |
|
|
129 I_RX => I_RX,
|
146 |
|
|
130 I_SWITCH => I_SWITCH(7 downto 0),
|
147 |
|
|
131 I_WE_IO => C_WE_IO,
|
148 |
|
|
132
|
149 |
|
|
133 Q_7_SEGMENT => N_7_SEGMENT,
|
150 |
|
|
134 Q_DOUT => N_DOUT,
|
151 |
|
|
135 Q_INTVEC => N_INTVEC,
|
152 |
|
|
136 Q_LEDS => Q_LEDS(1 downto 0),
|
153 |
|
|
137 Q_TX => N_TX);
|
154 |
|
|
138
|
155 |
|
|
139 seg : segment7
|
156 |
|
|
140 port map( I_CLK => L_CLK,
|
157 |
|
|
141 I_CLR => L_CLR,
|
158 |
|
|
142 I_OPC => C_OPC,
|
159 |
|
|
143 I_PC => C_PC,
|
160 |
|
|
144
|
161 |
|
|
145 Q_7_SEGMENT => S_7_SEGMENT);
|
162 |
|
|
146
|
163 |
|
|
147 -- input clock scaler
|
164 |
|
|
148 --
|
165 |
|
|
149 clk_div : process(I_CLK_100)
|
166 |
|
|
150 begin
|
167 |
|
|
151 if (rising_edge(I_CLK_100)) then
|
168 |
|
|
152 L_CLK_CNT <= L_CLK_CNT + "001";
|
169 |
|
|
153 if (L_CLK_CNT = "001") then
|
170 |
|
|
154 L_CLK_CNT <= "000";
|
171 |
|
|
155 L_CLK <= not L_CLK;
|
172 |
|
|
156 end if;
|
173 |
|
|
157 end if;
|
174 |
|
|
158 end process;
|
175 |
|
|
159
|
176 |
|
|
160 -- reset button debounce process
|
177 |
|
|
161 --
|
178 |
|
|
162 deb : process(L_CLK)
|
179 |
|
|
163 begin
|
180 |
|
|
164 if (rising_edge(L_CLK)) then
|
181 |
|
|
165 -- switch debounce
|
182 |
|
|
166 if ((I_SWITCH(8) = '0') or (I_SWITCH(9) = '0')) then -- pushed
|
183 |
|
|
167 L_CLR_N <= '0';
|
184 |
|
|
168 L_C2_N <= '0';
|
185 |
|
|
169 L_C1_N <= '0';
|
186 |
|
|
170 else -- released
|
187 |
|
|
171 L_CLR_N <= L_C2_N;
|
188 |
|
|
172 L_C2_N <= L_C1_N;
|
189 |
|
|
173 L_C1_N <= '1';
|
190 |
|
|
174 end if;
|
191 |
|
|
175 end if;
|
192 |
|
|
176 end process;
|
193 |
|
|
177
|
194 |
|
|
178 L_CLR <= not L_CLR_N;
|
195 |
|
|
179
|
196 |
|
|
180 Q_LEDS(2) <= I_RX;
|
197 |
|
|
181 Q_LEDS(3) <= N_TX;
|
198 |
|
|
182 Q_7_SEGMENT <= N_7_SEGMENT when (I_SWITCH(7) = '1') else S_7_SEGMENT;
|
199 |
|
|
183 Q_TX <= N_TX;
|
200 |
|
|
184
|
201 |
|
|
185 end Behavioral;
|
202 |
|
|
186
|
203 |
|
|
<pre class="filename">
|
204 |
|
|
src/avr_fpga.vhd
|
205 |
|
|
</pre></pre>
|
206 |
|
|
<P>
|
207 |
|
|
|
208 |
|
|
<P><hr><BR>
|
209 |
|
|
<table class="ttop"><th class="tpre"><a href="10_Listing_of_alu_vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="12_Listing_of_baudgen.vhd.html">Next Lesson</a></th></table>
|
210 |
|
|
</BODY>
|
211 |
|
|
</HTML>
|