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<P><table class="ttop"><th class="tpre"><a href="12_Listing_of_baudgen.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="14_Listing_of_cpu_core.vhd.html">Next Lesson</a></th></table>
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<H1><A NAME="section_1">13 LISTING OF common.vhd</A></H1>
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<pre class="vhdl">
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1 -------------------------------------------------------------------------------
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2 --
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3 -- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
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4 --
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5 -- This code is free software: you can redistribute it and/or modify
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6 -- it under the terms of the GNU General Public License as published by
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7 -- the Free Software Foundation, either version 3 of the License, or
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8 -- (at your option) any later version.
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9 --
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10 -- This code is distributed in the hope that it will be useful,
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11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
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12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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13 -- GNU General Public License for more details.
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14 --
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15 -- You should have received a copy of the GNU General Public License
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16 -- along with this code (see the file named COPYING).
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17 -- If not, see http://www.gnu.org/licenses/.
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18 --
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19 -------------------------------------------------------------------------------
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20 -------------------------------------------------------------------------------
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21 --
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22 -- Module Name: common
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23 -- Create Date: 13:51:24 11/07/2009
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24 -- Description: constants shared by different modules.
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25 --
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26 -------------------------------------------------------------------------------
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27 --
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28 library IEEE;
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29 use IEEE.STD_LOGIC_1164.all;
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30
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31 package common is
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32
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33 -----------------------------------------------------------------------
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34
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35 -- ALU operations
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36 --
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37 constant ALU_ADC : std_logic_vector(4 downto 0) := "00000";
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38 constant ALU_ADD : std_logic_vector(4 downto 0) := "00001";
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39 constant ALU_ADIW : std_logic_vector(4 downto 0) := "00010";
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40 constant ALU_AND : std_logic_vector(4 downto 0) := "00011";
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41 constant ALU_ASR : std_logic_vector(4 downto 0) := "00100";
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42 constant ALU_BLD : std_logic_vector(4 downto 0) := "00101";
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43 constant ALU_BIT_CS : std_logic_vector(4 downto 0) := "00110";
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44 constant ALU_COM : std_logic_vector(4 downto 0) := "00111";
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45 constant ALU_DEC : std_logic_vector(4 downto 0) := "01000";
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46 constant ALU_EOR : std_logic_vector(4 downto 0) := "01001";
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47 constant ALU_MV_16 : std_logic_vector(4 downto 0) := "01010";
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48 constant ALU_INC : std_logic_vector(4 downto 0) := "01011";
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49 constant ALU_INTR : std_logic_vector(4 downto 0) := "01100";
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50 constant ALU_LSR : std_logic_vector(4 downto 0) := "01101";
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51 constant ALU_D_MV_Q : std_logic_vector(4 downto 0) := "01110";
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52 constant ALU_R_MV_Q : std_logic_vector(4 downto 0) := "01111";
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53 constant ALU_MULT : std_logic_vector(4 downto 0) := "10000";
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54 constant ALU_NEG : std_logic_vector(4 downto 0) := "10001";
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55 constant ALU_OR : std_logic_vector(4 downto 0) := "10010";
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56 constant ALU_PC_1 : std_logic_vector(4 downto 0) := "10011";
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57 constant ALU_PC_2 : std_logic_vector(4 downto 0) := "10100";
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58 constant ALU_ROR : std_logic_vector(4 downto 0) := "10101";
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59 constant ALU_SBC : std_logic_vector(4 downto 0) := "10110";
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60 constant ALU_SBIW : std_logic_vector(4 downto 0) := "10111";
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61 constant ALU_SREG : std_logic_vector(4 downto 0) := "11000";
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62 constant ALU_SUB : std_logic_vector(4 downto 0) := "11001";
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63 constant ALU_SWAP : std_logic_vector(4 downto 0) := "11010";
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64
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65 -----------------------------------------------------------------------
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66 --
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67 -- PC manipulations
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68 --
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69 constant PC_NEXT : std_logic_vector(2 downto 0) := "000"; -- PC += 1
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70 constant PC_BCC : std_logic_vector(2 downto 0) := "001"; -- PC ?= IMM
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71 constant PC_LD_I : std_logic_vector(2 downto 0) := "010"; -- PC = IMM
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72 constant PC_LD_Z : std_logic_vector(2 downto 0) := "011"; -- PC = Z
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73 constant PC_LD_S : std_logic_vector(2 downto 0) := "100"; -- PC = (SP)
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74 constant PC_SKIP_Z : std_logic_vector(2 downto 0) := "101"; -- SKIP if Z
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75 constant PC_SKIP_T : std_logic_vector(2 downto 0) := "110"; -- SKIP if T
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76
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77 -----------------------------------------------------------------------
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78 --
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79 -- Addressing modes. An address mode consists of two sub-fields,
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80 -- which are the source of the address and an offset from the source.
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81 -- Bit 3 indicates if the address will be modified.
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82
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83 -- address source
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84 constant AS_SP : std_logic_vector(2 downto 0) := "000"; -- SP
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85 constant AS_Z : std_logic_vector(2 downto 0) := "001"; -- Z
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86 constant AS_Y : std_logic_vector(2 downto 0) := "010"; -- Y
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87 constant AS_X : std_logic_vector(2 downto 0) := "011"; -- X
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88 constant AS_IMM : std_logic_vector(2 downto 0) := "100"; -- IMM
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89
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90 -- address offset
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91 constant AO_0 : std_logic_vector(5 downto 3) := "000"; -- as is
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92 constant AO_Q : std_logic_vector(5 downto 3) := "010"; -- +q
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93 constant AO_i : std_logic_vector(5 downto 3) := "001"; -- +1
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94 constant AO_ii : std_logic_vector(5 downto 3) := "011"; -- +2
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95 constant AO_d : std_logic_vector(5 downto 3) := "101"; -- -1
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96 constant AO_dd : std_logic_vector(5 downto 3) := "111"; -- -2
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97 -- |
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98 -- +--+
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99 -- address updated ? |
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100 -- v
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101 constant AM_WX : std_logic_vector(3 downto 0) := '1' & AS_X; -- X ++ or --
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102 constant AM_WY : std_logic_vector(3 downto 0) := '1' & AS_Y; -- Y ++ or --
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103 constant AM_WZ : std_logic_vector(3 downto 0) := '1' & AS_Z; -- Z ++ or --
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104 constant AM_WS : std_logic_vector(3 downto 0) := '1' & AS_SP; -- SP ++/--
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105
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106 -- address modes used
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107 --
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108 constant AMOD_ABS : std_logic_vector(5 downto 0) := AO_0 & AS_IMM; -- IMM
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109 constant AMOD_X : std_logic_vector(5 downto 0) := AO_0 & AS_X; -- (X)
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110 constant AMOD_Xq : std_logic_vector(5 downto 0) := AO_Q & AS_X; -- (X+q)
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111 constant AMOD_Xi : std_logic_vector(5 downto 0) := AO_i & AS_X; -- (X++)
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112 constant AMOD_dX : std_logic_vector(5 downto 0) := AO_d & AS_X; -- (--X)
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113 constant AMOD_Y : std_logic_vector(5 downto 0) := AO_0 & AS_Y; -- (Y)
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114 constant AMOD_Yq : std_logic_vector(5 downto 0) := AO_Q & AS_Y; -- (Y+q)
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115 constant AMOD_Yi : std_logic_vector(5 downto 0) := AO_i & AS_Y; -- (Y++)
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116 constant AMOD_dY : std_logic_vector(5 downto 0) := AO_d & AS_Y; -- (--Y)
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117 constant AMOD_Z : std_logic_vector(5 downto 0) := AO_0 & AS_Z; -- (Z)
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118 constant AMOD_Zq : std_logic_vector(5 downto 0) := AO_Q & AS_Z; -- (Z+q)
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119 constant AMOD_Zi : std_logic_vector(5 downto 0) := AO_i & AS_Z; -- (Z++)
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120 constant AMOD_dZ : std_logic_vector(5 downto 0) := AO_d & AS_Z; -- (--Z)
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121 constant AMOD_SPi : std_logic_vector(5 downto 0) := AO_i & AS_SP; -- (SP++)
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122 constant AMOD_SPii: std_logic_vector(5 downto 0) := AO_ii & AS_SP; -- (SP++)
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123 constant AMOD_dSP : std_logic_vector(5 downto 0) := AO_d & AS_SP; -- (--SP)
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124 constant AMOD_ddSP: std_logic_vector(5 downto 0) := AO_dd & AS_SP; -- (--SP)
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125
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126 -----------------------------------------------------------------------
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127
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128 -- Stack pointer manipulations.
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129 --
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130 constant SP_NOP : std_logic_vector(2 downto 0) := "000";
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131 constant SP_ADD1: std_logic_vector(2 downto 0) := "001";
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132 constant SP_ADD2: std_logic_vector(2 downto 0) := "010";
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133 constant SP_SUB1: std_logic_vector(2 downto 0) := "011";
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134 constant SP_SUB2: std_logic_vector(2 downto 0) := "100";
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135
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136 -----------------------------------------------------------------------
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137 --
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138 -- ALU multiplexers.
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139 --
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140 constant RS_REG : std_logic_vector(1 downto 0) := "00";
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141 constant RS_IMM : std_logic_vector(1 downto 0) := "01";
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142 constant RS_DIN : std_logic_vector(1 downto 0) := "10";
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143
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144 -----------------------------------------------------------------------
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145 --
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146 -- Multiplier variants. F means FMULT (as opposed to MULT).
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147 -- S and U means signed vs. unsigned operands.
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148 --
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149 constant MULT_UU : std_logic_vector(2 downto 0) := "000";
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150 constant MULT_SU : std_logic_vector(2 downto 0) := "010";
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151 constant MULT_SS : std_logic_vector(2 downto 0) := "011";
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152 constant MULT_FUU : std_logic_vector(2 downto 0) := "100";
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153 constant MULT_FSU : std_logic_vector(2 downto 0) := "110";
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154 constant MULT_FSS : std_logic_vector(2 downto 0) := "111";
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155
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156 -----------------------------------------------------------------------
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157
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158 end common;
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<pre class="filename">
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src/common.vhd
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</pre></pre>
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<P>
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<P><hr><BR>
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<table class="ttop"><th class="tpre"><a href="12_Listing_of_baudgen.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="14_Listing_of_cpu_core.vhd.html">Next Lesson</a></th></table>
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