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jsauermann |
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<P><table class="ttop"><th class="tpre"><a href="13_Listing_of_common.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="15_Listing_of_data_mem.vhd.html">Next Lesson</a></th></table>
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<H1><A NAME="section_1">14 LISTING OF cpu_core.vhd</A></H1>
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<pre class="vhdl">
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1 -------------------------------------------------------------------------------
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2 --
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3 -- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
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4 --
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5 -- This code is free software: you can redistribute it and/or modify
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6 -- it under the terms of the GNU General Public License as published by
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7 -- the Free Software Foundation, either version 3 of the License, or
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8 -- (at your option) any later version.
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9 --
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10 -- This code is distributed in the hope that it will be useful,
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11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
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12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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13 -- GNU General Public License for more details.
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14 --
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15 -- You should have received a copy of the GNU General Public License
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16 -- along with this code (see the file named COPYING).
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17 -- If not, see http://www.gnu.org/licenses/.
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18 --
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19 -------------------------------------------------------------------------------
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20 -------------------------------------------------------------------------------
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21 --
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22 -- Module Name: cpu_core - Behavioral
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23 -- Create Date: 13:51:24 11/07/2009
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24 -- Description: the instruction set implementation of a CPU.
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25 --
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26 -------------------------------------------------------------------------------
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27 --
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28 library IEEE;
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29 use IEEE.STD_LOGIC_1164.ALL;
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30 use IEEE.STD_LOGIC_ARITH.ALL;
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31 use IEEE.STD_LOGIC_UNSIGNED.ALL;
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32
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33 entity cpu_core is
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34 port ( I_CLK : in std_logic;
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35 I_CLR : in std_logic;
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36 I_INTVEC : in std_logic_vector( 5 downto 0);
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37 I_DIN : in std_logic_vector( 7 downto 0);
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38
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39 Q_OPC : out std_logic_vector(15 downto 0);
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40 Q_PC : out std_logic_vector(15 downto 0);
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41 Q_DOUT : out std_logic_vector( 7 downto 0);
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42 Q_ADR_IO : out std_logic_vector( 7 downto 0);
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43 Q_RD_IO : out std_logic;
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44 Q_WE_IO : out std_logic);
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45 end cpu_core;
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46
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47 architecture Behavioral of cpu_core is
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48
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49 component opc_fetch
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50 port( I_CLK : in std_logic;
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51
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52 I_CLR : in std_logic;
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53 I_INTVEC : in std_logic_vector( 5 downto 0);
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54 I_NEW_PC : in std_logic_vector(15 downto 0);
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55 I_LOAD_PC : in std_logic;
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56 I_PM_ADR : in std_logic_vector(11 downto 0);
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57 I_SKIP : in std_logic;
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58
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59 Q_OPC : out std_logic_vector(31 downto 0);
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60 Q_PC : out std_logic_vector(15 downto 0);
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61 Q_PM_DOUT : out std_logic_vector( 7 downto 0);
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62 Q_T0 : out std_logic);
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63 end component;
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64
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65 signal F_PC : std_logic_vector(15 downto 0);
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66 signal F_OPC : std_logic_vector(31 downto 0);
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67 signal F_PM_DOUT : std_logic_vector( 7 downto 0);
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68 signal F_T0 : std_logic;
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69
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70 component opc_deco is
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71 port ( I_CLK : in std_logic;
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72
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73 I_OPC : in std_logic_vector(31 downto 0);
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74 I_PC : in std_logic_vector(15 downto 0);
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75 I_T0 : in std_logic;
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76
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77 Q_ALU_OP : out std_logic_vector( 4 downto 0);
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78 Q_AMOD : out std_logic_vector( 5 downto 0);
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79 Q_BIT : out std_logic_vector( 3 downto 0);
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80 Q_DDDDD : out std_logic_vector( 4 downto 0);
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81 Q_IMM : out std_logic_vector(15 downto 0);
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82 Q_JADR : out std_logic_vector(15 downto 0);
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83 Q_OPC : out std_logic_vector(15 downto 0);
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84 Q_PC : out std_logic_vector(15 downto 0);
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85 Q_PC_OP : out std_logic_vector( 2 downto 0);
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86 Q_PMS : out std_logic; -- program memory select
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87 Q_RD_M : out std_logic;
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88 Q_RRRRR : out std_logic_vector( 4 downto 0);
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89 Q_RSEL : out std_logic_vector( 1 downto 0);
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90 Q_WE_01 : out std_logic;
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91 Q_WE_D : out std_logic_vector( 1 downto 0);
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92 Q_WE_F : out std_logic;
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93 Q_WE_M : out std_logic_vector( 1 downto 0);
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94 Q_WE_XYZS : out std_logic);
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95 end component;
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96
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97 signal D_ALU_OP : std_logic_vector( 4 downto 0);
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98 signal D_AMOD : std_logic_vector( 5 downto 0);
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99 signal D_BIT : std_logic_vector( 3 downto 0);
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100 signal D_DDDDD : std_logic_vector( 4 downto 0);
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101 signal D_IMM : std_logic_vector(15 downto 0);
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102 signal D_JADR : std_logic_vector(15 downto 0);
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103 signal D_OPC : std_logic_vector(15 downto 0);
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104 signal D_PC : std_logic_vector(15 downto 0);
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105 signal D_PC_OP : std_logic_vector(2 downto 0);
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106 signal D_PMS : std_logic;
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107 signal D_RD_M : std_logic;
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108 signal D_RRRRR : std_logic_vector( 4 downto 0);
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109 signal D_RSEL : std_logic_vector( 1 downto 0);
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110 signal D_WE_01 : std_logic;
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111 signal D_WE_D : std_logic_vector( 1 downto 0);
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112 signal D_WE_F : std_logic;
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113 signal D_WE_M : std_logic_vector( 1 downto 0);
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114 signal D_WE_XYZS : std_logic;
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115
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116 component data_path
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117 port( I_CLK : in std_logic;
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118
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119 I_ALU_OP : in std_logic_vector( 4 downto 0);
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120 I_AMOD : in std_logic_vector( 5 downto 0);
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121 I_BIT : in std_logic_vector( 3 downto 0);
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122 I_DDDDD : in std_logic_vector( 4 downto 0);
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123 I_DIN : in std_logic_vector( 7 downto 0);
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124 I_IMM : in std_logic_vector(15 downto 0);
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125 I_JADR : in std_logic_vector(15 downto 0);
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126 I_PC_OP : in std_logic_vector( 2 downto 0);
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127 I_OPC : in std_logic_vector(15 downto 0);
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128 I_PC : in std_logic_vector(15 downto 0);
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129 I_PMS : in std_logic; -- program memory select
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130 I_RD_M : in std_logic;
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131 I_RRRRR : in std_logic_vector( 4 downto 0);
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132 I_RSEL : in std_logic_vector( 1 downto 0);
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133 I_WE_01 : in std_logic;
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134 I_WE_D : in std_logic_vector( 1 downto 0);
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135 I_WE_F : in std_logic;
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136 I_WE_M : in std_logic_vector( 1 downto 0);
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137 I_WE_XYZS : in std_logic;
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138
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139 Q_ADR : out std_logic_vector(15 downto 0);
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140 Q_DOUT : out std_logic_vector( 7 downto 0);
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141 Q_INT_ENA : out std_logic;
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142 Q_LOAD_PC : out std_logic;
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143 Q_NEW_PC : out std_logic_vector(15 downto 0);
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144 Q_OPC : out std_logic_vector(15 downto 0);
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145 Q_PC : out std_logic_vector(15 downto 0);
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146 Q_RD_IO : out std_logic;
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147 Q_SKIP : out std_logic;
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148 Q_WE_IO : out std_logic);
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149 end component;
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150
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151 signal R_INT_ENA : std_logic;
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152 signal R_NEW_PC : std_logic_vector(15 downto 0);
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153 signal R_LOAD_PC : std_logic;
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154 signal R_SKIP : std_logic;
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155 signal R_ADR : std_logic_vector(15 downto 0);
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156
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157 -- local signals
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158 --
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159 signal L_DIN : std_logic_vector( 7 downto 0);
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160 signal L_INTVEC_5 : std_logic;
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161
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162 begin
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163
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164 opcf : opc_fetch
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165 port map( I_CLK => I_CLK,
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166
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167 I_CLR => I_CLR,
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168 I_INTVEC(5) => L_INTVEC_5,
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169 I_INTVEC(4 downto 0) => I_INTVEC(4 downto 0),
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170 I_LOAD_PC => R_LOAD_PC,
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171 I_NEW_PC => R_NEW_PC,
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172 I_PM_ADR => R_ADR(11 downto 0),
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173 I_SKIP => R_SKIP,
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174
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175 Q_PC => F_PC,
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176 Q_OPC => F_OPC,
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177 Q_T0 => F_T0,
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178 Q_PM_DOUT => F_PM_DOUT);
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179
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180 odec : opc_deco
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181 port map( I_CLK => I_CLK,
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182
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183 I_OPC => F_OPC,
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184 I_PC => F_PC,
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185 I_T0 => F_T0,
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186
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187 Q_ALU_OP => D_ALU_OP,
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188 Q_AMOD => D_AMOD,
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189 Q_BIT => D_BIT,
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190 Q_DDDDD => D_DDDDD,
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191 Q_IMM => D_IMM,
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192 Q_JADR => D_JADR,
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193 Q_OPC => D_OPC,
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194 Q_PC => D_PC,
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195 Q_PC_OP => D_PC_OP,
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196 Q_PMS => D_PMS,
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197 Q_RD_M => D_RD_M,
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198 Q_RRRRR => D_RRRRR,
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199 Q_RSEL => D_RSEL,
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200 Q_WE_01 => D_WE_01,
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201 Q_WE_D => D_WE_D,
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202 Q_WE_F => D_WE_F,
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203 Q_WE_M => D_WE_M,
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204 Q_WE_XYZS => D_WE_XYZS);
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205
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206 dpath : data_path
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207 port map( I_CLK => I_CLK,
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208
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209 I_ALU_OP => D_ALU_OP,
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210 I_AMOD => D_AMOD,
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211 I_BIT => D_BIT,
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212 I_DDDDD => D_DDDDD,
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213 I_DIN => L_DIN,
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214 I_IMM => D_IMM,
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215 I_JADR => D_JADR,
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216 I_OPC => D_OPC,
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217 I_PC => D_PC,
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218 I_PC_OP => D_PC_OP,
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219 I_PMS => D_PMS,
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220 I_RD_M => D_RD_M,
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221 I_RRRRR => D_RRRRR,
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222 I_RSEL => D_RSEL,
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223 I_WE_01 => D_WE_01,
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224 I_WE_D => D_WE_D,
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225 I_WE_F => D_WE_F,
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226 I_WE_M => D_WE_M,
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227 I_WE_XYZS => D_WE_XYZS,
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228
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229 Q_ADR => R_ADR,
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230 Q_DOUT => Q_DOUT,
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231 Q_INT_ENA => R_INT_ENA,
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232 Q_NEW_PC => R_NEW_PC,
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233 Q_OPC => Q_OPC,
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234 Q_PC => Q_PC,
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235 Q_LOAD_PC => R_LOAD_PC,
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236 Q_RD_IO => Q_RD_IO,
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237 Q_SKIP => R_SKIP,
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238 Q_WE_IO => Q_WE_IO);
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239
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240 L_DIN <= F_PM_DOUT when (D_PMS = '1') else I_DIN(7 downto 0);
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241 L_INTVEC_5 <= I_INTVEC(5) and R_INT_ENA;
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242 Q_ADR_IO <= R_ADR(7 downto 0);
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243
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244 end Behavioral;
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245
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<pre class="filename">
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src/cpu_core.vhd
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</pre></pre>
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<P>
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<P><hr><BR>
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<table class="ttop"><th class="tpre"><a href="13_Listing_of_common.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="15_Listing_of_data_mem.vhd.html">Next Lesson</a></th></table>
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