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jsauermann |
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<P><table class="ttop"><th class="tpre"><a href="14_Listing_of_cpu_core.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="16_Listing_of_data_path.vhd.html">Next Lesson</a></th></table>
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<H1><A NAME="section_1">15 LISTING OF data_mem.vhd</A></H1>
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<pre class="vhdl">
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1 -------------------------------------------------------------------------------
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2 --
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3 -- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
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4 --
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5 -- This code is free software: you can redistribute it and/or modify
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6 -- it under the terms of the GNU General Public License as published by
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7 -- the Free Software Foundation, either version 3 of the License, or
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8 -- (at your option) any later version.
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9 --
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10 -- This code is distributed in the hope that it will be useful,
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11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
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12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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13 -- GNU General Public License for more details.
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14 --
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15 -- You should have received a copy of the GNU General Public License
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16 -- along with this code (see the file named COPYING).
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17 -- If not, see http://www.gnu.org/licenses/.
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18 --
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19 -------------------------------------------------------------------------------
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20 -------------------------------------------------------------------------------
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21 --
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22 -- Module Name: data_mem - Behavioral
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23 -- Create Date: 14:09:04 10/30/2009
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24 -- Description: the data mempry of a CPU.
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25 --
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26 -------------------------------------------------------------------------------
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27 --
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28 library IEEE;
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29 use IEEE.STD_LOGIC_1164.ALL;
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30 use IEEE.STD_LOGIC_ARITH.ALL;
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31 use IEEE.STD_LOGIC_UNSIGNED.ALL;
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32
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33 ---- Uncomment the following library declaration if instantiating
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34 ---- any Xilinx primitives in this code.
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35 -- library UNISIM;
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36 -- use UNISIM.VComponents.all;
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37
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38 entity data_mem is
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39 port ( I_CLK : in std_logic;
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40
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41 I_ADR : in std_logic_vector(10 downto 0);
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42 I_DIN : in std_logic_vector(15 downto 0);
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43 I_WE : in std_logic_vector( 1 downto 0);
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44
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45 Q_DOUT : out std_logic_vector(15 downto 0));
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46 end data_mem;
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47
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48 architecture Behavioral of data_mem is
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49
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50 constant zero_256 : bit_vector := X"00000000000000000000000000000000"
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51 & X"00000000000000000000000000000000";
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52 constant nine_256 : bit_vector := X"99999999999999999999999999999999"
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53 & X"99999999999999999999999999999999";
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54
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55 component RAMB4_S4_S4
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56 generic(INIT_00 : bit_vector := zero_256;
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57 INIT_01 : bit_vector := zero_256;
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58 INIT_02 : bit_vector := zero_256;
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59 INIT_03 : bit_vector := zero_256;
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60 INIT_04 : bit_vector := zero_256;
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61 INIT_05 : bit_vector := zero_256;
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62 INIT_06 : bit_vector := zero_256;
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63 INIT_07 : bit_vector := zero_256;
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64 INIT_08 : bit_vector := zero_256;
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65 INIT_09 : bit_vector := zero_256;
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66 INIT_0A : bit_vector := zero_256;
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67 INIT_0B : bit_vector := zero_256;
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68 INIT_0C : bit_vector := zero_256;
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69 INIT_0D : bit_vector := zero_256;
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70 INIT_0E : bit_vector := zero_256;
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71 INIT_0F : bit_vector := zero_256);
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72
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73 port( DOA : out std_logic_vector(3 downto 0);
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74 DOB : out std_logic_vector(3 downto 0);
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75 ADDRA : in std_logic_vector(9 downto 0);
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76 ADDRB : in std_logic_vector(9 downto 0);
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77 CLKA : in std_ulogic;
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78 CLKB : in std_ulogic;
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79 DIA : in std_logic_vector(3 downto 0);
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80 DIB : in std_logic_vector(3 downto 0);
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81 ENA : in std_ulogic;
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82 ENB : in std_ulogic;
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83 RSTA : in std_ulogic;
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84 RSTB : in std_ulogic;
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85 WEA : in std_ulogic;
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86 WEB : in std_ulogic);
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87 end component;
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88
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89 signal L_ADR_0 : std_logic;
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90 signal L_ADR_E : std_logic_vector(10 downto 1);
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91 signal L_ADR_O : std_logic_vector(10 downto 1);
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92 signal L_DIN_E : std_logic_vector( 7 downto 0);
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93 signal L_DIN_O : std_logic_vector( 7 downto 0);
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94 signal L_DOUT_E : std_logic_vector( 7 downto 0);
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95 signal L_DOUT_O : std_logic_vector( 7 downto 0);
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96 signal L_WE_E : std_logic;
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97 signal L_WE_O : std_logic;
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98
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99 begin
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100
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101 sr_0 : RAMB4_S4_S4 ---------------------------------------------------------
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102 generic map(INIT_00 => nine_256, INIT_01 => nine_256, INIT_02 => nine_256,
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103 INIT_03 => nine_256, INIT_04 => nine_256, INIT_05 => nine_256,
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104 INIT_06 => nine_256, INIT_07 => nine_256, INIT_08 => nine_256,
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105 INIT_09 => nine_256, INIT_0A => nine_256, INIT_0B => nine_256,
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106 INIT_0C => nine_256, INIT_0D => nine_256, INIT_0E => nine_256,
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107 INIT_0F => nine_256)
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108
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109 port map( ADDRA => L_ADR_E, ADDRB => "0000000000",
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110 CLKA => I_CLK, CLKB => I_CLK,
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111 DIA => L_DIN_E(3 downto 0), DIB => "0000",
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112 ENA => '1', ENB => '0',
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113 RSTA => '0', RSTB => '0',
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114 WEA => L_WE_E, WEB => '0',
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115 DOA => L_DOUT_E(3 downto 0), DOB => open);
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116
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117 sr_1 : RAMB4_S4_S4 ---------------------------------------------------------
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118 generic map(INIT_00 => nine_256, INIT_01 => nine_256, INIT_02 => nine_256,
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119 INIT_03 => nine_256, INIT_04 => nine_256, INIT_05 => nine_256,
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120 INIT_06 => nine_256, INIT_07 => nine_256, INIT_08 => nine_256,
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121 INIT_09 => nine_256, INIT_0A => nine_256, INIT_0B => nine_256,
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122 INIT_0C => nine_256, INIT_0D => nine_256, INIT_0E => nine_256,
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123 INIT_0F => nine_256)
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124
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125 port map( ADDRA => L_ADR_E, ADDRB => "0000000000",
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126 CLKA => I_CLK, CLKB => I_CLK,
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127 DIA => L_DIN_E(7 downto 4), DIB => "0000",
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128 ENA => '1', ENB => '0',
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129 RSTA => '0', RSTB => '0',
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130 WEA => L_WE_E, WEB => '0',
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131 DOA => L_DOUT_E(7 downto 4), DOB => open);
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132
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133 sr_2 : RAMB4_S4_S4 ---------------------------------------------------------
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134 generic map(INIT_00 => nine_256, INIT_01 => nine_256, INIT_02 => nine_256,
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135 INIT_03 => nine_256, INIT_04 => nine_256, INIT_05 => nine_256,
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136 INIT_06 => nine_256, INIT_07 => nine_256, INIT_08 => nine_256,
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137 INIT_09 => nine_256, INIT_0A => nine_256, INIT_0B => nine_256,
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138 INIT_0C => nine_256, INIT_0D => nine_256, INIT_0E => nine_256,
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139 INIT_0F => nine_256)
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140
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141 port map( ADDRA => L_ADR_O, ADDRB => "0000000000",
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142 CLKA => I_CLK, CLKB => I_CLK,
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143 DIA => L_DIN_O(3 downto 0), DIB => "0000",
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144 ENA => '1', ENB => '0',
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145 RSTA => '0', RSTB => '0',
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146 WEA => L_WE_O, WEB => '0',
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147 DOA => L_DOUT_O(3 downto 0), DOB => open);
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148
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149 sr_3 : RAMB4_S4_S4 ---------------------------------------------------------
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150 generic map(INIT_00 => nine_256, INIT_01 => nine_256, INIT_02 => nine_256,
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151 INIT_03 => nine_256, INIT_04 => nine_256, INIT_05 => nine_256,
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152 INIT_06 => nine_256, INIT_07 => nine_256, INIT_08 => nine_256,
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153 INIT_09 => nine_256, INIT_0A => nine_256, INIT_0B => nine_256,
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154 INIT_0C => nine_256, INIT_0D => nine_256, INIT_0E => nine_256,
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155 INIT_0F => nine_256)
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156
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157 port map( ADDRA => L_ADR_O, ADDRB => "0000000000",
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158 CLKA => I_CLK, CLKB => I_CLK,
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159 DIA => L_DIN_O(7 downto 4), DIB => "0000",
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160 ENA => '1', ENB => '0',
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161 RSTA => '0', RSTB => '0',
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162 WEA => L_WE_O, WEB => '0',
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163 DOA => L_DOUT_O(7 downto 4), DOB => open);
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164
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165
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166 -- remember ADR(0)
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167 --
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168 adr0: process(I_CLK)
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169 begin
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170 if (rising_edge(I_CLK)) then
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171 L_ADR_0 <= I_ADR(0);
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172 end if;
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173 end process;
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174
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175 -- we use two memory blocks _E and _O (even and odd).
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176 -- This gives us a memory with ADR and ADR + 1 at th same time.
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177 -- The second port is currently unused, but may be used later,
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178 -- e.g. for DMA.
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179 --
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180
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181 L_ADR_O <= I_ADR(10 downto 1);
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182 L_ADR_E <= I_ADR(10 downto 1) + ("000000000" & I_ADR(0));
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183
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184 L_DIN_E <= I_DIN( 7 downto 0) when (I_ADR(0) = '0') else I_DIN(15 downto 8);
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185 L_DIN_O <= I_DIN( 7 downto 0) when (I_ADR(0) = '1') else I_DIN(15 downto 8);
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186
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187 L_WE_E <= I_WE(1) or (I_WE(0) and not I_ADR(0));
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188 L_WE_O <= I_WE(1) or (I_WE(0) and I_ADR(0));
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189
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190 Q_DOUT( 7 downto 0) <= L_DOUT_E when (L_ADR_0 = '0') else L_DOUT_O;
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191 Q_DOUT(15 downto 8) <= L_DOUT_E when (L_ADR_0 = '1') else L_DOUT_O;
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192
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193 end Behavioral;
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194
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<pre class="filename">
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src/data_mem.vhd
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</pre></pre>
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<P>
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<P><hr><BR>
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<table class="ttop"><th class="tpre"><a href="14_Listing_of_cpu_core.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="16_Listing_of_data_path.vhd.html">Next Lesson</a></th></table>
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