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jsauermann |
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<P><table class="ttop"><th class="tpre"><a href="15_Listing_of_data_mem.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="17_Listing_of_io.vhd.html">Next Lesson</a></th></table>
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<H1><A NAME="section_1">16 LISTING OF data_path.vhd</A></H1>
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<pre class="vhdl">
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1 -------------------------------------------------------------------------------
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2 --
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3 -- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
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4 --
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5 -- This code is free software: you can redistribute it and/or modify
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6 -- it under the terms of the GNU General Public License as published by
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7 -- the Free Software Foundation, either version 3 of the License, or
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8 -- (at your option) any later version.
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9 --
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10 -- This code is distributed in the hope that it will be useful,
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11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
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12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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13 -- GNU General Public License for more details.
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14 --
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15 -- You should have received a copy of the GNU General Public License
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16 -- along with this code (see the file named COPYING).
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17 -- If not, see http://www.gnu.org/licenses/.
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18 --
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19 -------------------------------------------------------------------------------
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20 -------------------------------------------------------------------------------
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21 --
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22 -- Module Name: data_path - Behavioral
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23 -- Create Date: 13:24:10 10/29/2009
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24 -- Description: the data path of a CPU.
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25 --
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26 -------------------------------------------------------------------------------
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27 --
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28 library IEEE;
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29 use IEEE.std_logic_1164.ALL;
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30 use IEEE.std_logic_ARITH.ALL;
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31 use IEEE.std_logic_UNSIGNED.ALL;
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32
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33 use work.common.ALL;
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34
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35 entity data_path is
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36 port( I_CLK : in std_logic;
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37
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38 I_ALU_OP : in std_logic_vector( 4 downto 0);
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39 I_AMOD : in std_logic_vector( 5 downto 0);
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40 I_BIT : in std_logic_vector( 3 downto 0);
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41 I_DDDDD : in std_logic_vector( 4 downto 0);
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42 I_DIN : in std_logic_vector( 7 downto 0);
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43 I_IMM : in std_logic_vector(15 downto 0);
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44 I_JADR : in std_logic_vector(15 downto 0);
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45 I_OPC : in std_logic_vector(15 downto 0);
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46 I_PC : in std_logic_vector(15 downto 0);
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47 I_PC_OP : in std_logic_vector( 2 downto 0);
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48 I_PMS : in std_logic; -- program memory select
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49 I_RD_M : in std_logic;
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50 I_RRRRR : in std_logic_vector( 4 downto 0);
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51 I_RSEL : in std_logic_vector( 1 downto 0);
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52 I_WE_01 : in std_logic;
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53 I_WE_D : in std_logic_vector( 1 downto 0);
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54 I_WE_F : in std_logic;
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55 I_WE_M : in std_logic_vector( 1 downto 0);
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56 I_WE_XYZS : in std_logic;
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57
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58 Q_ADR : out std_logic_vector(15 downto 0);
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59 Q_DOUT : out std_logic_vector( 7 downto 0);
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60 Q_INT_ENA : out std_logic;
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61 Q_LOAD_PC : out std_logic;
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62 Q_NEW_PC : out std_logic_vector(15 downto 0);
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63 Q_OPC : out std_logic_vector(15 downto 0);
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64 Q_PC : out std_logic_vector(15 downto 0);
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65 Q_RD_IO : out std_logic;
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66 Q_SKIP : out std_logic;
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67 Q_WE_IO : out std_logic);
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68 end data_path;
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69
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70 architecture Behavioral of data_path is
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71
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72 component alu
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73 port ( I_ALU_OP : in std_logic_vector( 4 downto 0);
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74 I_BIT : in std_logic_vector( 3 downto 0);
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75 I_D : in std_logic_vector(15 downto 0);
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76 I_D0 : in std_logic;
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77 I_DIN : in std_logic_vector( 7 downto 0);
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78 I_FLAGS : in std_logic_vector( 7 downto 0);
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79 I_IMM : in std_logic_vector( 7 downto 0);
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80 I_PC : in std_logic_vector(15 downto 0);
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81 I_R : in std_logic_vector(15 downto 0);
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82 I_R0 : in std_logic;
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83 I_RSEL : in std_logic_vector( 1 downto 0);
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84
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85 Q_FLAGS : out std_logic_vector( 9 downto 0);
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86 Q_DOUT : out std_logic_vector(15 downto 0));
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87 end component;
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88
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89 signal A_DOUT : std_logic_vector(15 downto 0);
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90 signal A_FLAGS : std_logic_vector( 9 downto 0);
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91
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92 component register_file
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93 port ( I_CLK : in std_logic;
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94
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95 I_AMOD : in std_logic_vector( 5 downto 0);
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96 I_COND : in std_logic_vector( 3 downto 0);
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97 I_DDDDD : in std_logic_vector( 4 downto 0);
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98 I_DIN : in std_logic_vector(15 downto 0);
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99 I_FLAGS : in std_logic_vector( 7 downto 0);
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100 I_IMM : in std_logic_vector(15 downto 0);
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101 I_RRRR : in std_logic_vector( 4 downto 1);
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102 I_WE_01 : in std_logic;
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103 I_WE_D : in std_logic_vector( 1 downto 0);
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104 I_WE_F : in std_logic;
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105 I_WE_M : in std_logic;
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106 I_WE_XYZS : in std_logic;
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107
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108 Q_ADR : out std_logic_vector(15 downto 0);
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109 Q_CC : out std_logic;
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110 Q_D : out std_logic_vector(15 downto 0);
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111 Q_FLAGS : out std_logic_vector( 7 downto 0);
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112 Q_R : out std_logic_vector(15 downto 0);
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113 Q_S : out std_logic_vector( 7 downto 0);
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114 Q_Z : out std_logic_vector(15 downto 0));
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115 end component;
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116
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117 signal F_ADR : std_logic_vector(15 downto 0);
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118 signal F_CC : std_logic;
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119 signal F_D : std_logic_vector(15 downto 0);
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120 signal F_FLAGS : std_logic_vector( 7 downto 0);
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121 signal F_R : std_logic_vector(15 downto 0);
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122 signal F_S : std_logic_vector( 7 downto 0);
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123 signal F_Z : std_logic_vector(15 downto 0);
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124
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125 component data_mem
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126 port ( I_CLK : in std_logic;
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127
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128 I_ADR : in std_logic_vector(10 downto 0);
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129 I_DIN : in std_logic_vector(15 downto 0);
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130 I_WE : in std_logic_vector( 1 downto 0);
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131
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132 Q_DOUT : out std_logic_vector(15 downto 0));
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133 end component;
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134
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135 signal M_DOUT : std_logic_vector(15 downto 0);
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136
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137 signal L_DIN : std_logic_vector( 7 downto 0);
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138 signal L_WE_SRAM : std_logic_vector( 1 downto 0);
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139 signal L_FLAGS_98 : std_logic_vector( 9 downto 8);
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140
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141 begin
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142
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143 alui : alu
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144 port map( I_ALU_OP => I_ALU_OP,
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145 I_BIT => I_BIT,
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146 I_D => F_D,
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147 I_D0 => I_DDDDD(0),
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148 I_DIN => L_DIN,
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149 I_FLAGS => F_FLAGS,
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150 I_IMM => I_IMM(7 downto 0),
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151 I_PC => I_PC,
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152 I_R => F_R,
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153 I_R0 => I_RRRRR(0),
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154 I_RSEL => I_RSEL,
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155
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156 Q_FLAGS => A_FLAGS,
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157 Q_DOUT => A_DOUT);
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158
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159 regs : register_file
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160 port map( I_CLK => I_CLK,
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161
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162 I_AMOD => I_AMOD,
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163 I_COND(3) => I_OPC(10),
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164 I_COND(2 downto 0)=> I_OPC(2 downto 0),
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165 I_DDDDD => I_DDDDD,
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166 I_DIN => A_DOUT,
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167 I_FLAGS => A_FLAGS(7 downto 0),
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168 I_IMM => I_IMM,
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169 I_RRRR => I_RRRRR(4 downto 1),
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170 I_WE_01 => I_WE_01,
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171 I_WE_D => I_WE_D,
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172 I_WE_F => I_WE_F,
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173 I_WE_M => I_WE_M(0),
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174 I_WE_XYZS => I_WE_XYZS,
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175
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176 Q_ADR => F_ADR,
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177 Q_CC => F_CC,
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178 Q_D => F_D,
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179 Q_FLAGS => F_FLAGS,
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180 Q_R => F_R,
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181 Q_S => F_S, -- Q_Rxx(F_ADR)
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182 Q_Z => F_Z);
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183
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184 sram : data_mem
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185 port map( I_CLK => I_CLK,
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186
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187 I_ADR => F_ADR(10 downto 0),
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188 I_DIN => A_DOUT,
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189 I_WE => L_WE_SRAM,
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190
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191 Q_DOUT => M_DOUT);
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192
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193 -- remember A_FLAGS(9 downto 8) (within the current instruction).
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194 --
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195 flg98: process(I_CLK)
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196 begin
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197 if (rising_edge(I_CLK)) then
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198 L_FLAGS_98 <= A_FLAGS(9 downto 8);
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199 end if;
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200 end process;
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201
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202 -- whether PC shall be loaded with NEW_PC or not.
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203 -- I.e. if a branch shall be taken or not.
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204 --
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205 process(I_PC_OP, F_CC)
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206 begin
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207 case I_PC_OP is
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208 when PC_BCC => Q_LOAD_PC <= F_CC; -- maybe (PC on I_JADR)
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209 when PC_LD_I => Q_LOAD_PC <= '1'; -- yes: new PC on I_JADR
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210 when PC_LD_Z => Q_LOAD_PC <= '1'; -- yes: new PC in Z
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211 when PC_LD_S => Q_LOAD_PC <= '1'; -- yes: new PC on stack
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212 when others => Q_LOAD_PC <= '0'; -- no.
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213 end case;
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214 end process;
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215
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216 -- whether the next instruction shall be skipped or not.
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217 --
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218 process(I_PC_OP, L_FLAGS_98, F_CC)
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219 begin
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220 case I_PC_OP is
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221 when PC_BCC => Q_SKIP <= F_CC; -- if cond met
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222 when PC_LD_I => Q_SKIP <= '1'; -- yes
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223 when PC_LD_Z => Q_SKIP <= '1'; -- yes
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224 when PC_LD_S => Q_SKIP <= '1'; -- yes
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225 when PC_SKIP_Z => Q_SKIP <= L_FLAGS_98(8); -- if Z set
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226 when PC_SKIP_T => Q_SKIP <= L_FLAGS_98(9); -- if T set
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227 when others => Q_SKIP <= '0'; -- no.
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228 end case;
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229 end process;
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230
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231 Q_ADR <= F_ADR;
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232 Q_DOUT <= A_DOUT(7 downto 0);
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233 Q_INT_ENA <= A_FLAGS(7);
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234 Q_OPC <= I_OPC;
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235 Q_PC <= I_PC;
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236
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237 Q_RD_IO <= '0' when (F_ADR < X"20")
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238 else (I_RD_M and not I_PMS) when (F_ADR < X"5D")
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239 else '0';
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240 Q_WE_IO <= '0' when (F_ADR < X"20")
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241 else I_WE_M(0) when (F_ADR < X"5D")
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242 else '0';
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243 L_WE_SRAM <= "00" when (F_ADR < X"0060") else I_WE_M;
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244 L_DIN <= I_DIN when (I_PMS = '1')
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245 else F_S when (F_ADR < X"0020")
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246 else I_DIN when (F_ADR < X"005D")
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247 else F_S when (F_ADR < X"0060")
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248 else M_DOUT(7 downto 0);
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249
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250 -- compute potential new PC value from Z, (SP), or IMM.
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251 --
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252 Q_NEW_PC <= F_Z when I_PC_OP = PC_LD_Z -- IJMP, ICALL
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253 else M_DOUT when I_PC_OP = PC_LD_S -- RET, RETI
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254 else I_JADR; -- JMP adr
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255
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256 end Behavioral;
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257
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<pre class="filename">
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src/data_path.vhd
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</pre></pre>
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<P>
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<P><hr><BR>
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<table class="ttop"><th class="tpre"><a href="15_Listing_of_data_mem.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="17_Listing_of_io.vhd.html">Next Lesson</a></th></table>
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