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<P><table class="ttop"><th class="tpre"><a href="25_Listing_of_status_reg.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="27_Listing_of_uart_tx.vhd.html">Next Lesson</a></th></table>
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<H1><A NAME="section_1">26 LISTING OF uart_rx.vhd</A></H1>
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<pre class="vhdl">
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1 -------------------------------------------------------------------------------
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2 --
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3 -- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
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4 --
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5 -- This code is free software: you can redistribute it and/or modify
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6 -- it under the terms of the GNU General Public License as published by
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7 -- the Free Software Foundation, either version 3 of the License, or
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8 -- (at your option) any later version.
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9 --
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10 -- This code is distributed in the hope that it will be useful,
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11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
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12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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13 -- GNU General Public License for more details.
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14 --
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15 -- You should have received a copy of the GNU General Public License
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16 -- along with this code (see the file named COPYING).
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17 -- If not, see http://www.gnu.org/licenses/.
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18 --
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19 -------------------------------------------------------------------------------
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20 -------------------------------------------------------------------------------
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21 --
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22 -- Create Date: 14:22:28 11/07/2009
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23 -- Design Name:
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24 -- Module Name: uart_rx - Behavioral
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25 -- Description: a UART receiver.
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26 --
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27 -------------------------------------------------------------------------------
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28 --
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29 library IEEE;
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30 use IEEE.STD_LOGIC_1164.ALL;
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31 use IEEE.STD_LOGIC_ARITH.ALL;
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32 use IEEE.STD_LOGIC_UNSIGNED.ALL;
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33
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34 entity uart_rx is
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35 PORT( I_CLK : in std_logic;
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36 I_CLR : in std_logic;
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37 I_CE_16 : in std_logic; -- 16 times baud rate
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38 I_RX : in std_logic; -- Serial input line
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39
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40 Q_DATA : out std_logic_vector(7 downto 0);
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41 Q_FLAG : out std_logic); -- toggle on every byte received
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42 end uart_rx;
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43
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44 architecture Behavioral of uart_rx is
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45
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46 signal L_POSITION : std_logic_vector(7 downto 0); -- sample position
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47 signal L_BUF : std_logic_vector(9 downto 0);
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48 signal L_FLAG : std_logic;
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49 signal L_SERIN : std_logic; -- double clock the input
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50 signal L_SER_HOT : std_logic; -- double clock the input
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51
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52 begin
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53
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54 -- double clock the input data...
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55 --
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56 process(I_CLK)
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57 begin
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58 if (rising_edge(I_CLK)) then
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59 if (I_CLR = '1') then
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60 L_SERIN <= '1';
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61 L_SER_HOT <= '1';
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62 else
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63 L_SERIN <= I_RX;
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64 L_SER_HOT <= L_SERIN;
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65 end if;
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66 end if;
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67 end process;
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68
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69 process(I_CLK, L_POSITION)
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70 variable START_BIT : boolean;
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71 variable STOP_BIT : boolean;
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72 variable STOP_POS : boolean;
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73
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74 begin
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75 START_BIT := L_POSITION(7 downto 4) = X"0";
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76 STOP_BIT := L_POSITION(7 downto 4) = X"9";
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77 STOP_POS := STOP_BIT and L_POSITION(3 downto 2) = "11"; -- 3/4 of stop bit
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78
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79 if (rising_edge(I_CLK)) then
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80 if (I_CLR = '1') then
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81 L_FLAG <= '0';
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82 L_POSITION <= X"00"; -- idle
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83 L_BUF <= "1111111111";
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84 Q_DATA <= "00000000";
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85 elsif (I_CE_16 = '1') then
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86 if (L_POSITION = X"00") then -- uart idle
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87 L_BUF <= "1111111111";
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88 if (L_SER_HOT = '0') then -- start bit received
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89 L_POSITION <= X"01";
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90 end if;
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91 else
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92 L_POSITION <= L_POSITION + X"01";
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93 if (L_POSITION(3 downto 0) = "0111") then -- 1/2 bit
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94 L_BUF <= L_SER_HOT & L_BUF(9 downto 1); -- sample data
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95 --
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96 -- validate start bit
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97 --
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98 if (START_BIT and L_SER_HOT = '1') then -- 1/2 start bit
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99 L_POSITION <= X"00";
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100 end if;
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101
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102 if (STOP_BIT) then -- 1/2 stop bit
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103 Q_DATA <= L_BUF(9 downto 2);
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104 end if;
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105 elsif (STOP_POS) then -- 3/4 stop bit
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106 L_FLAG <= L_FLAG xor (L_BUF(9) and not L_BUF(0));
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107 L_POSITION <= X"00";
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108 end if;
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109 end if;
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110 end if;
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111 end if;
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112 end process;
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113
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114 Q_FLAG <= L_FLAG;
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115
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116 end Behavioral;
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117
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<pre class="filename">
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src/uart_rx.vhd
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</pre></pre>
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<P>
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<P><hr><BR>
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<table class="ttop"><th class="tpre"><a href="25_Listing_of_status_reg.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="27_Listing_of_uart_tx.vhd.html">Next Lesson</a></th></table>
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