URL
https://opencores.org/ocsvn/cpu_lecture/cpu_lecture/trunk
[/] [cpu_lecture/] [trunk/] [html/] [31_Listing_of_Makefile.html] - Blame information for rev 4
Go to most recent revision |
Details |
Compare with Previous |
View Log
Line No. |
Rev |
Author |
Line |
1 |
2 |
jsauermann |
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN"
|
2 |
|
|
"http://www.w3.org/TR/html4/strict.dtd">
|
3 |
|
|
<HTML>
|
4 |
|
|
<HEAD>
|
5 |
|
|
<TITLE>html/Listing_of_Makefile</TITLE>
|
6 |
|
|
<META NAME="generator" CONTENT="HTML::TextToHTML v2.46">
|
7 |
|
|
<LINK REL="stylesheet" TYPE="text/css" HREF="lecture.css">
|
8 |
|
|
</HEAD>
|
9 |
|
|
<BODY>
|
10 |
|
|
<P><table class="ttop"><th class="tpre"><a href="30_Listing_of_avr_fpga.ucf.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="32_Listing_of_hello.c.html">Next Lesson</a></th></table>
|
11 |
|
|
<hr>
|
12 |
|
|
|
13 |
|
|
<H1><A NAME="section_1">31 LISTING OF Makefile</A></H1>
|
14 |
|
|
|
15 |
|
|
<pre class="vhdl">
|
16 |
|
|
|
17 |
|
|
1 PROJECT=avr_core
|
18 |
|
|
2
|
19 |
|
|
3 # the vhdl source files (except testbench)
|
20 |
|
|
4 #
|
21 |
|
|
5 FILES += src/*.vhd
|
22 |
|
|
6
|
23 |
|
|
7 # the testbench sources and binary.
|
24 |
|
|
8 #
|
25 |
|
|
9 SIMFILES = test/test_tb.vhd test/RAMB4_S4_S4.vhd
|
26 |
|
|
10 SIMTOP = testbench
|
27 |
|
|
11
|
28 |
|
|
12 # When to stop the simulation
|
29 |
|
|
13 #
|
30 |
|
|
14 # GHDL_SIM_OPT = --assert-level=error
|
31 |
|
|
15 GHDL_SIM_OPT = --stop-time=40us
|
32 |
|
|
16
|
33 |
|
|
17 SIMDIR = simu
|
34 |
|
|
18
|
35 |
|
|
19 FLAGS = --ieee=synopsys --warn-no-vital-generic -fexplicit --std=93c
|
36 |
|
|
20
|
37 |
|
|
21 all:
|
38 |
|
|
22 make compile
|
39 |
|
|
23 make run 2>& 1 | grep -v std_logic_arith
|
40 |
|
|
24 make view
|
41 |
|
|
25
|
42 |
|
|
26 compile:
|
43 |
|
|
27 @mkdir -p simu
|
44 |
|
|
28 @echo -----------------------------------------------------------------
|
45 |
|
|
29 ghdl -i $(FLAGS) --workdir=simu --work=work $(SIMFILES) $(FILES)
|
46 |
|
|
30 @echo
|
47 |
|
|
31 @echo -----------------------------------------------------------------
|
48 |
|
|
32 ghdl -m $(FLAGS) --workdir=simu --work=work $(SIMTOP)
|
49 |
|
|
33 @echo
|
50 |
|
|
34 @mv $(SIMTOP) simu/$(SIMTOP)
|
51 |
|
|
35
|
52 |
|
|
36 run:
|
53 |
|
|
37 @$(SIMDIR)/$(SIMTOP) $(GHDL_SIM_OPT) --vcdgz=$(SIMDIR)/$(SIMTOP).vcdgz
|
54 |
|
|
38
|
55 |
|
|
39 view:
|
56 |
|
|
40 gunzip --stdout $(SIMDIR)/$(SIMTOP).vcdgz | gtkwave --vcd gtkwave.save
|
57 |
|
|
41
|
58 |
|
|
42 clean:
|
59 |
|
|
43 ghdl --clean --workdir=simu
|
60 |
|
|
44
|
61 |
|
|
<pre class="filename">
|
62 |
|
|
Makefile
|
63 |
|
|
</pre></pre>
|
64 |
|
|
<P>
|
65 |
|
|
|
66 |
|
|
<P><hr><BR>
|
67 |
|
|
<table class="ttop"><th class="tpre"><a href="30_Listing_of_avr_fpga.ucf.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="32_Listing_of_hello.c.html">Next Lesson</a></th></table>
|
68 |
|
|
</BODY>
|
69 |
|
|
</HTML>
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.