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[/] [cpu_lecture/] [trunk/] [src/] [avr_fpga.vhd] - Blame information for rev 15

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1 2 jsauermann
-------------------------------------------------------------------------------
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-- 
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-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
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-- 
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--  This code is free software: you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation, either version 3 of the License, or
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--  (at your option) any later version.
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--
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--  This code is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details.
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--
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--  You should have received a copy of the GNU General Public License
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--  along with this code (see the file named COPYING).
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--  If not, see http://www.gnu.org/licenses/.
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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-- Module Name:     avr_fpga - Behavioral 
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-- Create Date:     13:51:24 11/07/2009 
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-- Description:     top level of a CPU
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--
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity avr_fpga is
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    port (  I_CLK_100   : in  std_logic;
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            I_SWITCH    : in  std_logic_vector(9 downto 0);
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            I_RX        : in  std_logic;
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            Q_7_SEGMENT : out std_logic_vector(6 downto 0);
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            Q_LEDS      : out std_logic_vector(3 downto 0);
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            Q_TX        : out std_logic);
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end avr_fpga;
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architecture Behavioral of avr_fpga is
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component cpu_core
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    port (  I_CLK       : in  std_logic;
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            I_CLR       : in  std_logic;
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            I_INTVEC    : in  std_logic_vector( 5 downto 0);
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            I_DIN       : in  std_logic_vector( 7 downto 0);
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            Q_OPC       : out std_logic_vector(15 downto 0);
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            Q_PC        : out std_logic_vector(15 downto 0);
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            Q_DOUT      : out std_logic_vector( 7 downto 0);
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            Q_ADR_IO    : out std_logic_vector( 7 downto 0);
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            Q_RD_IO     : out std_logic;
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            Q_WE_IO     : out std_logic);
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end component;
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signal  C_PC            : std_logic_vector(15 downto 0);
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signal  C_OPC           : std_logic_vector(15 downto 0);
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signal  C_ADR_IO        : std_logic_vector( 7 downto 0);
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signal  C_DOUT          : std_logic_vector( 7 downto 0);
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signal  C_RD_IO         : std_logic;
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signal  C_WE_IO         : std_logic;
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component io
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    port (  I_CLK       : in  std_logic;
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            I_CLR       : in  std_logic;
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            I_ADR_IO    : in  std_logic_vector( 7 downto 0);
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            I_DIN       : in  std_logic_vector( 7 downto 0);
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            I_RD_IO     : in  std_logic;
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            I_WE_IO     : in  std_logic;
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            I_SWITCH    : in  std_logic_vector( 7 downto 0);
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            I_RX        : in  std_logic;
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            Q_7_SEGMENT : out std_logic_vector( 6 downto 0);
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            Q_DOUT      : out std_logic_vector( 7 downto 0);
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            Q_INTVEC    : out std_logic_vector(5 downto 0);
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            Q_LEDS      : out std_logic_vector( 1 downto 0);
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            Q_TX        : out std_logic);
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end component;
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signal N_INTVEC         : std_logic_vector( 5 downto 0);
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signal N_DOUT           : std_logic_vector( 7 downto 0);
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signal N_TX             : std_logic;
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signal N_7_SEGMENT      : std_logic_vector( 6 downto 0);
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component segment7
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    port ( I_CLK        : in  std_logic;
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           I_CLR        : in  std_logic;
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           I_OPC        : in  std_logic_vector(15 downto 0);
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           I_PC         : in  std_logic_vector(15 downto 0);
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           Q_7_SEGMENT  : out std_logic_vector( 6 downto 0));
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end component;
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signal S_7_SEGMENT      : std_logic_vector( 6 downto 0);
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signal L_CLK            : std_logic := '0';
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signal L_CLK_CNT        : std_logic_vector( 2 downto 0) := "000";
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signal L_CLR            : std_logic;            -- reset,  active low
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signal L_CLR_N          : std_logic := '0';     -- reset,  active low
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signal L_C1_N           : std_logic := '0';     -- switch debounce, active low
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signal L_C2_N           : std_logic := '0';     -- switch debounce, active low
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begin
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    cpu : cpu_core
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    port map(   I_CLK       => L_CLK,
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                I_CLR       => L_CLR,
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                I_DIN       => N_DOUT,
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                I_INTVEC    => N_INTVEC,
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                Q_ADR_IO    => C_ADR_IO,
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                Q_DOUT      => C_DOUT,
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                Q_OPC       => C_OPC,
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                Q_PC        => C_PC,
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                Q_RD_IO     => C_RD_IO,
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                Q_WE_IO     => C_WE_IO);
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    ino : io
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    port map(   I_CLK       => L_CLK,
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                I_CLR       => L_CLR,
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                I_ADR_IO    => C_ADR_IO,
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                I_DIN       => C_DOUT,
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                I_RD_IO     => C_RD_IO,
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                I_RX        => I_RX,
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                I_SWITCH    => I_SWITCH(7 downto 0),
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                I_WE_IO     => C_WE_IO,
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                Q_7_SEGMENT => N_7_SEGMENT,
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                Q_DOUT      => N_DOUT,
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                Q_INTVEC    => N_INTVEC,
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                Q_LEDS      => Q_LEDS(1 downto 0),
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                Q_TX        => N_TX);
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    seg : segment7
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    port map(   I_CLK       => L_CLK,
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                I_CLR       => L_CLR,
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                I_OPC       => C_OPC,
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                I_PC        => C_PC,
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                Q_7_SEGMENT => S_7_SEGMENT);
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    -- input clock scaler
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    --
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    clk_div : process(I_CLK_100)
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    begin
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        if (rising_edge(I_CLK_100)) then
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            L_CLK_CNT <= L_CLK_CNT + "001";
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            if (L_CLK_CNT = "001") then
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                L_CLK_CNT <= "000";
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                L_CLK <= not L_CLK;
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            end if;
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        end if;
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    end process;
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    -- reset button debounce process
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    --
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    deb : process(L_CLK)
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    begin
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        if (rising_edge(L_CLK)) then
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            -- switch debounce
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            if ((I_SWITCH(8) = '0') or (I_SWITCH(9) = '0')) then    -- pushed
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                L_CLR_N <= '0';
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                L_C2_N  <= '0';
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                L_C1_N  <= '0';
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            else                                                    -- released
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                L_CLR_N <= L_C2_N;
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                L_C2_N  <= L_C1_N;
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                L_C1_N  <= '1';
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            end if;
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        end if;
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    end process;
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    L_CLR <= not L_CLR_N;
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    Q_LEDS(2) <= I_RX;
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    Q_LEDS(3) <= N_TX;
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    Q_7_SEGMENT  <= N_7_SEGMENT when (I_SWITCH(7) = '1') else S_7_SEGMENT;
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    Q_TX <= N_TX;
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end Behavioral;
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