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[/] [cpu_lecture/] [trunk/] [src/] [baudgen.vhd] - Blame information for rev 18

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1 2 jsauermann
-------------------------------------------------------------------------------
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-- 
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-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
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-- 
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--  This code is free software: you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation, either version 3 of the License, or
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--  (at your option) any later version.
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--
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--  This code is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details.
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--
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--  You should have received a copy of the GNU General Public License
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--  along with this code (see the file named COPYING).
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--  If not, see http://www.gnu.org/licenses/.
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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-- Module Name:    baudgen - Behavioral 
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-- Create Date:    13:51:24 11/07/2009 
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-- Description:    fixed baud rate generator
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--
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-------------------------------------------------------------------------------
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity baudgen is
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    generic(clock_freq  : std_logic_vector(31 downto 0);
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                baud_rate   : std_logic_vector(27 downto 0));
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    port(   I_CLK       : in  std_logic;
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            I_CLR       : in  std_logic;
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            Q_CE_1      : out std_logic;    -- baud x  1 clock enable
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            Q_CE_16     : out std_logic);   -- baud x 16 clock enable
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end baudgen;
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architecture Behavioral of baudgen is
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constant BAUD_16        : std_logic_vector(31 downto 0) := baud_rate & "0000";
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constant LIMIT          : std_logic_vector(31 downto 0) := clock_freq - BAUD_16;
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signal L_CE_16          : std_logic;
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signal L_CNT_16         : std_logic_vector( 3 downto 0);
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signal L_COUNTER        : std_logic_vector(31 downto 0);
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begin
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    baud16: process(I_CLK)
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    begin
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        if (rising_edge(I_CLK)) then
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            if (I_CLR = '1') then
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                L_COUNTER <= X"00000000";
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            elsif (L_COUNTER >= LIMIT) then
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                L_COUNTER <= L_COUNTER - LIMIT;
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            else
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                L_COUNTER <= L_COUNTER + BAUD_16;
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            end if;
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        end if;
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    end process;
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    baud1: process(I_CLK)
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    begin
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        if (rising_edge(I_CLK)) then
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            if (I_CLR = '1') then
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                L_CNT_16 <= "0000";
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            elsif (L_CE_16 = '1') then
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                L_CNT_16 <= L_CNT_16 + "0001";
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            end if;
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        end if;
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    end process;
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    L_CE_16 <= '1' when (L_COUNTER >= LIMIT) else '0';
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    Q_CE_16 <= L_CE_16;
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    Q_CE_1 <= L_CE_16 when L_CNT_16 = "1111" else '0';
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end behavioral;
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