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jsauermann |
-------------------------------------------------------------------------------
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--
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-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
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--
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-- This code is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this code (see the file named COPYING).
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-- If not, see http://www.gnu.org/licenses/.
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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-- Module Name: data_mem - Behavioral
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-- Create Date: 14:09:04 10/30/2009
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-- Description: the data mempry of a CPU.
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--
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-------------------------------------------------------------------------------
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity data_mem is
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port ( I_CLK : in std_logic;
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I_ADR : in std_logic_vector(10 downto 0);
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I_DIN : in std_logic_vector(15 downto 0);
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I_WE : in std_logic_vector( 1 downto 0);
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Q_DOUT : out std_logic_vector(15 downto 0));
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end data_mem;
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architecture Behavioral of data_mem is
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constant zero_256 : bit_vector := X"00000000000000000000000000000000"
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& X"00000000000000000000000000000000";
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constant nine_256 : bit_vector := X"99999999999999999999999999999999"
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& X"99999999999999999999999999999999";
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component RAMB4_S4_S4
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generic(INIT_00 : bit_vector := zero_256;
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INIT_01 : bit_vector := zero_256;
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INIT_02 : bit_vector := zero_256;
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INIT_03 : bit_vector := zero_256;
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INIT_04 : bit_vector := zero_256;
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INIT_05 : bit_vector := zero_256;
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INIT_06 : bit_vector := zero_256;
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INIT_07 : bit_vector := zero_256;
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INIT_08 : bit_vector := zero_256;
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INIT_09 : bit_vector := zero_256;
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INIT_0A : bit_vector := zero_256;
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INIT_0B : bit_vector := zero_256;
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INIT_0C : bit_vector := zero_256;
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INIT_0D : bit_vector := zero_256;
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INIT_0E : bit_vector := zero_256;
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INIT_0F : bit_vector := zero_256);
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port( DOA : out std_logic_vector(3 downto 0);
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DOB : out std_logic_vector(3 downto 0);
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ADDRA : in std_logic_vector(9 downto 0);
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ADDRB : in std_logic_vector(9 downto 0);
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CLKA : in std_ulogic;
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CLKB : in std_ulogic;
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DIA : in std_logic_vector(3 downto 0);
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DIB : in std_logic_vector(3 downto 0);
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ENA : in std_ulogic;
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ENB : in std_ulogic;
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RSTA : in std_ulogic;
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RSTB : in std_ulogic;
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WEA : in std_ulogic;
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WEB : in std_ulogic);
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end component;
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signal L_ADR_0 : std_logic;
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signal L_ADR_E : std_logic_vector(10 downto 1);
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signal L_ADR_O : std_logic_vector(10 downto 1);
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signal L_DIN_E : std_logic_vector( 7 downto 0);
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signal L_DIN_O : std_logic_vector( 7 downto 0);
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signal L_DOUT_E : std_logic_vector( 7 downto 0);
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signal L_DOUT_O : std_logic_vector( 7 downto 0);
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signal L_WE_E : std_logic;
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signal L_WE_O : std_logic;
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begin
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sr_0 : RAMB4_S4_S4 ---------------------------------------------------------
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generic map(INIT_00 => nine_256, INIT_01 => nine_256, INIT_02 => nine_256,
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INIT_03 => nine_256, INIT_04 => nine_256, INIT_05 => nine_256,
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INIT_06 => nine_256, INIT_07 => nine_256, INIT_08 => nine_256,
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INIT_09 => nine_256, INIT_0A => nine_256, INIT_0B => nine_256,
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INIT_0C => nine_256, INIT_0D => nine_256, INIT_0E => nine_256,
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INIT_0F => nine_256)
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port map( ADDRA => L_ADR_E, ADDRB => "0000000000",
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CLKA => I_CLK, CLKB => I_CLK,
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DIA => L_DIN_E(3 downto 0), DIB => "0000",
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ENA => '1', ENB => '0',
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RSTA => '0', RSTB => '0',
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WEA => L_WE_E, WEB => '0',
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DOA => L_DOUT_E(3 downto 0), DOB => open);
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sr_1 : RAMB4_S4_S4 ---------------------------------------------------------
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generic map(INIT_00 => nine_256, INIT_01 => nine_256, INIT_02 => nine_256,
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INIT_03 => nine_256, INIT_04 => nine_256, INIT_05 => nine_256,
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INIT_06 => nine_256, INIT_07 => nine_256, INIT_08 => nine_256,
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INIT_09 => nine_256, INIT_0A => nine_256, INIT_0B => nine_256,
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INIT_0C => nine_256, INIT_0D => nine_256, INIT_0E => nine_256,
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INIT_0F => nine_256)
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port map( ADDRA => L_ADR_E, ADDRB => "0000000000",
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CLKA => I_CLK, CLKB => I_CLK,
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DIA => L_DIN_E(7 downto 4), DIB => "0000",
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ENA => '1', ENB => '0',
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RSTA => '0', RSTB => '0',
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WEA => L_WE_E, WEB => '0',
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DOA => L_DOUT_E(7 downto 4), DOB => open);
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sr_2 : RAMB4_S4_S4 ---------------------------------------------------------
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generic map(INIT_00 => nine_256, INIT_01 => nine_256, INIT_02 => nine_256,
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INIT_03 => nine_256, INIT_04 => nine_256, INIT_05 => nine_256,
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INIT_06 => nine_256, INIT_07 => nine_256, INIT_08 => nine_256,
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INIT_09 => nine_256, INIT_0A => nine_256, INIT_0B => nine_256,
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INIT_0C => nine_256, INIT_0D => nine_256, INIT_0E => nine_256,
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INIT_0F => nine_256)
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port map( ADDRA => L_ADR_O, ADDRB => "0000000000",
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CLKA => I_CLK, CLKB => I_CLK,
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DIA => L_DIN_O(3 downto 0), DIB => "0000",
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ENA => '1', ENB => '0',
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RSTA => '0', RSTB => '0',
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WEA => L_WE_O, WEB => '0',
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DOA => L_DOUT_O(3 downto 0), DOB => open);
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sr_3 : RAMB4_S4_S4 ---------------------------------------------------------
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generic map(INIT_00 => nine_256, INIT_01 => nine_256, INIT_02 => nine_256,
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INIT_03 => nine_256, INIT_04 => nine_256, INIT_05 => nine_256,
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INIT_06 => nine_256, INIT_07 => nine_256, INIT_08 => nine_256,
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INIT_09 => nine_256, INIT_0A => nine_256, INIT_0B => nine_256,
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INIT_0C => nine_256, INIT_0D => nine_256, INIT_0E => nine_256,
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INIT_0F => nine_256)
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port map( ADDRA => L_ADR_O, ADDRB => "0000000000",
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CLKA => I_CLK, CLKB => I_CLK,
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DIA => L_DIN_O(7 downto 4), DIB => "0000",
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ENA => '1', ENB => '0',
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RSTA => '0', RSTB => '0',
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WEA => L_WE_O, WEB => '0',
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DOA => L_DOUT_O(7 downto 4), DOB => open);
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-- remember ADR(0)
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--
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adr0: process(I_CLK)
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begin
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if (rising_edge(I_CLK)) then
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L_ADR_0 <= I_ADR(0);
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end if;
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end process;
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-- we use two memory blocks _E and _O (even and odd).
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-- This gives us a memory with ADR and ADR + 1 at th same time.
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-- The second port is currently unused, but may be used later,
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-- e.g. for DMA.
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--
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L_ADR_O <= I_ADR(10 downto 1);
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L_ADR_E <= I_ADR(10 downto 1) + ("000000000" & I_ADR(0));
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L_DIN_E <= I_DIN( 7 downto 0) when (I_ADR(0) = '0') else I_DIN(15 downto 8);
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L_DIN_O <= I_DIN( 7 downto 0) when (I_ADR(0) = '1') else I_DIN(15 downto 8);
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L_WE_E <= I_WE(1) or (I_WE(0) and not I_ADR(0));
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L_WE_O <= I_WE(1) or (I_WE(0) and I_ADR(0));
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Q_DOUT( 7 downto 0) <= L_DOUT_E when (L_ADR_0 = '0') else L_DOUT_O;
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Q_DOUT(15 downto 8) <= L_DOUT_E when (L_ADR_0 = '1') else L_DOUT_O;
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end Behavioral;
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