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jsauermann |
-------------------------------------------------------------------------------
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--
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-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
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--
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-- This code is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this code (see the file named COPYING).
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-- If not, see http://www.gnu.org/licenses/.
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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-- Module Name: opc_deco - Behavioral
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-- Create Date: 16:05:16 10/29/2009
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-- Description: the opcode decoder of a CPU.
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--
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-------------------------------------------------------------------------------
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use work.common.ALL;
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entity opc_deco is
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port ( I_CLK : in std_logic;
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I_OPC : in std_logic_vector(31 downto 0);
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I_PC : in std_logic_vector(15 downto 0);
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I_T0 : in std_logic;
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Q_ALU_OP : out std_logic_vector( 4 downto 0);
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Q_AMOD : out std_logic_vector( 5 downto 0);
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Q_BIT : out std_logic_vector( 3 downto 0);
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Q_DDDDD : out std_logic_vector( 4 downto 0);
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Q_IMM : out std_logic_vector(15 downto 0);
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Q_JADR : out std_logic_vector(15 downto 0);
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Q_OPC : out std_logic_vector(15 downto 0);
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Q_PC : out std_logic_vector(15 downto 0);
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Q_PC_OP : out std_logic_vector( 2 downto 0);
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Q_PMS : out std_logic; -- program memory select
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Q_RD_M : out std_logic;
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Q_RRRRR : out std_logic_vector( 4 downto 0);
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Q_RSEL : out std_logic_vector( 1 downto 0);
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Q_WE_01 : out std_logic;
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Q_WE_D : out std_logic_vector( 1 downto 0);
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Q_WE_F : out std_logic;
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Q_WE_M : out std_logic_vector( 1 downto 0);
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Q_WE_XYZS : out std_logic);
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end opc_deco;
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architecture Behavioral of opc_deco is
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begin
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process(I_CLK)
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begin
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if (rising_edge(I_CLK)) then
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--
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-- set the most common settings as default.
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--
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Q_ALU_OP <= ALU_D_MV_Q;
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Q_AMOD <= AMOD_ABS;
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Q_BIT <= I_OPC(10) & I_OPC(2 downto 0);
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Q_DDDDD <= I_OPC(8 downto 4);
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Q_IMM <= X"0000";
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Q_JADR <= I_OPC(31 downto 16);
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Q_OPC <= I_OPC(15 downto 0);
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Q_PC <= I_PC;
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Q_PC_OP <= PC_NEXT;
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Q_PMS <= '0';
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Q_RD_M <= '0';
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Q_RRRRR <= I_OPC(9) & I_OPC(3 downto 0);
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Q_RSEL <= RS_REG;
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Q_WE_D <= "00";
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Q_WE_01 <= '0';
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Q_WE_F <= '0';
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Q_WE_M <= "00";
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Q_WE_XYZS <= '0';
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case I_OPC(15 downto 10) is
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when "000000" =>
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case I_OPC(9 downto 8) is
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when "00" =>
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--
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-- 0000 0000 0000 0000 - NOP
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-- 0000 0000 001v vvvv - INTERRUPT
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--
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if (I_OPC(5)) = '1' then -- interrupt
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Q_ALU_OP <= ALU_INTR;
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Q_AMOD <= AMOD_ddSP;
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Q_JADR <= "0000000000" & I_OPC(4 downto 0) & "0";
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Q_PC_OP <= PC_LD_I;
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Q_WE_F <= '1';
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Q_WE_M <= "11";
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end if;
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when "01" =>
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--
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-- 0000 0001 dddd rrrr - MOVW
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--
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Q_DDDDD <= I_OPC(7 downto 4) & "0";
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Q_RRRRR <= I_OPC(3 downto 0) & "0";
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Q_ALU_OP <= ALU_MV_16;
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Q_WE_D <= "11";
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when "10" =>
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--
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-- 0000 0010 dddd rrrr - MULS
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--
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Q_DDDDD <= "1" & I_OPC(7 downto 4);
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Q_RRRRR <= "1" & I_OPC(3 downto 0);
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Q_ALU_OP <= ALU_MULT;
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Q_IMM(7 downto 5) <= MULT_SS;
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Q_WE_01 <= '1';
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Q_WE_F <= '1';
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when others =>
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--
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-- 0000 0011 0ddd 0rrr - _MULSU SU "010"
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-- 0000 0011 0ddd 1rrr - FMUL UU "100"
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-- 0000 0011 1ddd 0rrr - FMULS SS "111"
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-- 0000 0011 1ddd 1rrr - FMULSU SU "110"
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--
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Q_DDDDD(4 downto 3) <= "10"; -- regs 16 to 23
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Q_RRRRR(4 downto 3) <= "10"; -- regs 16 to 23
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Q_ALU_OP <= ALU_MULT;
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if I_OPC(7) = '0' then
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if I_OPC(3) = '0' then
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Q_IMM(7 downto 5) <= MULT_SU;
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else
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Q_IMM(7 downto 5) <= MULT_FUU;
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end if;
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else
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if I_OPC(3) = '0' then
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Q_IMM(7 downto 5) <= MULT_FSS;
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else
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Q_IMM(7 downto 5) <= MULT_FSU;
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end if;
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end if;
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Q_WE_01 <= '1';
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Q_WE_F <= '1';
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end case;
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when "000001" | "000010" =>
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--
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-- 0000 01rd dddd rrrr - CPC = SBC without Q_WE_D
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-- 0000 10rd dddd rrrr - SBC
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--
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Q_ALU_OP <= ALU_SBC;
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Q_WE_D <= '0' & I_OPC(11); -- write Rd if SBC.
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Q_WE_F <= '1';
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when "000011" =>
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--
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-- 0000 11rd dddd rrrr - ADD
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--
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Q_ALU_OP <= ALU_ADD;
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Q_WE_D <= "01";
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Q_WE_F <= '1';
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when "000100" => -- CPSE
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Q_ALU_OP <= ALU_SUB;
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Q_RD_M <= I_T0;
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if (I_T0 = '0') then -- second cycle.
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Q_PC_OP <= PC_SKIP_Z;
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end if;
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when "000101" | "000110" =>
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--
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-- 0001 01rd dddd rrrr - CP = SUB without Q_WE_D
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-- 0000 10rd dddd rrrr - SUB
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--
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Q_ALU_OP <= ALU_SUB;
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Q_WE_D <= '0' & I_OPC(11); -- write Rd if SUB.
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Q_WE_F <= '1';
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when "000111" =>
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--
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-- 0001 11rd dddd rrrr - ADC
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--
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Q_ALU_OP <= ALU_ADC;
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Q_WE_D <= "01";
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Q_WE_F <= '1';
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when "001000" =>
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--
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-- 0010 00rd dddd rrrr - AND
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--
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Q_ALU_OP <= ALU_AND;
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Q_WE_D <= "01";
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Q_WE_F <= '1';
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when "001001" =>
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--
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-- 0010 01rd dddd rrrr - EOR
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--
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Q_ALU_OP <= ALU_EOR;
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Q_WE_D <= "01";
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Q_WE_F <= '1';
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when "001010" => -- OR
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--
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-- 0010 10rd dddd rrrr - OR
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--
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Q_ALU_OP <= ALU_OR;
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Q_WE_D <= "01";
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Q_WE_F <= '1';
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when "001011" =>
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--
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-- 0010 11rd dddd rrrr - MOV
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--
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Q_ALU_OP <= ALU_R_MV_Q;
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Q_WE_D <= "01";
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when "001100" | "001101" | "001110" | "001111"
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| "010100" | "010101" | "010110" | "010111" =>
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--
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-- 0011 KKKK dddd KKKK - CPI
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-- 0101 KKKK dddd KKKK - SUBI
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--
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Q_ALU_OP <= ALU_SUB;
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Q_IMM(7 downto 0) <= I_OPC(11 downto 8) & I_OPC(3 downto 0);
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Q_RSEL <= RS_IMM;
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Q_DDDDD(4) <= '1'; -- Rd = 16...31
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Q_WE_D <= '0' & I_OPC(14);
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Q_WE_F <= '1';
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when "010000" | "010001" | "010010" | "010011" =>
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--
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-- 0100 KKKK dddd KKKK - SBCI
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--
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Q_ALU_OP <= ALU_SBC;
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Q_IMM(7 downto 0) <= I_OPC(11 downto 8) & I_OPC(3 downto 0);
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Q_RSEL <= RS_IMM;
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Q_DDDDD(4) <= '1'; -- Rd = 16...31
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Q_WE_D <= "01";
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Q_WE_F <= '1';
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when "011000" | "011001" | "011010" | "011011" =>
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--
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-- 0110 KKKK dddd KKKK - ORI
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--
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Q_ALU_OP <= ALU_OR;
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Q_IMM(7 downto 0) <= I_OPC(11 downto 8) & I_OPC(3 downto 0);
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Q_RSEL <= RS_IMM;
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Q_DDDDD(4) <= '1'; -- Rd = 16...31
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Q_WE_D <= "01";
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Q_WE_F <= '1';
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when "011100" | "011101" | "011110" | "011111" =>
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--
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-- 0111 KKKK dddd KKKK - ANDI
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--
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Q_ALU_OP <= ALU_AND;
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Q_IMM(7 downto 0) <= I_OPC(11 downto 8) & I_OPC(3 downto 0);
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Q_RSEL <= RS_IMM;
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Q_DDDDD(4) <= '1'; -- Rd = 16...31
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Q_WE_D <= "01";
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Q_WE_F <= '1';
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when "100000" | "100001" | "100010" | "100011"
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| "101000" | "101001" | "101010" | "101011" =>
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--
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-- LDD (Y + q) == LD (y) if q == 0
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--
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-- 10q0 qq0d dddd 1qqq LDD (Y + q)
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-- 10q0 qq0d dddd 0qqq LDD (Z + q)
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-- 10q0 qq1d dddd 1qqq SDD (Y + q)
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-- 10q0 qq1d dddd 0qqq SDD (Z + q)
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-- L/ Z/
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-- S Y
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--
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Q_IMM(5) <= I_OPC(13);
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Q_IMM(4 downto 3) <= I_OPC(11 downto 10);
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Q_IMM(2 downto 0) <= I_OPC( 2 downto 0);
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if (I_OPC(3) = '0') then Q_AMOD <= AMOD_Zq;
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else Q_AMOD <= AMOD_Yq;
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end if;
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Q_RD_M <= not I_OPC(9); -- '1' if LDD
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Q_WE_M <= '0' & I_OPC(9); -- "01" if STD
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when "100100" =>
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Q_IMM <= I_OPC(31 downto 16); -- absolute address for LDS/STS
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if (I_OPC(9) = '0') then -- LDD / POP
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--
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-- 1001 00-0d dddd 0000 - LDS
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-- 1001 00-0d dddd 0001 - LD Rd, Z+
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-- 1001 00-0d dddd 0010 - LD Rd, -Z
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-- 1001 00-0d dddd 0100 - (ii) LPM Rd, (Z)
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-- 1001 00-0d dddd 0101 - (iii) LPM Rd, (Z+)
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-- 1001 00-0d dddd 0110 - ELPM Z --- not mega8
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-- 1001 00-0d dddd 0111 - ELPM Z+ --- not mega8
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-- 1001 00-0d dddd 1001 - LD Rd, Y+
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-- 1001 00-0d dddd 1010 - LD Rd, -Y
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| 309 |
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-- 1001 00-0d dddd 1100 - LD Rd, X
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-- 1001 00-0d dddd 1101 - LD Rd, X+
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-- 1001 00-0d dddd 1110 - LD Rd, -X
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-- 1001 00-0d dddd 1111 - POP Rd
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--
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| 314 |
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Q_RSEL <= RS_DIN;
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|
Q_RD_M <= I_T0;
|
| 316 |
|
|
Q_WE_D <= '0' & not I_T0;
|
| 317 |
|
|
Q_WE_XYZS <= not I_T0;
|
| 318 |
|
|
Q_PMS <= (not I_OPC(3)) and I_OPC(2) and (not I_OPC(1));
|
| 319 |
|
|
case I_OPC(3 downto 0) is
|
| 320 |
|
|
when "0000" => Q_AMOD <= AMOD_ABS; Q_WE_XYZS <= '0';
|
| 321 |
|
|
when "0001" => Q_AMOD <= AMOD_Zi;
|
| 322 |
|
|
when "0100" => Q_AMOD <= AMOD_Z; Q_WE_XYZS <= '0';
|
| 323 |
|
|
when "0101" => Q_AMOD <= AMOD_Zi;
|
| 324 |
|
|
when "1001" => Q_AMOD <= AMOD_Yi;
|
| 325 |
|
|
when "1010" => Q_AMOD <= AMOD_dY;
|
| 326 |
|
|
when "1100" => Q_AMOD <= AMOD_X; Q_WE_XYZS <= '0';
|
| 327 |
|
|
when "1101" => Q_AMOD <= AMOD_Xi;
|
| 328 |
|
|
when "1110" => Q_AMOD <= AMOD_dX;
|
| 329 |
|
|
when "1111" => Q_AMOD <= AMOD_SPi;
|
| 330 |
|
|
when others => Q_WE_XYZS <= '0';
|
| 331 |
|
|
end case;
|
| 332 |
|
|
else -- STD / PUSH
|
| 333 |
|
|
--
|
| 334 |
|
|
-- 1001 00-1r rrrr 0000 - STS
|
| 335 |
|
|
-- 1001 00-1r rrrr 0001 - ST Z+. Rr
|
| 336 |
|
|
-- 1001 00-1r rrrr 0010 - ST -Z. Rr
|
| 337 |
|
|
-- 1001 00-1r rrrr 1000 - ST Y. Rr
|
| 338 |
|
|
-- 1001 00-1r rrrr 1001 - ST Y+. Rr
|
| 339 |
|
|
-- 1001 00-1r rrrr 1010 - ST -Y. Rr
|
| 340 |
|
|
-- 1001 00-1r rrrr 1100 - ST X. Rr
|
| 341 |
|
|
-- 1001 00-1r rrrr 1101 - ST X+. Rr
|
| 342 |
|
|
-- 1001 00-1r rrrr 1110 - ST -X. Rr
|
| 343 |
|
|
-- 1001 00-1r rrrr 1111 - PUSH Rr
|
| 344 |
|
|
--
|
| 345 |
|
|
Q_ALU_OP <= ALU_D_MV_Q;
|
| 346 |
|
|
Q_WE_M <= "01";
|
| 347 |
|
|
Q_WE_XYZS <= '1';
|
| 348 |
|
|
case I_OPC(3 downto 0) is
|
| 349 |
|
|
when "0000" => Q_AMOD <= AMOD_ABS; Q_WE_XYZS <= '0';
|
| 350 |
|
|
when "0001" => Q_AMOD <= AMOD_Zi;
|
| 351 |
|
|
when "0010" => Q_AMOD <= AMOD_dZ;
|
| 352 |
|
|
when "1001" => Q_AMOD <= AMOD_Yi;
|
| 353 |
|
|
when "1010" => Q_AMOD <= AMOD_dY;
|
| 354 |
|
|
when "1100" => Q_AMOD <= AMOD_X; Q_WE_XYZS <= '0';
|
| 355 |
|
|
when "1101" => Q_AMOD <= AMOD_Xi;
|
| 356 |
|
|
when "1110" => Q_AMOD <= AMOD_dX;
|
| 357 |
|
|
when "1111" => Q_AMOD <= AMOD_dSP;
|
| 358 |
|
|
when others =>
|
| 359 |
|
|
end case;
|
| 360 |
|
|
end if;
|
| 361 |
|
|
|
| 362 |
|
|
when "100101" =>
|
| 363 |
|
|
if (I_OPC(9) = '0') then
|
| 364 |
|
|
if (I_OPC(3) = '0') then
|
| 365 |
|
|
--
|
| 366 |
|
|
-- 1001 010d dddd 0000 - COM
|
| 367 |
|
|
-- 1001 010d dddd 0001 - NEG
|
| 368 |
|
|
-- 1001 010d dddd 0010 - SWAP
|
| 369 |
|
|
-- 1001 010d dddd 0011 - INC
|
| 370 |
|
|
-- 1001 010d dddd 0101 - ASR
|
| 371 |
|
|
-- 1001 010d dddd 0110 - LSR
|
| 372 |
|
|
-- 1001 010d dddd 0111 - ROR
|
| 373 |
|
|
--
|
| 374 |
|
|
case I_OPC(2 downto 0) is
|
| 375 |
|
|
when "000" => Q_ALU_OP <= ALU_COM;
|
| 376 |
|
|
when "001" => Q_ALU_OP <= ALU_NEG;
|
| 377 |
|
|
when "010" => Q_ALU_OP <= ALU_SWAP;
|
| 378 |
|
|
when "011" => Q_ALU_OP <= ALU_INC;
|
| 379 |
|
|
when "101" => Q_ALU_OP <= ALU_ASR;
|
| 380 |
|
|
when "110" => Q_ALU_OP <= ALU_LSR;
|
| 381 |
|
|
when "111" => Q_ALU_OP <= ALU_ROR;
|
| 382 |
|
|
when others =>
|
| 383 |
|
|
end case;
|
| 384 |
|
|
Q_WE_D <= "01";
|
| 385 |
|
|
Q_WE_F <= '1';
|
| 386 |
|
|
else
|
| 387 |
|
|
case I_OPC(2 downto 0) is
|
| 388 |
|
|
when "000" =>
|
| 389 |
|
|
if (I_OPC(8)) = '0' then
|
| 390 |
|
|
--
|
| 391 |
|
|
-- 1001 0100 0sss 1000 - BSET
|
| 392 |
|
|
-- 1001 0100 1sss 1000 - BCLR
|
| 393 |
|
|
--
|
| 394 |
|
|
Q_BIT(3 downto 0) <= I_OPC(7 downto 4);
|
| 395 |
|
|
Q_ALU_OP <= ALU_SREG;
|
| 396 |
|
|
Q_WE_F <= '1';
|
| 397 |
|
|
else
|
| 398 |
|
|
--
|
| 399 |
|
|
-- 1001 0101 0000 1000 - RET
|
| 400 |
|
|
-- 1001 0101 0001 1000 - RETI
|
| 401 |
|
|
-- 1001 0101 1000 1000 - SLEEP
|
| 402 |
|
|
-- 1001 0101 1001 1000 - BREAK
|
| 403 |
|
|
-- 1001 0101 1100 1000 - LPM [ R0,(Z) ]
|
| 404 |
|
|
-- 1001 0101 1101 1000 - ELPM not mega8
|
| 405 |
|
|
-- 1001 0101 1110 1000 - SPM
|
| 406 |
|
|
-- 1001 0101 1111 1000 - SPM #2
|
| 407 |
|
|
-- 1001 0101 1010 1000 - WDR
|
| 408 |
|
|
--
|
| 409 |
|
|
case I_OPC(7 downto 4) is
|
| 410 |
|
|
when "0000" => -- RET
|
| 411 |
|
|
Q_AMOD <= AMOD_SPii;
|
| 412 |
|
|
if (I_T0 = '1') then
|
| 413 |
|
|
Q_RD_M <= '1';
|
| 414 |
|
|
else
|
| 415 |
|
|
Q_PC_OP <= PC_LD_S;
|
| 416 |
|
|
Q_WE_XYZS <= not I_T0;
|
| 417 |
|
|
end if;
|
| 418 |
|
|
|
| 419 |
|
|
when "0001" => -- RETI
|
| 420 |
|
|
Q_ALU_OP <= ALU_INTR;
|
| 421 |
|
|
Q_IMM(6) <= '1';
|
| 422 |
|
|
Q_AMOD <= AMOD_SPii;
|
| 423 |
|
|
if (I_T0 = '1') then
|
| 424 |
|
|
Q_RD_M <= '1';
|
| 425 |
|
|
else
|
| 426 |
|
|
Q_PC_OP <= PC_LD_S;
|
| 427 |
|
|
Q_WE_XYZS <= not I_T0;
|
| 428 |
|
|
end if;
|
| 429 |
|
|
|
| 430 |
|
|
when "1000" => -- (i) LPM R0, (Z)
|
| 431 |
|
|
Q_DDDDD <= "00000";
|
| 432 |
|
|
Q_AMOD <= AMOD_Z;
|
| 433 |
|
|
Q_PMS <= '1';
|
| 434 |
|
|
Q_WE_D <= '0' & not I_T0;
|
| 435 |
|
|
|
| 436 |
|
|
when "1110" => -- SPM
|
| 437 |
|
|
Q_DDDDD <= "00000";
|
| 438 |
|
|
Q_AMOD <= AMOD_Z;
|
| 439 |
|
|
Q_PMS <= '1';
|
| 440 |
|
|
Q_WE_M <= "01";
|
| 441 |
|
|
|
| 442 |
|
|
when "1111" => -- SPM #2
|
| 443 |
|
|
-- page write: not su[pported
|
| 444 |
|
|
|
| 445 |
|
|
when others =>
|
| 446 |
|
|
end case;
|
| 447 |
|
|
end if;
|
| 448 |
|
|
|
| 449 |
|
|
when "001" =>
|
| 450 |
|
|
--
|
| 451 |
|
|
-- 1001 0100 0000 1001 IJMP
|
| 452 |
|
|
-- 1001 0100 0001 1001 EIJMP -- not mega8
|
| 453 |
|
|
-- 1001 0101 0000 1001 ICALL
|
| 454 |
|
|
-- 1001 0101 0001 1001 EICALL -- not mega8
|
| 455 |
|
|
--
|
| 456 |
|
|
Q_PC_OP <= PC_LD_Z;
|
| 457 |
|
|
if (I_OPC(8) = '1') then -- ICALL
|
| 458 |
|
|
Q_ALU_OP <= ALU_PC_1;
|
| 459 |
|
|
Q_AMOD <= AMOD_ddSP;
|
| 460 |
|
|
Q_WE_M <= "11";
|
| 461 |
|
|
Q_WE_XYZS <= '1';
|
| 462 |
|
|
end if;
|
| 463 |
|
|
|
| 464 |
|
|
when "010" =>
|
| 465 |
|
|
--
|
| 466 |
|
|
-- 1001 010d dddd 1010 - DEC
|
| 467 |
|
|
--
|
| 468 |
|
|
Q_ALU_OP <= ALU_DEC;
|
| 469 |
|
|
Q_WE_D <= "01";
|
| 470 |
|
|
Q_WE_F <= '1';
|
| 471 |
|
|
|
| 472 |
|
|
when "011" =>
|
| 473 |
|
|
--
|
| 474 |
|
|
-- 1001 0100 KKKK 1011 - DES -- not mega8
|
| 475 |
|
|
--
|
| 476 |
|
|
|
| 477 |
|
|
when "100" | "101" =>
|
| 478 |
|
|
--
|
| 479 |
|
|
-- 1001 010k kkkk 110k - JMP (k = 0 for 16 bit)
|
| 480 |
|
|
-- kkkk kkkk kkkk kkkk
|
| 481 |
|
|
--
|
| 482 |
|
|
Q_PC_OP <= PC_LD_I;
|
| 483 |
|
|
|
| 484 |
|
|
when "110" | "111" =>
|
| 485 |
|
|
--
|
| 486 |
|
|
-- 1001 010k kkkk 111k - CALL (k = 0)
|
| 487 |
|
|
-- kkkk kkkk kkkk kkkk
|
| 488 |
|
|
--
|
| 489 |
|
|
Q_ALU_OP <= ALU_PC_2;
|
| 490 |
|
|
Q_AMOD <= AMOD_ddSP;
|
| 491 |
|
|
Q_PC_OP <= PC_LD_I;
|
| 492 |
|
|
Q_WE_M <= "11"; -- both PC bytes
|
| 493 |
|
|
Q_WE_XYZS <= '1';
|
| 494 |
|
|
|
| 495 |
|
|
when others =>
|
| 496 |
|
|
end case;
|
| 497 |
|
|
end if;
|
| 498 |
|
|
else
|
| 499 |
|
|
--
|
| 500 |
|
|
-- 1001 0110 KKdd KKKK - ADIW
|
| 501 |
|
|
-- 1001 0111 KKdd KKKK - SBIW
|
| 502 |
|
|
--
|
| 503 |
|
|
if (I_OPC(8) = '0') then Q_ALU_OP <= ALU_ADIW;
|
| 504 |
|
|
else Q_ALU_OP <= ALU_SBIW;
|
| 505 |
|
|
end if;
|
| 506 |
|
|
Q_IMM(5 downto 4) <= I_OPC(7 downto 6);
|
| 507 |
|
|
Q_IMM(3 downto 0) <= I_OPC(3 downto 0);
|
| 508 |
|
|
Q_RSEL <= RS_IMM;
|
| 509 |
|
|
Q_DDDDD <= "11" & I_OPC(5 downto 4) & "0";
|
| 510 |
|
|
|
| 511 |
|
|
Q_WE_D <= "11";
|
| 512 |
|
|
Q_WE_F <= '1';
|
| 513 |
|
|
end if; -- I_OPC(9) = 0/1
|
| 514 |
|
|
|
| 515 |
|
|
when "100110" =>
|
| 516 |
|
|
--
|
| 517 |
|
|
-- 1001 1000 AAAA Abbb - CBI
|
| 518 |
|
|
-- 1001 1001 AAAA Abbb - SBIC
|
| 519 |
|
|
-- 1001 1010 AAAA Abbb - SBI
|
| 520 |
|
|
-- 1001 1011 AAAA Abbb - SBIS
|
| 521 |
|
|
--
|
| 522 |
|
|
Q_ALU_OP <= ALU_BIT_CS;
|
| 523 |
|
|
Q_AMOD <= AMOD_ABS;
|
| 524 |
|
|
Q_BIT(3) <= I_OPC(9); -- set/clear
|
| 525 |
|
|
|
| 526 |
|
|
-- IMM = AAAAAA + 0x20
|
| 527 |
|
|
--
|
| 528 |
|
|
Q_IMM(4 downto 0) <= I_OPC(7 downto 3);
|
| 529 |
|
|
Q_IMM(6 downto 5) <= "01";
|
| 530 |
|
|
|
| 531 |
|
|
Q_RD_M <= I_T0;
|
| 532 |
|
|
if ((I_OPC(8) = '0') ) then -- CBI or SBI
|
| 533 |
|
|
Q_WE_M(0) <= '1';
|
| 534 |
|
|
else -- SBIC or SBIS
|
| 535 |
|
|
if (I_T0 = '0') then -- second cycle.
|
| 536 |
|
|
Q_PC_OP <= PC_SKIP_T;
|
| 537 |
|
|
end if;
|
| 538 |
|
|
end if;
|
| 539 |
|
|
|
| 540 |
|
|
when "100111" => -- MUL
|
| 541 |
|
|
--
|
| 542 |
|
|
-- 1001 11rd dddd rrrr - MUL
|
| 543 |
|
|
--
|
| 544 |
|
|
Q_ALU_OP <= ALU_MULT;
|
| 545 |
|
|
Q_IMM(7 downto 5) <= "000"; -- -MUL UU;
|
| 546 |
|
|
Q_WE_01 <= '1';
|
| 547 |
|
|
Q_WE_F <= '1';
|
| 548 |
|
|
|
| 549 |
|
|
when "101100" | "101101" =>
|
| 550 |
|
|
--
|
| 551 |
|
|
-- 1011 0AAd dddd AAAA - IN
|
| 552 |
|
|
--
|
| 553 |
|
|
Q_RSEL <= RS_DIN;
|
| 554 |
|
|
Q_AMOD <= AMOD_ABS;
|
| 555 |
|
|
|
| 556 |
|
|
-- IMM = AAAAAA
|
| 557 |
|
|
-- + 010000 (0x20)
|
| 558 |
|
|
Q_IMM(3 downto 0) <= I_OPC(3 downto 0);
|
| 559 |
|
|
Q_IMM(4) <= I_OPC(9);
|
| 560 |
|
|
Q_IMM(6 downto 5) <= "01" + ('0' & I_OPC(10 downto 10));
|
| 561 |
|
|
|
| 562 |
|
|
Q_WE_D <= "01";
|
| 563 |
|
|
|
| 564 |
|
|
when "101110" | "101111" =>
|
| 565 |
|
|
--
|
| 566 |
|
|
-- 1011 1AAr rrrr AAAA - OUT
|
| 567 |
|
|
--
|
| 568 |
|
|
Q_ALU_OP <= ALU_D_MV_Q;
|
| 569 |
|
|
Q_AMOD <= AMOD_ABS;
|
| 570 |
|
|
|
| 571 |
|
|
-- IMM = AAAAAA
|
| 572 |
|
|
-- + 010000 (0x20)
|
| 573 |
|
|
--
|
| 574 |
|
|
Q_IMM(3 downto 0) <= I_OPC(3 downto 0);
|
| 575 |
|
|
Q_IMM(4) <= I_OPC(9);
|
| 576 |
|
|
Q_IMM(6 downto 5) <= "01" + ('0' & I_OPC(10 downto 10));
|
| 577 |
|
|
Q_WE_M <= "01";
|
| 578 |
|
|
|
| 579 |
|
|
when "110000" | "110001" | "110010" | "110011" =>
|
| 580 |
|
|
--
|
| 581 |
|
|
-- 1100 kkkk kkkk kkkk - RJMP
|
| 582 |
|
|
--
|
| 583 |
|
|
Q_JADR <= I_PC + (I_OPC(11) & I_OPC(11) & I_OPC(11) & I_OPC(11)
|
| 584 |
|
|
& I_OPC(11 downto 0)) + X"0001";
|
| 585 |
|
|
Q_PC_OP <= PC_LD_I;
|
| 586 |
|
|
|
| 587 |
|
|
when "110100" | "110101" | "110110" | "110111" =>
|
| 588 |
|
|
--
|
| 589 |
|
|
-- 1101 kkkk kkkk kkkk - RCALL
|
| 590 |
|
|
--
|
| 591 |
|
|
Q_JADR <= I_PC + (I_OPC(11) & I_OPC(11) & I_OPC(11) & I_OPC(11)
|
| 592 |
|
|
& I_OPC(11 downto 0)) + X"0001";
|
| 593 |
|
|
Q_ALU_OP <= ALU_PC_1;
|
| 594 |
|
|
Q_AMOD <= AMOD_ddSP;
|
| 595 |
|
|
Q_PC_OP <= PC_LD_I;
|
| 596 |
|
|
Q_WE_M <= "11"; -- both PC bytes
|
| 597 |
|
|
Q_WE_XYZS <= '1';
|
| 598 |
|
|
|
| 599 |
|
|
when "111000" | "111001" | "111010" | "111011" => -- LDI
|
| 600 |
|
|
--
|
| 601 |
|
|
-- 1110 KKKK dddd KKKK - LDI Rd, K
|
| 602 |
|
|
--
|
| 603 |
|
|
Q_ALU_OP <= ALU_R_MV_Q;
|
| 604 |
|
|
Q_RSEL <= RS_IMM;
|
| 605 |
|
|
Q_DDDDD <= '1' & I_OPC(7 downto 4); -- 16..31
|
| 606 |
|
|
Q_IMM(7 downto 0) <= I_OPC(11 downto 8) & I_OPC(3 downto 0);
|
| 607 |
|
|
Q_WE_D <= "01";
|
| 608 |
|
|
|
| 609 |
|
|
when "111100" | "111101" =>
|
| 610 |
|
|
--
|
| 611 |
|
|
-- 1111 00kk kkkk kbbb - BRBS
|
| 612 |
|
|
-- 1111 01kk kkkk kbbb - BRBC
|
| 613 |
|
|
-- v
|
| 614 |
|
|
-- bbb: status register bit
|
| 615 |
|
|
-- v: value (set/cleared) of status register bit
|
| 616 |
|
|
--
|
| 617 |
|
|
Q_JADR <= I_PC + (I_OPC(9) & I_OPC(9) & I_OPC(9) & I_OPC(9)
|
| 618 |
|
|
& I_OPC(9) & I_OPC(9) & I_OPC(9) & I_OPC(9)
|
| 619 |
|
|
& I_OPC(9) & I_OPC(9 downto 3)) + X"0001";
|
| 620 |
|
|
Q_PC_OP <= PC_BCC;
|
| 621 |
|
|
|
| 622 |
|
|
when "111110" =>
|
| 623 |
|
|
--
|
| 624 |
|
|
-- 1111 100d dddd 0bbb - BLD
|
| 625 |
|
|
-- 1111 101d dddd 0bbb - BST
|
| 626 |
|
|
--
|
| 627 |
|
|
if I_OPC(9) = '0' then -- BLD: T flag to register
|
| 628 |
|
|
Q_ALU_OP <= ALU_BLD;
|
| 629 |
|
|
Q_WE_D <= "01";
|
| 630 |
|
|
else -- BST: register to T flag
|
| 631 |
|
|
Q_AMOD <= AMOD_ABS;
|
| 632 |
|
|
Q_BIT(3) <= I_OPC(10);
|
| 633 |
|
|
Q_IMM(4 downto 0) <= I_OPC(8 downto 4);
|
| 634 |
|
|
Q_ALU_OP <= ALU_BIT_CS;
|
| 635 |
|
|
Q_WE_F <= '1';
|
| 636 |
|
|
end if;
|
| 637 |
|
|
|
| 638 |
|
|
when "111111" =>
|
| 639 |
|
|
--
|
| 640 |
|
|
-- 1111 110r rrrr 0bbb - SBRC
|
| 641 |
|
|
-- 1111 111r rrrr 0bbb - SBRS
|
| 642 |
|
|
--
|
| 643 |
|
|
-- like SBIC, but and general purpose regs instead of I/O regs.
|
| 644 |
|
|
--
|
| 645 |
|
|
Q_ALU_OP <= ALU_BIT_CS;
|
| 646 |
|
|
Q_AMOD <= AMOD_ABS;
|
| 647 |
|
|
Q_BIT(3) <= I_OPC(9); -- set/clear bit
|
| 648 |
|
|
Q_IMM(4 downto 0) <= I_OPC(8 downto 4);
|
| 649 |
|
|
if (I_T0 = '0') then
|
| 650 |
|
|
Q_PC_OP <= PC_SKIP_T;
|
| 651 |
|
|
end if;
|
| 652 |
|
|
|
| 653 |
|
|
when others =>
|
| 654 |
|
|
end case;
|
| 655 |
|
|
end if;
|
| 656 |
|
|
end process;
|
| 657 |
|
|
|
| 658 |
|
|
end Behavioral;
|
| 659 |
|
|
|
