1 |
2 |
jsauermann |
-------------------------------------------------------------------------------
|
2 |
|
|
--
|
3 |
|
|
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
|
4 |
|
|
--
|
5 |
|
|
-- This code is free software: you can redistribute it and/or modify
|
6 |
|
|
-- it under the terms of the GNU General Public License as published by
|
7 |
|
|
-- the Free Software Foundation, either version 3 of the License, or
|
8 |
|
|
-- (at your option) any later version.
|
9 |
|
|
--
|
10 |
|
|
-- This code is distributed in the hope that it will be useful,
|
11 |
|
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
12 |
|
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
13 |
|
|
-- GNU General Public License for more details.
|
14 |
|
|
--
|
15 |
|
|
-- You should have received a copy of the GNU General Public License
|
16 |
|
|
-- along with this code (see the file named COPYING).
|
17 |
|
|
-- If not, see http://www.gnu.org/licenses/.
|
18 |
|
|
--
|
19 |
|
|
-------------------------------------------------------------------------------
|
20 |
|
|
-------------------------------------------------------------------------------
|
21 |
|
|
--
|
22 |
|
|
-- Module Name: opc_fetch - Behavioral
|
23 |
|
|
-- Create Date: 13:00:44 10/30/2009
|
24 |
|
|
-- Description: the opcode fetch stage of a CPU.
|
25 |
|
|
--
|
26 |
|
|
-------------------------------------------------------------------------------
|
27 |
|
|
--
|
28 |
|
|
library IEEE;
|
29 |
|
|
use IEEE.std_logic_1164.ALL;
|
30 |
|
|
use IEEE.std_logic_ARITH.ALL;
|
31 |
|
|
use IEEE.std_logic_UNSIGNED.ALL;
|
32 |
|
|
|
33 |
|
|
entity opc_fetch is
|
34 |
|
|
port ( I_CLK : in std_logic;
|
35 |
|
|
|
36 |
|
|
I_CLR : in std_logic;
|
37 |
|
|
I_INTVEC : in std_logic_vector( 5 downto 0);
|
38 |
|
|
I_LOAD_PC : in std_logic;
|
39 |
|
|
I_NEW_PC : in std_logic_vector(15 downto 0);
|
40 |
|
|
I_PM_ADR : in std_logic_vector(11 downto 0);
|
41 |
|
|
I_SKIP : in std_logic;
|
42 |
|
|
|
43 |
|
|
Q_OPC : out std_logic_vector(31 downto 0);
|
44 |
|
|
Q_PC : out std_logic_vector(15 downto 0);
|
45 |
|
|
Q_PM_DOUT : out std_logic_vector( 7 downto 0);
|
46 |
|
|
Q_T0 : out std_logic);
|
47 |
|
|
end opc_fetch;
|
48 |
|
|
|
49 |
|
|
architecture Behavioral of opc_fetch is
|
50 |
|
|
|
51 |
|
|
component prog_mem
|
52 |
|
|
port ( I_CLK : in std_logic;
|
53 |
|
|
|
54 |
|
|
I_WAIT : in std_logic;
|
55 |
|
|
I_PC : in std_logic_vector (15 downto 0);
|
56 |
|
|
I_PM_ADR : in std_logic_vector (11 downto 0);
|
57 |
|
|
|
58 |
|
|
Q_OPC : out std_logic_vector (31 downto 0);
|
59 |
|
|
Q_PC : out std_logic_vector (15 downto 0);
|
60 |
|
|
Q_PM_DOUT : out std_logic_vector ( 7 downto 0));
|
61 |
|
|
end component;
|
62 |
|
|
|
63 |
|
|
signal P_OPC : std_logic_vector(31 downto 0);
|
64 |
|
|
signal P_PC : std_logic_vector(15 downto 0);
|
65 |
|
|
|
66 |
|
|
signal L_INVALIDATE : std_logic;
|
67 |
|
|
signal L_LONG_OP : std_logic;
|
68 |
|
|
signal L_NEXT_PC : std_logic_vector(15 downto 0);
|
69 |
19 |
jsauermann |
signal L_OPC_1_0123 : std_logic;
|
70 |
|
|
signal L_OPC_8A_014589CD: std_logic;
|
71 |
|
|
signal L_OPC_9_01 : std_logic;
|
72 |
|
|
signal L_OPC_9_5_01_8 : std_logic;
|
73 |
|
|
signal L_OPC_9_5_CD_8 : std_logic;
|
74 |
|
|
signal L_OPC_9_9B : std_logic;
|
75 |
|
|
signal L_OPC_F_CDEF : std_logic;
|
76 |
2 |
jsauermann |
signal L_PC : std_logic_vector(15 downto 0);
|
77 |
|
|
signal L_T0 : std_logic;
|
78 |
|
|
signal L_WAIT : std_logic;
|
79 |
|
|
|
80 |
|
|
begin
|
81 |
|
|
|
82 |
|
|
pmem : prog_mem
|
83 |
|
|
port map( I_CLK => I_CLK,
|
84 |
|
|
|
85 |
|
|
I_WAIT => L_WAIT,
|
86 |
|
|
I_PC => L_NEXT_PC,
|
87 |
|
|
I_PM_ADR => I_PM_ADR,
|
88 |
|
|
|
89 |
|
|
Q_OPC => P_OPC,
|
90 |
|
|
Q_PC => P_PC,
|
91 |
|
|
Q_PM_DOUT => Q_PM_DOUT);
|
92 |
|
|
|
93 |
|
|
lpc: process(I_CLK)
|
94 |
|
|
begin
|
95 |
|
|
if (rising_edge(I_CLK)) then
|
96 |
|
|
L_PC <= L_NEXT_PC;
|
97 |
|
|
L_T0 <= not L_WAIT;
|
98 |
|
|
end if;
|
99 |
|
|
end process;
|
100 |
|
|
|
101 |
|
|
L_NEXT_PC <= X"0000" when (I_CLR = '1')
|
102 |
|
|
else L_PC when (L_WAIT = '1')
|
103 |
|
|
else I_NEW_PC when (I_LOAD_PC = '1')
|
104 |
|
|
else L_PC + X"0002" when (L_LONG_OP = '1')
|
105 |
|
|
else L_PC + X"0001";
|
106 |
|
|
|
107 |
|
|
-- Two word opcodes:
|
108 |
|
|
--
|
109 |
|
|
-- 9 3210
|
110 |
|
|
-- 1001 000d dddd 0000 kkkk kkkk kkkk kkkk - LDS
|
111 |
|
|
-- 1001 001d dddd 0000 kkkk kkkk kkkk kkkk - SDS
|
112 |
|
|
-- 1001 010k kkkk 110k kkkk kkkk kkkk kkkk - JMP
|
113 |
|
|
-- 1001 010k kkkk 111k kkkk kkkk kkkk kkkk - CALL
|
114 |
|
|
--
|
115 |
|
|
L_LONG_OP <= '1' when (((P_OPC(15 downto 9) = "1001010") and
|
116 |
|
|
(P_OPC( 3 downto 2) = "11")) -- JMP, CALL
|
117 |
|
|
or ((P_OPC(15 downto 10) = "100100") and
|
118 |
|
|
(P_OPC( 3 downto 0) = "0000"))) -- LDS, STS
|
119 |
|
|
else '0';
|
120 |
|
|
|
121 |
19 |
jsauermann |
----------------------------------
|
122 |
|
|
-- Two cycle opcodes... --
|
123 |
|
|
----------------------------------
|
124 |
|
|
|
125 |
|
|
-------------------------------------------------
|
126 |
|
|
-- 0001 00rd dddd rrrr - CPSE
|
127 |
2 |
jsauermann |
--
|
128 |
19 |
jsauermann |
L_OPC_1_0123 <= '1' when (P_OPC(15 downto 10) = "000100" )
|
129 |
|
|
else '0';
|
130 |
|
|
|
131 |
|
|
-------------------------------------------------
|
132 |
|
|
-- 10q0 qq0d dddd 1qqq - LDD (Y + q)
|
133 |
|
|
-- 10q0 qq0d dddd 0qqq - LDD (Z + q)
|
134 |
2 |
jsauermann |
--
|
135 |
19 |
jsauermann |
L_OPC_8A_014589CD <= '1' when ((P_OPC(15 downto 14) = "10" )
|
136 |
|
|
and (P_OPC(12) = '0')
|
137 |
|
|
and (P_OPC( 9) = '0'))
|
138 |
|
|
else '0';
|
139 |
2 |
jsauermann |
|
140 |
19 |
jsauermann |
-------------------------------------------------
|
141 |
|
|
-- 1001 000d dddd .... - LDS, LD, LPM (ii/iii), ELPM, POP
|
142 |
|
|
--
|
143 |
|
|
L_OPC_9_01 <= '1' when ( P_OPC(15 downto 9) = "1001000")
|
144 |
|
|
else '0';
|
145 |
18 |
jsauermann |
|
146 |
19 |
jsauermann |
-------------------------------------------------
|
147 |
|
|
-- 1001 0101 0000 1000 - RET
|
148 |
|
|
-- 1001 0101 0001 1000 - RETI
|
149 |
|
|
--
|
150 |
|
|
L_OPC_9_5_01_8 <= '1' when ((P_OPC(15 downto 5) = "10010101000")
|
151 |
|
|
and (P_OPC( 3 downto 0) = "1000"))
|
152 |
|
|
else '0';
|
153 |
|
|
|
154 |
|
|
-------------------------------------------------
|
155 |
|
|
-- 1001 0101 1100 1000 - LPM (i)
|
156 |
|
|
-- 1001 0101 1101 1000 - ELPM
|
157 |
|
|
--
|
158 |
|
|
L_OPC_9_5_CD_8 <= '1' when ((P_OPC(15 downto 5) = "10010101110")
|
159 |
|
|
and (P_OPC( 3 downto 0) = "1000"))
|
160 |
|
|
else '0';
|
161 |
|
|
|
162 |
|
|
-------------------------------------------------
|
163 |
|
|
-- 1001 1001 AAAA Abbb - SBIC
|
164 |
|
|
-- 1001 1011 AAAA Abbb - SBIS
|
165 |
|
|
--
|
166 |
|
|
L_OPC_9_9B <= '1' when ((P_OPC(15 downto 10) = "100110")
|
167 |
|
|
and (P_OPC(8) = '1'))
|
168 |
|
|
else '0';
|
169 |
|
|
|
170 |
|
|
-------------------------------------------------
|
171 |
|
|
-- 1111 110r rrrr 0bbb - SBRC
|
172 |
|
|
-- 1111 111r rrrr 0bbb - SBRS
|
173 |
|
|
--
|
174 |
|
|
L_OPC_F_CDEF <= '1' when ( P_OPC(15 downto 10) = "111111")
|
175 |
|
|
else '0';
|
176 |
|
|
|
177 |
|
|
L_WAIT <= L_T0 and (not L_INVALIDATE)
|
178 |
|
|
and (not I_INTVEC(5))
|
179 |
|
|
and (L_OPC_1_0123 or -- CPSE
|
180 |
|
|
L_OPC_8A_014589CD or -- LDD
|
181 |
|
|
L_OPC_9_01 or -- LDS, LD, LPM, POP
|
182 |
|
|
L_OPC_9_5_01_8 or -- RET, RETI
|
183 |
|
|
L_OPC_9_5_CD_8 or -- LPM, ELPM
|
184 |
|
|
L_OPC_9_9B or -- SBIC, SBIS
|
185 |
|
|
L_OPC_F_CDEF); -- SBRC, SBRS
|
186 |
|
|
|
187 |
2 |
jsauermann |
L_INVALIDATE <= I_CLR or I_SKIP;
|
188 |
|
|
|
189 |
|
|
Q_OPC <= X"00000000" when (L_INVALIDATE = '1')
|
190 |
|
|
else P_OPC when (I_INTVEC(5) = '0')
|
191 |
|
|
else (X"000000" & "00" & I_INTVEC); -- "interrupt opcode"
|
192 |
|
|
|
193 |
|
|
Q_PC <= P_PC;
|
194 |
|
|
Q_T0 <= L_T0;
|
195 |
|
|
|
196 |
|
|
end Behavioral;
|
197 |
|
|
|