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jsauermann |
-------------------------------------------------------------------------------
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--
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-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
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--
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-- This code is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this code (see the file named COPYING).
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-- If not, see http://www.gnu.org/licenses/.
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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-- Create Date: 14:22:28 11/07/2009
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-- Design Name:
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-- Module Name: uart_rx - Behavioral
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-- Description: a UART receiver.
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--
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-------------------------------------------------------------------------------
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity uart_rx is
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PORT( I_CLK : in std_logic;
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I_CLR : in std_logic;
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I_CE_16 : in std_logic; -- 16 times baud rate
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I_RX : in std_logic; -- Serial input line
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Q_DATA : out std_logic_vector(7 downto 0);
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Q_FLAG : out std_logic); -- toggle on every byte received
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end uart_rx;
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architecture Behavioral of uart_rx is
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signal L_POSITION : std_logic_vector(7 downto 0); -- sample position
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signal L_BUF : std_logic_vector(9 downto 0);
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signal L_FLAG : std_logic;
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signal L_SERIN : std_logic; -- double clock the input
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signal L_SER_HOT : std_logic; -- double clock the input
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begin
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-- double clock the input data...
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--
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process(I_CLK)
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begin
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if (rising_edge(I_CLK)) then
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if (I_CLR = '1') then
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L_SERIN <= '1';
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L_SER_HOT <= '1';
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else
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L_SERIN <= I_RX;
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L_SER_HOT <= L_SERIN;
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end if;
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end if;
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end process;
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process(I_CLK, L_POSITION)
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variable START_BIT : boolean;
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variable STOP_BIT : boolean;
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variable STOP_POS : boolean;
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begin
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START_BIT := L_POSITION(7 downto 4) = X"0";
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STOP_BIT := L_POSITION(7 downto 4) = X"9";
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STOP_POS := STOP_BIT and L_POSITION(3 downto 2) = "11"; -- 3/4 of stop bit
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if (rising_edge(I_CLK)) then
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if (I_CLR = '1') then
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L_FLAG <= '0';
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L_POSITION <= X"00"; -- idle
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L_BUF <= "1111111111";
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Q_DATA <= "00000000";
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elsif (I_CE_16 = '1') then
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if (L_POSITION = X"00") then -- uart idle
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L_BUF <= "1111111111";
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if (L_SER_HOT = '0') then -- start bit received
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L_POSITION <= X"01";
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end if;
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else
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L_POSITION <= L_POSITION + X"01";
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if (L_POSITION(3 downto 0) = "0111") then -- 1/2 bit
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L_BUF <= L_SER_HOT & L_BUF(9 downto 1); -- sample data
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--
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-- validate start bit
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--
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if (START_BIT and L_SER_HOT = '1') then -- 1/2 start bit
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L_POSITION <= X"00";
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end if;
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if (STOP_BIT) then -- 1/2 stop bit
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Q_DATA <= L_BUF(9 downto 2);
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end if;
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elsif (STOP_POS) then -- 3/4 stop bit
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L_FLAG <= L_FLAG xor (L_BUF(9) and not L_BUF(0));
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L_POSITION <= X"00";
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end if;
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end if;
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end if;
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end if;
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end process;
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Q_FLAG <= L_FLAG;
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end Behavioral;
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