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[/] [cpu_lecture/] [trunk/] [test/] [test_tb.vhd] - Blame information for rev 21

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1 2 jsauermann
-------------------------------------------------------------------------------
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-- 
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-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
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-- 
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--  This code is free software: you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation, either version 3 of the License, or
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--  (at your option) any later version.
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--
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--  This code is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details.
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--
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--  You should have received a copy of the GNU General Public License
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--  along with this code (see the file named COPYING).
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--  If not, see http://www.gnu.org/licenses/.
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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-- Module Name:    alu - Behavioral 
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-- Create Date:    16:47:24 12/29/2009 
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-- Description:    arithmetic logic unit of a CPU
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--
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-------------------------------------------------------------------------------
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity testbench is
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end testbench;
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architecture Behavioral of testbench is
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component avr_fpga
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    port (  I_CLK_100   : in  std_logic;
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            I_SWITCH    : in  std_logic_vector(9 downto 0);
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            I_RX        : in  std_logic;
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            Q_7_SEGMENT : out std_logic_vector(6 downto 0);
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            Q_LEDS      : out std_logic_vector(3 downto 0);
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            Q_TX        : out std_logic);
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end component;
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signal L_CLK_100            : std_logic;
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signal L_LEDS               : std_logic_vector(3 downto 0);
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signal L_7_SEGMENT          : std_logic_vector(6 downto 0);
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signal L_RX                 : std_logic;
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signal L_SWITCH             : std_logic_vector(9 downto 0);
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signal L_TX                 : std_logic;
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signal  L_CLK_COUNT         : integer := 0;
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begin
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    fpga: avr_fpga
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    port map(   I_CLK_100   => L_CLK_100,
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                I_SWITCH    => L_SWITCH,
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                I_RX        => L_RX,
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                Q_LEDS      => L_LEDS,
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                Q_7_SEGMENT => L_7_SEGMENT,
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                Q_TX        => L_TX);
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    process -- clock process for CLK_100,
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    begin
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        clock_loop : loop
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            L_CLK_100 <= transport '0';
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            wait for 5 ns;
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            L_CLK_100 <= transport '1';
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            wait for 5 ns;
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        end loop clock_loop;
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    end process;
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    process(L_CLK_100)
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    begin
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        if (rising_edge(L_CLK_100)) then
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            case L_CLK_COUNT is
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                when 0 => L_SWITCH <= "0011100000";   L_RX <= '0';
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                when 2 => L_SWITCH(9 downto 8) <= "11";
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                when others =>
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            end case;
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            L_CLK_COUNT <= L_CLK_COUNT + 1;
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        end if;
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    end process;
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end Behavioral;
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