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5 |
kfleming |
=== Generated schedule for mkBRAMFeeder ===
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| 2 |
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| 3 |
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Method schedule
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| 4 |
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---------------
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| 5 |
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Method: ppcMessageInput_put
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Ready signal: ppcMesgQ.i_notFull && ppcMesgQ.notFull
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| 7 |
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Conflict-free: bramInitiatorWires_bramCLK,
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| 8 |
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bramInitiatorWires_bramRST,
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| 9 |
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bramInitiatorWires_bramAddr,
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| 10 |
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bramInitiatorWires_bramDout,
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| 11 |
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bramInitiatorWires_bramDin,
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bramInitiatorWires_bramWEN,
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bramInitiatorWires_bramEN
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Sequenced before (restricted): ppcMessageOutput_get
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Conflicts: ppcMessageInput_put
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| 16 |
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Method: ppcMessageOutput_get
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Ready signal: ppcInstQ.notEmpty && ppcInstQ.i_notEmpty
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Conflict-free: bramInitiatorWires_bramCLK,
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bramInitiatorWires_bramRST,
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bramInitiatorWires_bramAddr,
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bramInitiatorWires_bramDout,
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bramInitiatorWires_bramDin,
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bramInitiatorWires_bramWEN,
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bramInitiatorWires_bramEN
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Sequenced after (restricted): ppcMessageInput_put
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Conflicts: ppcMessageOutput_get
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Method: bramInitiatorWires_bramCLK
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Ready signal: True
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Conflict-free: ppcMessageInput_put,
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ppcMessageOutput_get,
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bramInitiatorWires_bramCLK,
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bramInitiatorWires_bramRST,
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bramInitiatorWires_bramAddr,
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bramInitiatorWires_bramDout,
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bramInitiatorWires_bramDin,
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bramInitiatorWires_bramWEN,
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bramInitiatorWires_bramEN
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Method: bramInitiatorWires_bramRST
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Ready signal: True
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Conflict-free: ppcMessageInput_put,
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| 44 |
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ppcMessageOutput_get,
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bramInitiatorWires_bramCLK,
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| 46 |
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bramInitiatorWires_bramRST,
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| 47 |
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bramInitiatorWires_bramAddr,
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bramInitiatorWires_bramDout,
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bramInitiatorWires_bramDin,
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bramInitiatorWires_bramWEN,
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bramInitiatorWires_bramEN
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| 52 |
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| 53 |
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Method: bramInitiatorWires_bramAddr
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Ready signal: True
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Conflict-free: ppcMessageInput_put,
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ppcMessageOutput_get,
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bramInitiatorWires_bramCLK,
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bramInitiatorWires_bramRST,
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bramInitiatorWires_bramAddr,
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| 60 |
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bramInitiatorWires_bramDout,
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| 61 |
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bramInitiatorWires_bramDin,
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| 62 |
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bramInitiatorWires_bramWEN,
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| 63 |
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bramInitiatorWires_bramEN
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| 64 |
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| 65 |
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Method: bramInitiatorWires_bramDout
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| 66 |
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Ready signal: True
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| 67 |
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Conflict-free: ppcMessageInput_put,
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| 68 |
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ppcMessageOutput_get,
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bramInitiatorWires_bramCLK,
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| 70 |
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bramInitiatorWires_bramRST,
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| 71 |
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bramInitiatorWires_bramAddr,
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bramInitiatorWires_bramDout,
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| 73 |
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bramInitiatorWires_bramDin,
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| 74 |
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bramInitiatorWires_bramWEN,
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bramInitiatorWires_bramEN
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Method: bramInitiatorWires_bramDin
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Ready signal: True
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Conflict-free: ppcMessageInput_put,
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ppcMessageOutput_get,
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bramInitiatorWires_bramCLK,
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| 82 |
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bramInitiatorWires_bramRST,
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bramInitiatorWires_bramAddr,
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bramInitiatorWires_bramDout,
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bramInitiatorWires_bramDin,
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| 86 |
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bramInitiatorWires_bramWEN,
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| 87 |
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bramInitiatorWires_bramEN
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| 88 |
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Method: bramInitiatorWires_bramWEN
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Ready signal: True
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Conflict-free: ppcMessageInput_put,
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| 92 |
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ppcMessageOutput_get,
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bramInitiatorWires_bramCLK,
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| 94 |
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bramInitiatorWires_bramRST,
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| 95 |
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bramInitiatorWires_bramAddr,
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| 96 |
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bramInitiatorWires_bramDout,
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| 97 |
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bramInitiatorWires_bramDin,
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| 98 |
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bramInitiatorWires_bramWEN,
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bramInitiatorWires_bramEN
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| 100 |
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| 101 |
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Method: bramInitiatorWires_bramEN
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Ready signal: True
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| 103 |
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Conflict-free: ppcMessageInput_put,
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| 104 |
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ppcMessageOutput_get,
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bramInitiatorWires_bramCLK,
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| 106 |
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bramInitiatorWires_bramRST,
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| 107 |
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bramInitiatorWires_bramAddr,
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| 108 |
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bramInitiatorWires_bramDout,
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| 109 |
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bramInitiatorWires_bramDin,
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| 110 |
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bramInitiatorWires_bramWEN,
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| 111 |
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bramInitiatorWires_bramEN
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Rule schedule
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-------------
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Rule: inStartPush
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Predicate: state == 4'd7
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Blocking rules: (none)
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| 119 |
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Rule: inStartWrite
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| 120 |
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Predicate: bramInit_bramFlat.RDY_read_resp && ppcMesgQ.i_notEmpty &&
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(state == 4'd6)
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Blocking rules: ppcMessageInput_put
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Rule: inStartCheckWrite
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Predicate: bramInit_bramFlat.RDY_read_req && (state == 4'd5)
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| 126 |
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Blocking rules: (none)
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| 127 |
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| 128 |
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Rule: inStartTake
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| 129 |
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Predicate: bramInit_bramFlat.RDY_read_resp && ppcInstQ.i_notFull &&
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(state == 4'd4)
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Blocking rules: ppcMessageInput_put
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| 132 |
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| 133 |
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Rule: inStartRead
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| 134 |
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Predicate: bramInit_bramFlat.RDY_read_resp &&
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bramInit_bramFlat.RDY_read_req &&
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(state == 4'd3)
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Blocking rules: (none)
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| 138 |
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| 139 |
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Rule: inStartCheckRead
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| 140 |
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Predicate: bramInit_bramFlat.RDY_read_req && (state == 4'd2)
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| 141 |
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Blocking rules: (none)
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| 142 |
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| 143 |
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Rule: inStartIdle
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Predicate: state == 4'd1
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Blocking rules: (none)
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| 147 |
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Rule: beat
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| 148 |
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Predicate: (! (heartbeat == 30'd1073741823)) || ppcMesgQ.i_notFull
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| 149 |
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Blocking rules: ppcMessageInput_put
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| 150 |
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| 151 |
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Logical execution order: bramInitiatorWires_bramEN,
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bramInitiatorWires_bramWEN,
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bramInitiatorWires_bramDin,
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| 154 |
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bramInitiatorWires_bramDout,
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| 155 |
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bramInitiatorWires_bramAddr,
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| 156 |
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bramInitiatorWires_bramRST,
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| 157 |
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bramInitiatorWires_bramCLK,
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| 158 |
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inStartRead,
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inStartIdle,
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ppcMessageInput_put,
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inStartPush,
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inStartWrite,
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ppcMessageOutput_get,
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inStartCheckWrite,
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inStartTake,
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inStartCheckRead,
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beat
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============================================
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