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[/] [cryptosorter/] [trunk/] [lib/] [bsv/] [PLBMaster/] [build/] [Makefile] - Blame information for rev 5

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Line No. Rev Author Line
1 5 kfleming
#/*
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#Copyright (c) 2008 MIT
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#
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#Permission is hereby granted, free of charge, to any person
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#obtaining a copy of this software and associated documentation
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#files (the "Software"), to deal in the Software without
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#restriction, including without limitation the rights to use,
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#copy, modify, merge, publish, distribute, sublicense, and/or sell
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#copies of the Software, and to permit persons to whom the
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#Software is furnished to do so, subject to the following
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#conditions:
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#
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#The above copyright notice and this permission notice shall be
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#included in all copies or substantial portions of the Software.
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#
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#THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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#EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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#OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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#NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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#HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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#WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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#FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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#OTHER DEALINGS IN THE SOFTWARE.
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#
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#Author: Kermin Fleming
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#*/
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srcdir = ../src
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debugdir = ../../Debug
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testdir = ../test
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commondir = ../common
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bramdir = ../../BRAM/
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feederdir = ../../BRAMFeeder/src
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fpgadir = ../fpga
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bdir = build/bdir
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vdir = build/vdir
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cdir = build/cdir
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simdir = build/simdir
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BSC = bsc
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VER_OPTS =  +RTS -K100000000 --RTS -u -v -verilog -aggressive-conditions -vdir ./
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SIM_OPTS =  +RTS -K100000000 --RTS -u -v -sim -aggressive-conditions -show-schedule
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EXE_OPTS =  +RTS -K100000000 --RTS -sim
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#--------------------------------------------------------------------
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# Build targets
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#--------------------------------------------------------------------
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build:
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        mkdir -p build
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        mkdir -p $(bdir)
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        mkdir -p $(vdir)
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        mkdir -p $(cdir)
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        mkdir -p $(simdir)
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plbmaster : build
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        $(BSC) $(VER_OPTS) -D PLB_DEFAULTS=0  -bdir $(bdir) -vdir $(vdir) -p +:$(srcdir):$(bramdir):$(debugdir):$(commondir):$(feederdir):$(bdir) -g mkPLBMaster $(srcdir)/PLBMaster.bsv > out.log
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plbtester_verilog : build
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        $(BSC) $(VER_OPTS) -D PLB_DEFAULTS=0 -bdir $(bdir) -vdir $(vdir) -p +:$(srcdir):$(bramdir):$(debugdir):$(commondir):$(feederdir):$(bdir):$(fpgadir) -g mkPLBMasterTester $(fpgadir)/PLBMasterTester.bsv > out.log
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clean :
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        rm -rf build

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