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3 |
kfleming |
=== Generated schedule for mkBRAMLevel4MergerInstance ===
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Method schedule
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---------------
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Method: inStream_getTokInfo
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Ready signal: res_inFstHalf_finishInit && res_inSndHalf_finishInit
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Conflict-free: inStream_getTokInfo,
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inStream_putDeqTok,
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inStream_putRecord,
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outStream_putTokInfo,
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11 |
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outStream_getDeqTok_fst,
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outStream_getDeqTok_snd,
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outStream_getRecord_fst,
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outStream_getRecord_snd
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Method: inStream_putDeqTok
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Ready signal: res_inSndHalf_finishInit && res_inFstHalf_finishInit
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Conflict-free: inStream_getTokInfo,
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inStream_putRecord,
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outStream_putTokInfo,
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outStream_getDeqTok_fst,
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outStream_getDeqTok_snd,
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outStream_getRecord_fst,
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outStream_getRecord_snd
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Conflicts: inStream_putDeqTok
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Method: inStream_putRecord
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Ready signal: res_inSndHalf_finishInit && res_inFstHalf_finishInit
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Conflict-free: inStream_getTokInfo,
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inStream_putDeqTok,
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outStream_putTokInfo,
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outStream_getDeqTok_fst,
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outStream_getDeqTok_snd,
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outStream_getRecord_fst,
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outStream_getRecord_snd
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Conflicts: inStream_putRecord
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Method: outStream_putTokInfo
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Ready signal: True
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Conflict-free: inStream_getTokInfo,
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inStream_putDeqTok,
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inStream_putRecord,
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outStream_getRecord_fst,
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outStream_getRecord_snd
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Sequenced before (restricted): outStream_getDeqTok_fst,
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outStream_getDeqTok_snd
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Conflicts: outStream_putTokInfo
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Method: outStream_getDeqTok_fst
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Ready signal: res_getDeqTokW.whas && res_getDeqTokW.wget[3]
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Conflict-free: inStream_getTokInfo,
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inStream_putDeqTok,
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inStream_putRecord,
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outStream_getDeqTok_fst,
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outStream_getDeqTok_snd,
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outStream_getRecord_fst,
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outStream_getRecord_snd
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Sequenced after (restricted): outStream_putTokInfo
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Method: outStream_getDeqTok_snd
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Ready signal: res_getDeqTokW.whas && res_getDeqTokW.wget[3]
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Conflict-free: inStream_getTokInfo,
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inStream_putDeqTok,
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inStream_putRecord,
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outStream_getDeqTok_fst,
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outStream_getDeqTok_snd,
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outStream_getRecord_fst,
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outStream_getRecord_snd
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Sequenced after (restricted): outStream_putTokInfo
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Method: outStream_getRecord_fst
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Ready signal: res_outW.whas && res_outW.wget[132]
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Conflict-free: inStream_getTokInfo,
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inStream_putDeqTok,
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inStream_putRecord,
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outStream_putTokInfo,
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outStream_getDeqTok_fst,
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outStream_getDeqTok_snd,
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outStream_getRecord_fst,
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outStream_getRecord_snd
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Method: outStream_getRecord_snd
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Ready signal: res_outW.whas && res_outW.wget[132]
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Conflict-free: inStream_getTokInfo,
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inStream_putDeqTok,
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inStream_putRecord,
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outStream_putTokInfo,
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outStream_getDeqTok_fst,
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outStream_getDeqTok_snd,
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outStream_getRecord_fst,
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outStream_getRecord_snd
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Rule schedule
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-------------
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Rule: res_compares
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Predicate: res_inFstHalf_ugbram_bram.RDY_read_resp &&
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res_inSndHalf_ugbram_bram.RDY_read_resp &&
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res_inFstHalf_finishInit &&
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res_inSndHalf_finishInit && res_reqQ.i_notEmpty
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Blocking rules: (none)
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Rule: res_nextToProcess
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Predicate: res_inFstHalf_finishInit &&
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res_inSndHalf_finishInit &&
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((! res_scheduler_getNextW.whas) ||
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(! res_scheduler_getNextW.wget[3]) ||
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res_reqQ.i_notFull)
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Blocking rules: (none)
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Rule: res_feedScheduler
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Predicate: (((res_nextTokW.whas
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? res_nextTokW.wget[2:0]
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: _) ==
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3'd0) ||
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res_inFstHalf_finishInit) &&
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(((res_nextTokW.whas
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? res_nextTokW.wget[2:0]
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: _) ==
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3'd0) ||
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(((res_scheduler_last[3]
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? res_scheduler_last[2:0]
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: _) ==
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3'd0)
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? res_scheduler_last[3] ||
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(res_inFstHalf_usedReg_dataReg[2:0] == 3'd0)
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: (res_inFstHalf_usedReg_dataReg[2:0] == 3'd0)) ||
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res_inSndHalf_finishInit) &&
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(((! ((res_nextTokW.whas
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? res_nextTokW.wget[2:0]
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: _) ==
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3'd0)) &&
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132 |
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(((res_scheduler_last[3]
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? res_scheduler_last[2:0]
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: _) ==
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3'd0)
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? (! res_scheduler_last[3]) &&
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(((res_scheduler_last[3]
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? res_scheduler_last[2:0]
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: _) ==
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3'd0)
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? ! (res_inFstHalf_usedReg_dataReg[2:0] == 3'd0)
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: (((res_scheduler_last[3]
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? res_scheduler_last[2:0]
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: _) ==
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145 |
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3'd1)
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? ! (res_inFstHalf_usedReg_dataReg[5:3] == 3'd0)
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: (((res_scheduler_last[3]
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? res_scheduler_last[2:0]
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: _) ==
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3'd2)
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? ! (res_inFstHalf_usedReg_dataReg[8:6] == 3'd0)
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: (((res_scheduler_last[3]
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? res_scheduler_last[2:0]
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154 |
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: _) ==
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3'd3)
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156 |
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? ! (res_inFstHalf_usedReg_dataReg[11:9] == 3'd0)
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157 |
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: (((res_scheduler_last[3]
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158 |
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? res_scheduler_last[2:0]
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159 |
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: _) ==
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160 |
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3'd4)
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161 |
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? ! (res_inFstHalf_usedReg_dataReg[14:12] ==
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162 |
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3'd0)
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163 |
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: (((res_scheduler_last[3]
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164 |
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? res_scheduler_last[2:0]
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165 |
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: _) ==
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166 |
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3'd5)
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167 |
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? ! (res_inFstHalf_usedReg_dataReg[17:15] ==
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168 |
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3'd0)
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169 |
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: (((res_scheduler_last[3]
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170 |
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? res_scheduler_last[2:0]
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171 |
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: _) ==
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3'd6)
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173 |
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? ! (res_inFstHalf_usedReg_dataReg[20:18] ==
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174 |
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3'd0)
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175 |
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: (((res_scheduler_last[3]
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176 |
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? res_scheduler_last[2:0]
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177 |
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: _) ==
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178 |
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3'd7)
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179 |
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? ! (res_inFstHalf_usedReg_dataReg[23:21] ==
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180 |
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3'd0)
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181 |
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: _))))))))
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182 |
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: (! (res_inFstHalf_usedReg_dataReg[2:0] == 3'd0))) &&
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(! (res_inSndHalf_usedReg_dataReg[2:0] == 3'd0)))
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184 |
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? res_inFstHalf_finishInit && res_inSndHalf_finishInit
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185 |
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: ((((res_nextTokW.whas
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186 |
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? res_nextTokW.wget[5:3]
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187 |
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: _) ==
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188 |
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3'd0) ||
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189 |
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res_inFstHalf_finishInit) &&
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190 |
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(((res_nextTokW.whas
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191 |
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? res_nextTokW.wget[5:3]
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192 |
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: _) ==
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193 |
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3'd0) ||
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194 |
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(((res_scheduler_last[3]
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195 |
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? res_scheduler_last[2:0]
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196 |
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: _) ==
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197 |
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3'd1)
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198 |
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? res_scheduler_last[3] ||
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199 |
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(res_inFstHalf_usedReg_dataReg[5:3] == 3'd0)
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200 |
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: (res_inFstHalf_usedReg_dataReg[5:3] == 3'd0)) ||
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201 |
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res_inSndHalf_finishInit))) &&
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202 |
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(((! ((res_nextTokW.whas
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203 |
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? res_nextTokW.wget[2:0]
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204 |
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: _) ==
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205 |
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3'd0)) &&
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206 |
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(((res_scheduler_last[3]
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207 |
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? res_scheduler_last[2:0]
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208 |
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: _) ==
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209 |
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3'd0)
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210 |
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? (! res_scheduler_last[3]) &&
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211 |
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(((res_scheduler_last[3]
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212 |
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? res_scheduler_last[2:0]
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213 |
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: _) ==
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214 |
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3'd0)
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215 |
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? ! (res_inFstHalf_usedReg_dataReg[2:0] == 3'd0)
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216 |
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: (((res_scheduler_last[3]
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217 |
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? res_scheduler_last[2:0]
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218 |
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: _) ==
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219 |
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3'd1)
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220 |
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? ! (res_inFstHalf_usedReg_dataReg[5:3] == 3'd0)
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221 |
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: (((res_scheduler_last[3]
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222 |
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? res_scheduler_last[2:0]
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223 |
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: _) ==
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224 |
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3'd2)
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225 |
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? ! (res_inFstHalf_usedReg_dataReg[8:6] == 3'd0)
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226 |
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: (((res_scheduler_last[3]
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227 |
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? res_scheduler_last[2:0]
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228 |
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: _) ==
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229 |
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3'd3)
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230 |
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? ! (res_inFstHalf_usedReg_dataReg[11:9] == 3'd0)
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231 |
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: (((res_scheduler_last[3]
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232 |
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? res_scheduler_last[2:0]
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233 |
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: _) ==
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234 |
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3'd4)
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235 |
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? ! (res_inFstHalf_usedReg_dataReg[14:12] ==
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236 |
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3'd0)
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237 |
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: (((res_scheduler_last[3]
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238 |
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? res_scheduler_last[2:0]
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239 |
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: _) ==
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240 |
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3'd5)
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241 |
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? ! (res_inFstHalf_usedReg_dataReg[17:15] ==
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242 |
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3'd0)
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243 |
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: (((res_scheduler_last___d1083(...)[3]
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244 |
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? res_scheduler_last___d1083(...)[2:0]
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245 |
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: _) ==
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246 |
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3'd6)
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247 |
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? ! (res_inFstHalf_usedReg_dataReg__h11884(...)[20:18] ==
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248 |
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3'd0)
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249 |
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: (((res_scheduler_last_36_BIT_3___d1029(...)
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250 |
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? res_scheduler_last_36_BITS_2_TO_0___d1209(...)
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251 |
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: _) ==
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252 |
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3'd7)
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253 |
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? ! (n__h36594(...) == 3'd0)
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254 |
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: _))))))))
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255 |
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: (! (res_inFstHalf_usedReg_dataReg[2:0] == 3'd0))) &&
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256 |
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(! (res_inSndHalf_usedReg_dataReg[2:0] == 3'd0))) ||
|
257 |
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((! ((res_nextTokW.whas
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258 |
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? res_nextTokW.wget[5:3]
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259 |
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: _) ==
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260 |
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3'd0)) &&
|
261 |
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(((res_scheduler_last[3]
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262 |
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? res_scheduler_last[2:0]
|
263 |
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: _) ==
|
264 |
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3'd1)
|
265 |
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? (! res_scheduler_last[3]) &&
|
266 |
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(((res_scheduler_last[3]
|
267 |
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? res_scheduler_last[2:0]
|
268 |
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: _) ==
|
269 |
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3'd0)
|
270 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[2:0] == 3'd0)
|
271 |
|
|
: (((res_scheduler_last[3]
|
272 |
|
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? res_scheduler_last[2:0]
|
273 |
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: _) ==
|
274 |
|
|
3'd1)
|
275 |
|
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? ! (res_inFstHalf_usedReg_dataReg[5:3] == 3'd0)
|
276 |
|
|
: (((res_scheduler_last[3]
|
277 |
|
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? res_scheduler_last[2:0]
|
278 |
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: _) ==
|
279 |
|
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3'd2)
|
280 |
|
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? ! (res_inFstHalf_usedReg_dataReg[8:6] == 3'd0)
|
281 |
|
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: (((res_scheduler_last[3]
|
282 |
|
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? res_scheduler_last[2:0]
|
283 |
|
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: _) ==
|
284 |
|
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3'd3)
|
285 |
|
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? ! (res_inFstHalf_usedReg_dataReg[11:9] == 3'd0)
|
286 |
|
|
: (((res_scheduler_last[3]
|
287 |
|
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? res_scheduler_last[2:0]
|
288 |
|
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: _) ==
|
289 |
|
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3'd4)
|
290 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[14:12] ==
|
291 |
|
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3'd0)
|
292 |
|
|
: (((res_scheduler_last[3]
|
293 |
|
|
? res_scheduler_last[2:0]
|
294 |
|
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: _) ==
|
295 |
|
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3'd5)
|
296 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[17:15] ==
|
297 |
|
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3'd0)
|
298 |
|
|
: (((res_scheduler_last___d1083(...)[3]
|
299 |
|
|
? res_scheduler_last___d1083(...)[2:0]
|
300 |
|
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: _) ==
|
301 |
|
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3'd6)
|
302 |
|
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? ! (res_inFstHalf_usedReg_dataReg__h11884(...)[20:18] ==
|
303 |
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3'd0)
|
304 |
|
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: (((res_scheduler_last_36_BIT_3___d1029(...)
|
305 |
|
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? res_scheduler_last_36_BITS_2_TO_0___d1209(...)
|
306 |
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: _) ==
|
307 |
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3'd7)
|
308 |
|
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? ! (n__h36594(...) == 3'd0)
|
309 |
|
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: _))))))))
|
310 |
|
|
: (! (res_inFstHalf_usedReg_dataReg[5:3] == 3'd0))) &&
|
311 |
|
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(! (res_inSndHalf_usedReg_dataReg[5:3] == 3'd0))) ||
|
312 |
|
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((((res_nextTokW.whas
|
313 |
|
|
? res_nextTokW.wget[8:6]
|
314 |
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: _) ==
|
315 |
|
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3'd0) ||
|
316 |
|
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res_inFstHalf_finishInit) &&
|
317 |
|
|
(((res_nextTokW.whas
|
318 |
|
|
? res_nextTokW.wget[8:6]
|
319 |
|
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: _) ==
|
320 |
|
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3'd0) ||
|
321 |
|
|
(((res_scheduler_last[3]
|
322 |
|
|
? res_scheduler_last[2:0]
|
323 |
|
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: _) ==
|
324 |
|
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3'd2)
|
325 |
|
|
? res_scheduler_last[3] ||
|
326 |
|
|
(res_inFstHalf_usedReg_dataReg[8:6] == 3'd0)
|
327 |
|
|
: (res_inFstHalf_usedReg_dataReg[8:6] == 3'd0)) ||
|
328 |
|
|
res_inSndHalf_finishInit) &&
|
329 |
|
|
(((! ((res_nextTokW.whas
|
330 |
|
|
? res_nextTokW.wget[8:6]
|
331 |
|
|
: _) ==
|
332 |
|
|
3'd0)) &&
|
333 |
|
|
(((res_scheduler_last[3]
|
334 |
|
|
? res_scheduler_last[2:0]
|
335 |
|
|
: _) ==
|
336 |
|
|
3'd2)
|
337 |
|
|
? (! res_scheduler_last[3]) &&
|
338 |
|
|
(((res_scheduler_last[3]
|
339 |
|
|
? res_scheduler_last[2:0]
|
340 |
|
|
: _) ==
|
341 |
|
|
3'd0)
|
342 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[2:0] == 3'd0)
|
343 |
|
|
: (((res_scheduler_last[3]
|
344 |
|
|
? res_scheduler_last[2:0]
|
345 |
|
|
: _) ==
|
346 |
|
|
3'd1)
|
347 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[5:3] == 3'd0)
|
348 |
|
|
: (((res_scheduler_last[3]
|
349 |
|
|
? res_scheduler_last[2:0]
|
350 |
|
|
: _) ==
|
351 |
|
|
3'd2)
|
352 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[8:6] == 3'd0)
|
353 |
|
|
: (((res_scheduler_last[3]
|
354 |
|
|
? res_scheduler_last[2:0]
|
355 |
|
|
: _) ==
|
356 |
|
|
3'd3)
|
357 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[11:9] == 3'd0)
|
358 |
|
|
: (((res_scheduler_last___d1083(...)[3]
|
359 |
|
|
? res_scheduler_last___d1083(...)[2:0]
|
360 |
|
|
: _) ==
|
361 |
|
|
3'd4)
|
362 |
|
|
? ! (res_inFstHalf_usedReg_dataReg__h11884(...)[14:12] ==
|
363 |
|
|
3'd0)
|
364 |
|
|
: (((res_scheduler_last_36_BIT_3___d1029(...)
|
365 |
|
|
? res_scheduler_last_36_BITS_2_TO_0___d1209(...)
|
366 |
|
|
: _) ==
|
367 |
|
|
3'd5)
|
368 |
|
|
? ! (n__h36618(...) == 3'd0)
|
369 |
|
|
: ((idx__h92163(...) == 3'd6)
|
370 |
|
|
? ! res_inFstHalf_usedReg_dataReg_41_BITS_20_TO_18_ETC___d972(...)
|
371 |
|
|
: (IF_res_scheduler_last_36_BIT_3_37_THEN_res_sch_ETC___d1216(...)
|
372 |
|
|
? NOT_res_inFstHalf_usedReg_dataReg_41_BITS_23_T_ETC___d1174(...)
|
373 |
|
|
: _))))))))
|
374 |
|
|
: (! (res_inFstHalf_usedReg_dataReg[8:6] == 3'd0))) &&
|
375 |
|
|
(! (res_inSndHalf_usedReg_dataReg[8:6] == 3'd0)))
|
376 |
|
|
? res_inFstHalf_finishInit && res_inSndHalf_finishInit
|
377 |
|
|
: ((((res_nextTokW.whas
|
378 |
|
|
? res_nextTokW.wget[11:9]
|
379 |
|
|
: _) ==
|
380 |
|
|
3'd0) ||
|
381 |
|
|
res_inFstHalf_finishInit) &&
|
382 |
|
|
(((res_nextTokW.whas
|
383 |
|
|
? res_nextTokW.wget[11:9]
|
384 |
|
|
: _) ==
|
385 |
|
|
3'd0) ||
|
386 |
|
|
(((res_scheduler_last[3]
|
387 |
|
|
? res_scheduler_last[2:0]
|
388 |
|
|
: _) ==
|
389 |
|
|
3'd3)
|
390 |
|
|
? res_scheduler_last[3] ||
|
391 |
|
|
(res_inFstHalf_usedReg_dataReg[11:9] == 3'd0)
|
392 |
|
|
: (res_inFstHalf_usedReg_dataReg[11:9] == 3'd0)) ||
|
393 |
|
|
res_inSndHalf_finishInit))))) &&
|
394 |
|
|
(((! ((res_nextTokW.whas
|
395 |
|
|
? res_nextTokW.wget[2:0]
|
396 |
|
|
: _) ==
|
397 |
|
|
3'd0)) &&
|
398 |
|
|
(((res_scheduler_last[3]
|
399 |
|
|
? res_scheduler_last[2:0]
|
400 |
|
|
: _) ==
|
401 |
|
|
3'd0)
|
402 |
|
|
? (! res_scheduler_last[3]) &&
|
403 |
|
|
(((res_scheduler_last[3]
|
404 |
|
|
? res_scheduler_last[2:0]
|
405 |
|
|
: _) ==
|
406 |
|
|
3'd0)
|
407 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[2:0] == 3'd0)
|
408 |
|
|
: (((res_scheduler_last[3]
|
409 |
|
|
? res_scheduler_last[2:0]
|
410 |
|
|
: _) ==
|
411 |
|
|
3'd1)
|
412 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[5:3] == 3'd0)
|
413 |
|
|
: (((res_scheduler_last[3]
|
414 |
|
|
? res_scheduler_last[2:0]
|
415 |
|
|
: _) ==
|
416 |
|
|
3'd2)
|
417 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[8:6] == 3'd0)
|
418 |
|
|
: (((res_scheduler_last[3]
|
419 |
|
|
? res_scheduler_last[2:0]
|
420 |
|
|
: _) ==
|
421 |
|
|
3'd3)
|
422 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[11:9] == 3'd0)
|
423 |
|
|
: (((res_scheduler_last___d1083(...)[3]
|
424 |
|
|
? res_scheduler_last___d1083(...)[2:0]
|
425 |
|
|
: _) ==
|
426 |
|
|
3'd4)
|
427 |
|
|
? ! (res_inFstHalf_usedReg_dataReg__h11884(...)[14:12] ==
|
428 |
|
|
3'd0)
|
429 |
|
|
: (((res_scheduler_last_36_BIT_3___d1029(...)
|
430 |
|
|
? res_scheduler_last_36_BITS_2_TO_0___d1209(...)
|
431 |
|
|
: _) ==
|
432 |
|
|
3'd5)
|
433 |
|
|
? ! (n__h36618(...) == 3'd0)
|
434 |
|
|
: ((idx__h92163(...) == 3'd6)
|
435 |
|
|
? ! res_inFstHalf_usedReg_dataReg_41_BITS_20_TO_18_ETC___d972(...)
|
436 |
|
|
: (IF_res_scheduler_last_36_BIT_3_37_THEN_res_sch_ETC___d1216(...)
|
437 |
|
|
? NOT_res_inFstHalf_usedReg_dataReg_41_BITS_23_T_ETC___d1174(...)
|
438 |
|
|
: _))))))))
|
439 |
|
|
: (! (res_inFstHalf_usedReg_dataReg[2:0] == 3'd0))) &&
|
440 |
|
|
(! (res_inSndHalf_usedReg_dataReg[2:0] == 3'd0))) ||
|
441 |
|
|
((! ((res_nextTokW.whas
|
442 |
|
|
? res_nextTokW.wget[5:3]
|
443 |
|
|
: _) ==
|
444 |
|
|
3'd0)) &&
|
445 |
|
|
(((res_scheduler_last[3]
|
446 |
|
|
? res_scheduler_last[2:0]
|
447 |
|
|
: _) ==
|
448 |
|
|
3'd1)
|
449 |
|
|
? (! res_scheduler_last[3]) &&
|
450 |
|
|
(((res_scheduler_last[3]
|
451 |
|
|
? res_scheduler_last[2:0]
|
452 |
|
|
: _) ==
|
453 |
|
|
3'd0)
|
454 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[2:0] == 3'd0)
|
455 |
|
|
: (((res_scheduler_last[3]
|
456 |
|
|
? res_scheduler_last[2:0]
|
457 |
|
|
: _) ==
|
458 |
|
|
3'd1)
|
459 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[5:3] == 3'd0)
|
460 |
|
|
: (((res_scheduler_last[3]
|
461 |
|
|
? res_scheduler_last[2:0]
|
462 |
|
|
: _) ==
|
463 |
|
|
3'd2)
|
464 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[8:6] == 3'd0)
|
465 |
|
|
: (((res_scheduler_last[3]
|
466 |
|
|
? res_scheduler_last[2:0]
|
467 |
|
|
: _) ==
|
468 |
|
|
3'd3)
|
469 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[11:9] == 3'd0)
|
470 |
|
|
: (((res_scheduler_last___d1083(...)[3]
|
471 |
|
|
? res_scheduler_last___d1083(...)[2:0]
|
472 |
|
|
: _) ==
|
473 |
|
|
3'd4)
|
474 |
|
|
? ! (res_inFstHalf_usedReg_dataReg__h11884(...)[14:12] ==
|
475 |
|
|
3'd0)
|
476 |
|
|
: (((res_scheduler_last_36_BIT_3___d1029(...)
|
477 |
|
|
? res_scheduler_last_36_BITS_2_TO_0___d1209(...)
|
478 |
|
|
: _) ==
|
479 |
|
|
3'd5)
|
480 |
|
|
? ! (n__h36618(...) == 3'd0)
|
481 |
|
|
: ((idx__h92163(...) == 3'd6)
|
482 |
|
|
? ! res_inFstHalf_usedReg_dataReg_41_BITS_20_TO_18_ETC___d972(...)
|
483 |
|
|
: (IF_res_scheduler_last_36_BIT_3_37_THEN_res_sch_ETC___d1216(...)
|
484 |
|
|
? NOT_res_inFstHalf_usedReg_dataReg_41_BITS_23_T_ETC___d1174(...)
|
485 |
|
|
: _))))))))
|
486 |
|
|
: (! (res_inFstHalf_usedReg_dataReg[5:3] == 3'd0))) &&
|
487 |
|
|
(! (res_inSndHalf_usedReg_dataReg[5:3] == 3'd0))) ||
|
488 |
|
|
((! ((res_nextTokW.whas
|
489 |
|
|
? res_nextTokW.wget[8:6]
|
490 |
|
|
: _) ==
|
491 |
|
|
3'd0)) &&
|
492 |
|
|
(((res_scheduler_last[3]
|
493 |
|
|
? res_scheduler_last[2:0]
|
494 |
|
|
: _) ==
|
495 |
|
|
3'd2)
|
496 |
|
|
? (! res_scheduler_last[3]) &&
|
497 |
|
|
(((res_scheduler_last[3]
|
498 |
|
|
? res_scheduler_last[2:0]
|
499 |
|
|
: _) ==
|
500 |
|
|
3'd0)
|
501 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[2:0] == 3'd0)
|
502 |
|
|
: (((res_scheduler_last[3]
|
503 |
|
|
? res_scheduler_last[2:0]
|
504 |
|
|
: _) ==
|
505 |
|
|
3'd1)
|
506 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[5:3] == 3'd0)
|
507 |
|
|
: (((res_scheduler_last[3]
|
508 |
|
|
? res_scheduler_last[2:0]
|
509 |
|
|
: _) ==
|
510 |
|
|
3'd2)
|
511 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[8:6] == 3'd0)
|
512 |
|
|
: (((res_scheduler_last[3]
|
513 |
|
|
? res_scheduler_last[2:0]
|
514 |
|
|
: _) ==
|
515 |
|
|
3'd3)
|
516 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[11:9] == 3'd0)
|
517 |
|
|
: (((res_scheduler_last___d1083(...)[3]
|
518 |
|
|
? res_scheduler_last___d1083(...)[2:0]
|
519 |
|
|
: _) ==
|
520 |
|
|
3'd4)
|
521 |
|
|
? ! (res_inFstHalf_usedReg_dataReg__h11884(...)[14:12] ==
|
522 |
|
|
3'd0)
|
523 |
|
|
: (((res_scheduler_last_36_BIT_3___d1029(...)
|
524 |
|
|
? res_scheduler_last_36_BITS_2_TO_0___d1209(...)
|
525 |
|
|
: _) ==
|
526 |
|
|
3'd5)
|
527 |
|
|
? ! (n__h36618(...) == 3'd0)
|
528 |
|
|
: ((idx__h92163(...) == 3'd6)
|
529 |
|
|
? ! res_inFstHalf_usedReg_dataReg_41_BITS_20_TO_18_ETC___d972(...)
|
530 |
|
|
: (IF_res_scheduler_last_36_BIT_3_37_THEN_res_sch_ETC___d1216(...)
|
531 |
|
|
? NOT_res_inFstHalf_usedReg_dataReg_41_BITS_23_T_ETC___d1174(...)
|
532 |
|
|
: _))))))))
|
533 |
|
|
: (! (res_inFstHalf_usedReg_dataReg[8:6] == 3'd0))) &&
|
534 |
|
|
(! (res_inSndHalf_usedReg_dataReg[8:6] == 3'd0))) ||
|
535 |
|
|
((! ((res_nextTokW.whas
|
536 |
|
|
? res_nextTokW.wget[11:9]
|
537 |
|
|
: _) ==
|
538 |
|
|
3'd0)) &&
|
539 |
|
|
(((res_scheduler_last[3]
|
540 |
|
|
? res_scheduler_last[2:0]
|
541 |
|
|
: _) ==
|
542 |
|
|
3'd3)
|
543 |
|
|
? (! res_scheduler_last[3]) &&
|
544 |
|
|
(((res_scheduler_last[3]
|
545 |
|
|
? res_scheduler_last[2:0]
|
546 |
|
|
: _) ==
|
547 |
|
|
3'd0)
|
548 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[2:0] == 3'd0)
|
549 |
|
|
: (((res_scheduler_last[3]
|
550 |
|
|
? res_scheduler_last[2:0]
|
551 |
|
|
: _) ==
|
552 |
|
|
3'd1)
|
553 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[5:3] == 3'd0)
|
554 |
|
|
: (((res_scheduler_last[3]
|
555 |
|
|
? res_scheduler_last[2:0]
|
556 |
|
|
: _) ==
|
557 |
|
|
3'd2)
|
558 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[8:6] == 3'd0)
|
559 |
|
|
: (((res_scheduler_last[3]
|
560 |
|
|
? res_scheduler_last[2:0]
|
561 |
|
|
: _) ==
|
562 |
|
|
3'd3)
|
563 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[11:9] == 3'd0)
|
564 |
|
|
: (((res_scheduler_last___d1083(...)[3]
|
565 |
|
|
? res_scheduler_last___d1083(...)[2:0]
|
566 |
|
|
: _) ==
|
567 |
|
|
3'd4)
|
568 |
|
|
? ! (res_inFstHalf_usedReg_dataReg__h11884(...)[14:12] ==
|
569 |
|
|
3'd0)
|
570 |
|
|
: (((res_scheduler_last_36_BIT_3___d1029(...)
|
571 |
|
|
? res_scheduler_last_36_BITS_2_TO_0___d1209(...)
|
572 |
|
|
: _) ==
|
573 |
|
|
3'd5)
|
574 |
|
|
? ! (n__h36618(...) == 3'd0)
|
575 |
|
|
: ((idx__h92163(...) == 3'd6)
|
576 |
|
|
? ! res_inFstHalf_usedReg_dataReg_41_BITS_20_TO_18_ETC___d972(...)
|
577 |
|
|
: (IF_res_scheduler_last_36_BIT_3_37_THEN_res_sch_ETC___d1216(...)
|
578 |
|
|
? NOT_res_inFstHalf_usedReg_dataReg_41_BITS_23_T_ETC___d1174(...)
|
579 |
|
|
: _))))))))
|
580 |
|
|
: (! (res_inFstHalf_usedReg_dataReg[11:9] == 3'd0))) &&
|
581 |
|
|
(! (res_inSndHalf_usedReg_dataReg[11:9] == 3'd0))) ||
|
582 |
|
|
((((res_nextTokW.whas
|
583 |
|
|
? res_nextTokW.wget[14:12]
|
584 |
|
|
: _) ==
|
585 |
|
|
3'd0) ||
|
586 |
|
|
res_inFstHalf_finishInit) &&
|
587 |
|
|
(((res_nextTokW.whas
|
588 |
|
|
? res_nextTokW.wget[14:12]
|
589 |
|
|
: _) ==
|
590 |
|
|
3'd0) ||
|
591 |
|
|
(((res_scheduler_last[3]
|
592 |
|
|
? res_scheduler_last[2:0]
|
593 |
|
|
: _) ==
|
594 |
|
|
3'd4)
|
595 |
|
|
? res_scheduler_last[3] ||
|
596 |
|
|
(res_inFstHalf_usedReg_dataReg[14:12] == 3'd0)
|
597 |
|
|
: (res_inFstHalf_usedReg_dataReg[14:12] == 3'd0)) ||
|
598 |
|
|
res_inSndHalf_finishInit) &&
|
599 |
|
|
(((! ((res_nextTokW.whas
|
600 |
|
|
? res_nextTokW.wget[14:12]
|
601 |
|
|
: _) ==
|
602 |
|
|
3'd0)) &&
|
603 |
|
|
(((res_scheduler_last[3]
|
604 |
|
|
? res_scheduler_last[2:0]
|
605 |
|
|
: _) ==
|
606 |
|
|
3'd4)
|
607 |
|
|
? (! res_scheduler_last[3]) &&
|
608 |
|
|
(((res_scheduler_last[3]
|
609 |
|
|
? res_scheduler_last[2:0]
|
610 |
|
|
: _) ==
|
611 |
|
|
3'd0)
|
612 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[2:0] == 3'd0)
|
613 |
|
|
: (((res_scheduler_last[3]
|
614 |
|
|
? res_scheduler_last[2:0]
|
615 |
|
|
: _) ==
|
616 |
|
|
3'd1)
|
617 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[5:3] == 3'd0)
|
618 |
|
|
: (((res_scheduler_last___d1083(...)[3]
|
619 |
|
|
? res_scheduler_last___d1083(...)[2:0]
|
620 |
|
|
: _) ==
|
621 |
|
|
3'd2)
|
622 |
|
|
? ! (res_inFstHalf_usedReg_dataReg__h11884(...)[8:6] ==
|
623 |
|
|
3'd0)
|
624 |
|
|
: (((res_scheduler_last_36_BIT_3___d1029(...)
|
625 |
|
|
? res_scheduler_last_36_BITS_2_TO_0___d1209(...)
|
626 |
|
|
: _) ==
|
627 |
|
|
3'd3)
|
628 |
|
|
? ! (n__h36642(...) == 3'd0)
|
629 |
|
|
: ((idx__h92163(...) == 3'd4)
|
630 |
|
|
? ! res_inFstHalf_usedReg_dataReg_41_BITS_14_TO_12_ETC___d971(...)
|
631 |
|
|
: (IF_res_scheduler_last_36_BIT_3_37_THEN_res_sch_ETC___d1214(...)
|
632 |
|
|
? NOT_res_inFstHalf_usedReg_dataReg_41_BITS_17_T_ETC___d1172(...)
|
633 |
|
|
: IF_IF_res_scheduler_last_36_BIT_3_37_THEN_res__ETC___d180(...)))))))
|
634 |
|
|
: (! (res_inFstHalf_usedReg_dataReg[14:12] == 3'd0))) &&
|
635 |
|
|
(! (res_inSndHalf_usedReg_dataReg[14:12] == 3'd0)))
|
636 |
|
|
? res_inFstHalf_finishInit && res_inSndHalf_finishInit
|
637 |
|
|
: ((((res_nextTokW.whas
|
638 |
|
|
? res_nextTokW.wget[17:15]
|
639 |
|
|
: _) ==
|
640 |
|
|
3'd0) ||
|
641 |
|
|
res_inFstHalf_finishInit) &&
|
642 |
|
|
(((res_nextTokW.whas
|
643 |
|
|
? res_nextTokW.wget[17:15]
|
644 |
|
|
: _) ==
|
645 |
|
|
3'd0) ||
|
646 |
|
|
(((res_scheduler_last[3]
|
647 |
|
|
? res_scheduler_last[2:0]
|
648 |
|
|
: _) ==
|
649 |
|
|
3'd5)
|
650 |
|
|
? res_scheduler_last[3] ||
|
651 |
|
|
(res_inFstHalf_usedReg_dataReg[17:15] == 3'd0)
|
652 |
|
|
: (res_inFstHalf_usedReg_dataReg[17:15] == 3'd0)) ||
|
653 |
|
|
res_inSndHalf_finishInit))) &&
|
654 |
|
|
(((! ((res_nextTokW.whas
|
655 |
|
|
? res_nextTokW.wget[14:12]
|
656 |
|
|
: _) ==
|
657 |
|
|
3'd0)) &&
|
658 |
|
|
(((res_scheduler_last[3]
|
659 |
|
|
? res_scheduler_last[2:0]
|
660 |
|
|
: _) ==
|
661 |
|
|
3'd4)
|
662 |
|
|
? (! res_scheduler_last[3]) &&
|
663 |
|
|
(((res_scheduler_last[3]
|
664 |
|
|
? res_scheduler_last[2:0]
|
665 |
|
|
: _) ==
|
666 |
|
|
3'd0)
|
667 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[2:0] == 3'd0)
|
668 |
|
|
: (((res_scheduler_last___d1083(...)[3]
|
669 |
|
|
? res_scheduler_last___d1083(...)[2:0]
|
670 |
|
|
: _) ==
|
671 |
|
|
3'd1)
|
672 |
|
|
? ! (res_inFstHalf_usedReg_dataReg__h11884(...)[5:3] ==
|
673 |
|
|
3'd0)
|
674 |
|
|
: (((res_scheduler_last_36_BIT_3___d1029(...)
|
675 |
|
|
? res_scheduler_last_36_BITS_2_TO_0___d1209(...)
|
676 |
|
|
: _) ==
|
677 |
|
|
3'd2)
|
678 |
|
|
? ! (n__h36654(...) == 3'd0)
|
679 |
|
|
: ((idx__h92163(...) == 3'd3)
|
680 |
|
|
? ! res_inFstHalf_usedReg_dataReg_41_BITS_11_TO_9__ETC___d1018(...)
|
681 |
|
|
: (IF_res_scheduler_last_36_BIT_3_37_THEN_res_sch_ETC___d1213(...)
|
682 |
|
|
? NOT_res_inFstHalf_usedReg_dataReg_41_BITS_14_T_ETC___d1171(...)
|
683 |
|
|
: IF_IF_res_scheduler_last_36_BIT_3_37_THEN_res__ETC___d181(...))))))
|
684 |
|
|
: (! (res_inFstHalf_usedReg_dataReg[14:12] == 3'd0))) &&
|
685 |
|
|
(! (res_inSndHalf_usedReg_dataReg[14:12] == 3'd0))) ||
|
686 |
|
|
((! ((res_nextTokW.whas
|
687 |
|
|
? res_nextTokW.wget[17:15]
|
688 |
|
|
: _) ==
|
689 |
|
|
3'd0)) &&
|
690 |
|
|
(((res_scheduler_last[3]
|
691 |
|
|
? res_scheduler_last[2:0]
|
692 |
|
|
: _) ==
|
693 |
|
|
3'd5)
|
694 |
|
|
? (! res_scheduler_last[3]) &&
|
695 |
|
|
(((res_scheduler_last[3]
|
696 |
|
|
? res_scheduler_last[2:0]
|
697 |
|
|
: _) ==
|
698 |
|
|
3'd0)
|
699 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[2:0] == 3'd0)
|
700 |
|
|
: (((res_scheduler_last___d1083(...)[3]
|
701 |
|
|
? res_scheduler_last___d1083(...)[2:0]
|
702 |
|
|
: _) ==
|
703 |
|
|
3'd1)
|
704 |
|
|
? ! (res_inFstHalf_usedReg_dataReg__h11884(...)[5:3] ==
|
705 |
|
|
3'd0)
|
706 |
|
|
: (((res_scheduler_last_36_BIT_3___d1029(...)
|
707 |
|
|
? res_scheduler_last_36_BITS_2_TO_0___d1209(...)
|
708 |
|
|
: _) ==
|
709 |
|
|
3'd2)
|
710 |
|
|
? ! (n__h36654(...) == 3'd0)
|
711 |
|
|
: ((idx__h92163(...) == 3'd3)
|
712 |
|
|
? ! res_inFstHalf_usedReg_dataReg_41_BITS_11_TO_9__ETC___d1018(...)
|
713 |
|
|
: (IF_res_scheduler_last_36_BIT_3_37_THEN_res_sch_ETC___d1213(...)
|
714 |
|
|
? NOT_res_inFstHalf_usedReg_dataReg_41_BITS_14_T_ETC___d1171(...)
|
715 |
|
|
: IF_IF_res_scheduler_last_36_BIT_3_37_THEN_res__ETC___d181(...))))))
|
716 |
|
|
: (! (res_inFstHalf_usedReg_dataReg[17:15] == 3'd0))) &&
|
717 |
|
|
(! (res_inSndHalf_usedReg_dataReg[17:15] == 3'd0))) ||
|
718 |
|
|
((((res_nextTokW.whas
|
719 |
|
|
? res_nextTokW.wget[20:18]
|
720 |
|
|
: _) ==
|
721 |
|
|
3'd0) ||
|
722 |
|
|
res_inFstHalf_finishInit) &&
|
723 |
|
|
(((res_nextTokW.whas
|
724 |
|
|
? res_nextTokW.wget[20:18]
|
725 |
|
|
: _) ==
|
726 |
|
|
3'd0) ||
|
727 |
|
|
(((res_scheduler_last[3]
|
728 |
|
|
? res_scheduler_last[2:0]
|
729 |
|
|
: _) ==
|
730 |
|
|
3'd6)
|
731 |
|
|
? res_scheduler_last[3] ||
|
732 |
|
|
(res_inFstHalf_usedReg_dataReg[20:18] == 3'd0)
|
733 |
|
|
: (res_inFstHalf_usedReg_dataReg[20:18] == 3'd0)) ||
|
734 |
|
|
res_inSndHalf_finishInit) &&
|
735 |
|
|
(((! ((res_nextTokW.whas
|
736 |
|
|
? res_nextTokW.wget[20:18]
|
737 |
|
|
: _) ==
|
738 |
|
|
3'd0)) &&
|
739 |
|
|
(((res_scheduler_last[3]
|
740 |
|
|
? res_scheduler_last[2:0]
|
741 |
|
|
: _) ==
|
742 |
|
|
3'd6)
|
743 |
|
|
? (! res_scheduler_last[3]) &&
|
744 |
|
|
(((res_scheduler_last_36_BIT_3___d1029(...)
|
745 |
|
|
? res_scheduler_last_36_BITS_2_TO_0___d1209(...)
|
746 |
|
|
: _) ==
|
747 |
|
|
3'd0)
|
748 |
|
|
? ! (n__h36678(...) == 3'd0)
|
749 |
|
|
: ((idx__h92163(...) == 3'd1)
|
750 |
|
|
? ! res_inFstHalf_usedReg_dataReg_41_BITS_5_TO_3_5_ETC___d1017(...)
|
751 |
|
|
: (IF_res_scheduler_last_36_BIT_3_37_THEN_res_sch_ETC___d1211(...)
|
752 |
|
|
? NOT_res_inFstHalf_usedReg_dataReg_41_BITS_8_TO_ETC___d1169(...)
|
753 |
|
|
: IF_IF_res_scheduler_last_36_BIT_3_37_THEN_res__ETC___d183(...))))
|
754 |
|
|
: (! (res_inFstHalf_usedReg_dataReg[20:18] == 3'd0))) &&
|
755 |
|
|
(! (res_inSndHalf_usedReg_dataReg[20:18] == 3'd0)))
|
756 |
|
|
? res_inFstHalf_finishInit && res_inSndHalf_finishInit
|
757 |
|
|
: ((((res_nextTokW.whas
|
758 |
|
|
? res_nextTokW.wget[23:21]
|
759 |
|
|
: _) ==
|
760 |
|
|
3'd0) ||
|
761 |
|
|
res_inFstHalf_finishInit) &&
|
762 |
|
|
(((res_nextTokW.whas
|
763 |
|
|
? res_nextTokW.wget[23:21]
|
764 |
|
|
: _) ==
|
765 |
|
|
3'd0) ||
|
766 |
|
|
(((res_scheduler_last___d1083(...)[3]
|
767 |
|
|
? res_scheduler_last___d1083(...)[2:0]
|
768 |
|
|
: _) ==
|
769 |
|
|
3'd7)
|
770 |
|
|
? res_scheduler_last[3] ||
|
771 |
|
|
(res_inFstHalf_usedReg_dataReg__h11884(...)[23:21] ==
|
772 |
|
|
3'd0)
|
773 |
|
|
: (res_inFstHalf_usedReg_dataReg[23:21] == 3'd0)) ||
|
774 |
|
|
res_inSndHalf_finishInit))))))) &&
|
775 |
|
|
(((((res_nextTokW.whas
|
776 |
|
|
? res_nextTokW.wget[2:0]
|
777 |
|
|
: _) ==
|
778 |
|
|
3'd0) ||
|
779 |
|
|
(((res_scheduler_last[3]
|
780 |
|
|
? res_scheduler_last[2:0]
|
781 |
|
|
: _) ==
|
782 |
|
|
3'd0)
|
783 |
|
|
? res_scheduler_last[3] ||
|
784 |
|
|
(res_inFstHalf_usedReg_dataReg[2:0] == 3'd0)
|
785 |
|
|
: (res_inFstHalf_usedReg_dataReg[2:0] == 3'd0)) ||
|
786 |
|
|
(res_inSndHalf_usedReg_dataReg[2:0] == 3'd0)) &&
|
787 |
|
|
(((res_nextTokW.whas
|
788 |
|
|
? res_nextTokW.wget[5:3]
|
789 |
|
|
: _) ==
|
790 |
|
|
3'd0) ||
|
791 |
|
|
(((res_scheduler_last[3]
|
792 |
|
|
? res_scheduler_last[2:0]
|
793 |
|
|
: _) ==
|
794 |
|
|
3'd1)
|
795 |
|
|
? res_scheduler_last[3] ||
|
796 |
|
|
(res_inFstHalf_usedReg_dataReg[5:3] == 3'd0)
|
797 |
|
|
: (res_inFstHalf_usedReg_dataReg[5:3] == 3'd0)) ||
|
798 |
|
|
(res_inSndHalf_usedReg_dataReg[5:3] == 3'd0)) &&
|
799 |
|
|
(((res_nextTokW.whas
|
800 |
|
|
? res_nextTokW.wget[8:6]
|
801 |
|
|
: _) ==
|
802 |
|
|
3'd0) ||
|
803 |
|
|
(((res_scheduler_last[3]
|
804 |
|
|
? res_scheduler_last[2:0]
|
805 |
|
|
: _) ==
|
806 |
|
|
3'd2)
|
807 |
|
|
? res_scheduler_last[3] ||
|
808 |
|
|
(res_inFstHalf_usedReg_dataReg[8:6] == 3'd0)
|
809 |
|
|
: (res_inFstHalf_usedReg_dataReg[8:6] == 3'd0)) ||
|
810 |
|
|
(res_inSndHalf_usedReg_dataReg[8:6] == 3'd0)) &&
|
811 |
|
|
(((res_nextTokW.whas
|
812 |
|
|
? res_nextTokW.wget[11:9]
|
813 |
|
|
: _) ==
|
814 |
|
|
3'd0) ||
|
815 |
|
|
(((res_scheduler_last[3]
|
816 |
|
|
? res_scheduler_last[2:0]
|
817 |
|
|
: _) ==
|
818 |
|
|
3'd3)
|
819 |
|
|
? res_scheduler_last[3] ||
|
820 |
|
|
(res_inFstHalf_usedReg_dataReg[11:9] == 3'd0)
|
821 |
|
|
: (res_inFstHalf_usedReg_dataReg[11:9] == 3'd0)) ||
|
822 |
|
|
(res_inSndHalf_usedReg_dataReg[11:9] == 3'd0)) &&
|
823 |
|
|
(((res_nextTokW.whas
|
824 |
|
|
? res_nextTokW.wget[14:12]
|
825 |
|
|
: _) ==
|
826 |
|
|
3'd0) ||
|
827 |
|
|
(((res_scheduler_last[3]
|
828 |
|
|
? res_scheduler_last[2:0]
|
829 |
|
|
: _) ==
|
830 |
|
|
3'd4)
|
831 |
|
|
? res_scheduler_last[3] ||
|
832 |
|
|
(res_inFstHalf_usedReg_dataReg[14:12] == 3'd0)
|
833 |
|
|
: (res_inFstHalf_usedReg_dataReg[14:12] == 3'd0)) ||
|
834 |
|
|
(res_inSndHalf_usedReg_dataReg[14:12] == 3'd0)) &&
|
835 |
|
|
(((res_nextTokW.whas
|
836 |
|
|
? res_nextTokW.wget[17:15]
|
837 |
|
|
: _) ==
|
838 |
|
|
3'd0) ||
|
839 |
|
|
(((res_scheduler_last[3]
|
840 |
|
|
? res_scheduler_last[2:0]
|
841 |
|
|
: _) ==
|
842 |
|
|
3'd5)
|
843 |
|
|
? res_scheduler_last[3] ||
|
844 |
|
|
(res_inFstHalf_usedReg_dataReg[17:15] == 3'd0)
|
845 |
|
|
: (res_inFstHalf_usedReg_dataReg[17:15] == 3'd0)) ||
|
846 |
|
|
(res_inSndHalf_usedReg_dataReg[17:15] == 3'd0)) &&
|
847 |
|
|
(((res_nextTokW.whas
|
848 |
|
|
? res_nextTokW.wget[20:18]
|
849 |
|
|
: _) ==
|
850 |
|
|
3'd0) ||
|
851 |
|
|
(((res_scheduler_last[3]
|
852 |
|
|
? res_scheduler_last[2:0]
|
853 |
|
|
: _) ==
|
854 |
|
|
3'd6)
|
855 |
|
|
? res_scheduler_last[3] ||
|
856 |
|
|
(res_inFstHalf_usedReg_dataReg[20:18] == 3'd0)
|
857 |
|
|
: (res_inFstHalf_usedReg_dataReg[20:18] == 3'd0)) ||
|
858 |
|
|
(res_inSndHalf_usedReg_dataReg[20:18] == 3'd0)) &&
|
859 |
|
|
(((res_nextTokW.whas
|
860 |
|
|
? res_nextTokW.wget[23:21]
|
861 |
|
|
: _) ==
|
862 |
|
|
3'd0) ||
|
863 |
|
|
(((res_scheduler_last[3]
|
864 |
|
|
? res_scheduler_last[2:0]
|
865 |
|
|
: _) ==
|
866 |
|
|
3'd7)
|
867 |
|
|
? res_scheduler_last[3] ||
|
868 |
|
|
(res_inFstHalf_usedReg_dataReg[23:21] == 3'd0)
|
869 |
|
|
: (res_inFstHalf_usedReg_dataReg[23:21] == 3'd0)) ||
|
870 |
|
|
(res_inSndHalf_usedReg_dataReg[23:21] == 3'd0))) ||
|
871 |
|
|
((((! ((res_nextTokW.whas
|
872 |
|
|
? res_nextTokW.wget[2:0]
|
873 |
|
|
: _) ==
|
874 |
|
|
3'd0)) &&
|
875 |
|
|
(((res_scheduler_last[3]
|
876 |
|
|
? res_scheduler_last[2:0]
|
877 |
|
|
: _) ==
|
878 |
|
|
3'd0)
|
879 |
|
|
? (! res_scheduler_last[3]) &&
|
880 |
|
|
(((res_scheduler_last[3]
|
881 |
|
|
? res_scheduler_last[2:0]
|
882 |
|
|
: _) ==
|
883 |
|
|
3'd0)
|
884 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[2:0] == 3'd0)
|
885 |
|
|
: (((res_scheduler_last[3]
|
886 |
|
|
? res_scheduler_last[2:0]
|
887 |
|
|
: _) ==
|
888 |
|
|
3'd1)
|
889 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[5:3] == 3'd0)
|
890 |
|
|
: (((res_scheduler_last[3]
|
891 |
|
|
? res_scheduler_last[2:0]
|
892 |
|
|
: _) ==
|
893 |
|
|
3'd2)
|
894 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[8:6] == 3'd0)
|
895 |
|
|
: (((res_scheduler_last___d1083(...)[3]
|
896 |
|
|
? res_scheduler_last___d1083(...)[2:0]
|
897 |
|
|
: _) ==
|
898 |
|
|
3'd3)
|
899 |
|
|
? ! (res_inFstHalf_usedReg_dataReg__h11884(...)[11:9] ==
|
900 |
|
|
3'd0)
|
901 |
|
|
: (((res_scheduler_last_36_BIT_3___d1029(...)
|
902 |
|
|
? res_scheduler_last_36_BITS_2_TO_0___d1209(...)
|
903 |
|
|
: _) ==
|
904 |
|
|
3'd4)
|
905 |
|
|
? ! (n__h36630(...) == 3'd0)
|
906 |
|
|
: ((idx__h92163(...) == 3'd5)
|
907 |
|
|
? ! res_inFstHalf_usedReg_dataReg_41_BITS_17_TO_15_ETC___d970(...)
|
908 |
|
|
: (IF_res_scheduler_last_36_BIT_3_37_THEN_res_sch_ETC___d1215(...)
|
909 |
|
|
? NOT_res_inFstHalf_usedReg_dataReg_41_BITS_20_T_ETC___d1173(...)
|
910 |
|
|
: IF_IF_res_scheduler_last_36_BIT_3_37_THEN_res__ETC___d179(...))))))))
|
911 |
|
|
: (! (res_inFstHalf_usedReg_dataReg[2:0] == 3'd0))) &&
|
912 |
|
|
(! (res_inSndHalf_usedReg_dataReg[2:0] == 3'd0))) ||
|
913 |
|
|
((! ((res_nextTokW.whas
|
914 |
|
|
? res_nextTokW.wget[5:3]
|
915 |
|
|
: _) ==
|
916 |
|
|
3'd0)) &&
|
917 |
|
|
(((res_scheduler_last[3]
|
918 |
|
|
? res_scheduler_last[2:0]
|
919 |
|
|
: _) ==
|
920 |
|
|
3'd1)
|
921 |
|
|
? (! res_scheduler_last[3]) &&
|
922 |
|
|
(((res_scheduler_last[3]
|
923 |
|
|
? res_scheduler_last[2:0]
|
924 |
|
|
: _) ==
|
925 |
|
|
3'd0)
|
926 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[2:0] == 3'd0)
|
927 |
|
|
: (((res_scheduler_last[3]
|
928 |
|
|
? res_scheduler_last[2:0]
|
929 |
|
|
: _) ==
|
930 |
|
|
3'd1)
|
931 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[5:3] == 3'd0)
|
932 |
|
|
: (((res_scheduler_last[3]
|
933 |
|
|
? res_scheduler_last[2:0]
|
934 |
|
|
: _) ==
|
935 |
|
|
3'd2)
|
936 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[8:6] == 3'd0)
|
937 |
|
|
: (((res_scheduler_last___d1083(...)[3]
|
938 |
|
|
? res_scheduler_last___d1083(...)[2:0]
|
939 |
|
|
: _) ==
|
940 |
|
|
3'd3)
|
941 |
|
|
? ! (res_inFstHalf_usedReg_dataReg__h11884(...)[11:9] ==
|
942 |
|
|
3'd0)
|
943 |
|
|
: (((res_scheduler_last_36_BIT_3___d1029(...)
|
944 |
|
|
? res_scheduler_last_36_BITS_2_TO_0___d1209(...)
|
945 |
|
|
: _) ==
|
946 |
|
|
3'd4)
|
947 |
|
|
? ! (n__h36630(...) == 3'd0)
|
948 |
|
|
: ((idx__h92163(...) == 3'd5)
|
949 |
|
|
? ! res_inFstHalf_usedReg_dataReg_41_BITS_17_TO_15_ETC___d970(...)
|
950 |
|
|
: (IF_res_scheduler_last_36_BIT_3_37_THEN_res_sch_ETC___d1215(...)
|
951 |
|
|
? NOT_res_inFstHalf_usedReg_dataReg_41_BITS_20_T_ETC___d1173(...)
|
952 |
|
|
: IF_IF_res_scheduler_last_36_BIT_3_37_THEN_res__ETC___d179(...))))))))
|
953 |
|
|
: (! (res_inFstHalf_usedReg_dataReg[5:3] == 3'd0))) &&
|
954 |
|
|
(! (res_inSndHalf_usedReg_dataReg[5:3] == 3'd0))) ||
|
955 |
|
|
((! ((res_nextTokW.whas
|
956 |
|
|
? res_nextTokW.wget[8:6]
|
957 |
|
|
: _) ==
|
958 |
|
|
3'd0)) &&
|
959 |
|
|
(((res_scheduler_last[3]
|
960 |
|
|
? res_scheduler_last[2:0]
|
961 |
|
|
: _) ==
|
962 |
|
|
3'd2)
|
963 |
|
|
? (! res_scheduler_last[3]) &&
|
964 |
|
|
(((res_scheduler_last[3]
|
965 |
|
|
? res_scheduler_last[2:0]
|
966 |
|
|
: _) ==
|
967 |
|
|
3'd0)
|
968 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[2:0] == 3'd0)
|
969 |
|
|
: (((res_scheduler_last[3]
|
970 |
|
|
? res_scheduler_last[2:0]
|
971 |
|
|
: _) ==
|
972 |
|
|
3'd1)
|
973 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[5:3] == 3'd0)
|
974 |
|
|
: (((res_scheduler_last[3]
|
975 |
|
|
? res_scheduler_last[2:0]
|
976 |
|
|
: _) ==
|
977 |
|
|
3'd2)
|
978 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[8:6] == 3'd0)
|
979 |
|
|
: (((res_scheduler_last___d1083(...)[3]
|
980 |
|
|
? res_scheduler_last___d1083(...)[2:0]
|
981 |
|
|
: _) ==
|
982 |
|
|
3'd3)
|
983 |
|
|
? ! (res_inFstHalf_usedReg_dataReg__h11884(...)[11:9] ==
|
984 |
|
|
3'd0)
|
985 |
|
|
: (((res_scheduler_last_36_BIT_3___d1029(...)
|
986 |
|
|
? res_scheduler_last_36_BITS_2_TO_0___d1209(...)
|
987 |
|
|
: _) ==
|
988 |
|
|
3'd4)
|
989 |
|
|
? ! (n__h36630(...) == 3'd0)
|
990 |
|
|
: ((idx__h92163(...) == 3'd5)
|
991 |
|
|
? ! res_inFstHalf_usedReg_dataReg_41_BITS_17_TO_15_ETC___d970(...)
|
992 |
|
|
: (IF_res_scheduler_last_36_BIT_3_37_THEN_res_sch_ETC___d1215(...)
|
993 |
|
|
? NOT_res_inFstHalf_usedReg_dataReg_41_BITS_20_T_ETC___d1173(...)
|
994 |
|
|
: IF_IF_res_scheduler_last_36_BIT_3_37_THEN_res__ETC___d179(...))))))))
|
995 |
|
|
: (! (res_inFstHalf_usedReg_dataReg[8:6] == 3'd0))) &&
|
996 |
|
|
(! (res_inSndHalf_usedReg_dataReg[8:6] == 3'd0))) ||
|
997 |
|
|
((! ((res_nextTokW.whas
|
998 |
|
|
? res_nextTokW.wget[11:9]
|
999 |
|
|
: _) ==
|
1000 |
|
|
3'd0)) &&
|
1001 |
|
|
(((res_scheduler_last[3]
|
1002 |
|
|
? res_scheduler_last[2:0]
|
1003 |
|
|
: _) ==
|
1004 |
|
|
3'd3)
|
1005 |
|
|
? (! res_scheduler_last[3]) &&
|
1006 |
|
|
(((res_scheduler_last[3]
|
1007 |
|
|
? res_scheduler_last[2:0]
|
1008 |
|
|
: _) ==
|
1009 |
|
|
3'd0)
|
1010 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[2:0] == 3'd0)
|
1011 |
|
|
: (((res_scheduler_last[3]
|
1012 |
|
|
? res_scheduler_last[2:0]
|
1013 |
|
|
: _) ==
|
1014 |
|
|
3'd1)
|
1015 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[5:3] == 3'd0)
|
1016 |
|
|
: (((res_scheduler_last[3]
|
1017 |
|
|
? res_scheduler_last[2:0]
|
1018 |
|
|
: _) ==
|
1019 |
|
|
3'd2)
|
1020 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[8:6] == 3'd0)
|
1021 |
|
|
: (((res_scheduler_last___d1083(...)[3]
|
1022 |
|
|
? res_scheduler_last___d1083(...)[2:0]
|
1023 |
|
|
: _) ==
|
1024 |
|
|
3'd3)
|
1025 |
|
|
? ! (res_inFstHalf_usedReg_dataReg__h11884(...)[11:9] ==
|
1026 |
|
|
3'd0)
|
1027 |
|
|
: (((res_scheduler_last_36_BIT_3___d1029(...)
|
1028 |
|
|
? res_scheduler_last_36_BITS_2_TO_0___d1209(...)
|
1029 |
|
|
: _) ==
|
1030 |
|
|
3'd4)
|
1031 |
|
|
? ! (n__h36630(...) == 3'd0)
|
1032 |
|
|
: ((idx__h92163(...) == 3'd5)
|
1033 |
|
|
? ! res_inFstHalf_usedReg_dataReg_41_BITS_17_TO_15_ETC___d970(...)
|
1034 |
|
|
: (IF_res_scheduler_last_36_BIT_3_37_THEN_res_sch_ETC___d1215(...)
|
1035 |
|
|
? NOT_res_inFstHalf_usedReg_dataReg_41_BITS_20_T_ETC___d1173(...)
|
1036 |
|
|
: IF_IF_res_scheduler_last_36_BIT_3_37_THEN_res__ETC___d179(...))))))))
|
1037 |
|
|
: (! (res_inFstHalf_usedReg_dataReg[11:9] == 3'd0))) &&
|
1038 |
|
|
(! (res_inSndHalf_usedReg_dataReg[11:9] == 3'd0))))
|
1039 |
|
|
? ((! ((res_nextTokW.whas
|
1040 |
|
|
? res_nextTokW.wget[2:0]
|
1041 |
|
|
: _) ==
|
1042 |
|
|
3'd0)) &&
|
1043 |
|
|
(((res_scheduler_last[3]
|
1044 |
|
|
? res_scheduler_last[2:0]
|
1045 |
|
|
: _) ==
|
1046 |
|
|
3'd0)
|
1047 |
|
|
? (! res_scheduler_last[3]) &&
|
1048 |
|
|
(((res_scheduler_last[3]
|
1049 |
|
|
? res_scheduler_last[2:0]
|
1050 |
|
|
: _) ==
|
1051 |
|
|
3'd0)
|
1052 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[2:0] == 3'd0)
|
1053 |
|
|
: (((res_scheduler_last[3]
|
1054 |
|
|
? res_scheduler_last[2:0]
|
1055 |
|
|
: _) ==
|
1056 |
|
|
3'd1)
|
1057 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[5:3] == 3'd0)
|
1058 |
|
|
: (((res_scheduler_last[3]
|
1059 |
|
|
? res_scheduler_last[2:0]
|
1060 |
|
|
: _) ==
|
1061 |
|
|
3'd2)
|
1062 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[8:6] == 3'd0)
|
1063 |
|
|
: (((res_scheduler_last___d1083(...)[3]
|
1064 |
|
|
? res_scheduler_last___d1083(...)[2:0]
|
1065 |
|
|
: _) ==
|
1066 |
|
|
3'd3)
|
1067 |
|
|
? ! (res_inFstHalf_usedReg_dataReg__h11884(...)[11:9] ==
|
1068 |
|
|
3'd0)
|
1069 |
|
|
: (((res_scheduler_last_36_BIT_3___d1029(...)
|
1070 |
|
|
? res_scheduler_last_36_BITS_2_TO_0___d1209(...)
|
1071 |
|
|
: _) ==
|
1072 |
|
|
3'd4)
|
1073 |
|
|
? ! (n__h36630(...) == 3'd0)
|
1074 |
|
|
: ((idx__h92163(...) == 3'd5)
|
1075 |
|
|
? ! res_inFstHalf_usedReg_dataReg_41_BITS_17_TO_15_ETC___d970(...)
|
1076 |
|
|
: (IF_res_scheduler_last_36_BIT_3_37_THEN_res_sch_ETC___d1215(...)
|
1077 |
|
|
? NOT_res_inFstHalf_usedReg_dataReg_41_BITS_20_T_ETC___d1173(...)
|
1078 |
|
|
: IF_IF_res_scheduler_last_36_BIT_3_37_THEN_res__ETC___d179(...))))))))
|
1079 |
|
|
: (! (res_inFstHalf_usedReg_dataReg[2:0] == 3'd0))) &&
|
1080 |
|
|
(! (res_inSndHalf_usedReg_dataReg[2:0] == 3'd0))) ||
|
1081 |
|
|
((! ((res_nextTokW.whas
|
1082 |
|
|
? res_nextTokW.wget[5:3]
|
1083 |
|
|
: _) ==
|
1084 |
|
|
3'd0)) &&
|
1085 |
|
|
(((res_scheduler_last[3]
|
1086 |
|
|
? res_scheduler_last[2:0]
|
1087 |
|
|
: _) ==
|
1088 |
|
|
3'd1)
|
1089 |
|
|
? (! res_scheduler_last[3]) &&
|
1090 |
|
|
(((res_scheduler_last[3]
|
1091 |
|
|
? res_scheduler_last[2:0]
|
1092 |
|
|
: _) ==
|
1093 |
|
|
3'd0)
|
1094 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[2:0] == 3'd0)
|
1095 |
|
|
: (((res_scheduler_last[3]
|
1096 |
|
|
? res_scheduler_last[2:0]
|
1097 |
|
|
: _) ==
|
1098 |
|
|
3'd1)
|
1099 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[5:3] == 3'd0)
|
1100 |
|
|
: (((res_scheduler_last[3]
|
1101 |
|
|
? res_scheduler_last[2:0]
|
1102 |
|
|
: _) ==
|
1103 |
|
|
3'd2)
|
1104 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[8:6] == 3'd0)
|
1105 |
|
|
: (((res_scheduler_last___d1083(...)[3]
|
1106 |
|
|
? res_scheduler_last___d1083(...)[2:0]
|
1107 |
|
|
: _) ==
|
1108 |
|
|
3'd3)
|
1109 |
|
|
? ! (res_inFstHalf_usedReg_dataReg__h11884(...)[11:9] ==
|
1110 |
|
|
3'd0)
|
1111 |
|
|
: (((res_scheduler_last_36_BIT_3___d1029(...)
|
1112 |
|
|
? res_scheduler_last_36_BITS_2_TO_0___d1209(...)
|
1113 |
|
|
: _) ==
|
1114 |
|
|
3'd4)
|
1115 |
|
|
? ! (n__h36630(...) == 3'd0)
|
1116 |
|
|
: ((idx__h92163(...) == 3'd5)
|
1117 |
|
|
? ! res_inFstHalf_usedReg_dataReg_41_BITS_17_TO_15_ETC___d970(...)
|
1118 |
|
|
: (IF_res_scheduler_last_36_BIT_3_37_THEN_res_sch_ETC___d1215(...)
|
1119 |
|
|
? NOT_res_inFstHalf_usedReg_dataReg_41_BITS_20_T_ETC___d1173(...)
|
1120 |
|
|
: IF_IF_res_scheduler_last_36_BIT_3_37_THEN_res__ETC___d179(...))))))))
|
1121 |
|
|
: (! (res_inFstHalf_usedReg_dataReg[5:3] == 3'd0))) &&
|
1122 |
|
|
(! (res_inSndHalf_usedReg_dataReg[5:3] == 3'd0))) ||
|
1123 |
|
|
((((res_nextTokW.whas
|
1124 |
|
|
? res_nextTokW.wget[8:6]
|
1125 |
|
|
: _) ==
|
1126 |
|
|
3'd0) ||
|
1127 |
|
|
res_inFstHalf_finishInit) &&
|
1128 |
|
|
(((res_nextTokW.whas
|
1129 |
|
|
? res_nextTokW.wget[8:6]
|
1130 |
|
|
: _) ==
|
1131 |
|
|
3'd0) ||
|
1132 |
|
|
(((res_scheduler_last[3]
|
1133 |
|
|
? res_scheduler_last[2:0]
|
1134 |
|
|
: _) ==
|
1135 |
|
|
3'd2)
|
1136 |
|
|
? res_scheduler_last[3] ||
|
1137 |
|
|
(res_inFstHalf_usedReg_dataReg[8:6] == 3'd0)
|
1138 |
|
|
: (res_inFstHalf_usedReg_dataReg[8:6] == 3'd0)) ||
|
1139 |
|
|
res_inSndHalf_finishInit))
|
1140 |
|
|
: ((((res_nextTokW.whas
|
1141 |
|
|
? res_nextTokW.wget[14:12]
|
1142 |
|
|
: _) ==
|
1143 |
|
|
3'd0) ||
|
1144 |
|
|
res_inFstHalf_finishInit) &&
|
1145 |
|
|
(((res_nextTokW.whas
|
1146 |
|
|
? res_nextTokW.wget[14:12]
|
1147 |
|
|
: _) ==
|
1148 |
|
|
3'd0) ||
|
1149 |
|
|
(((res_scheduler_last[3]
|
1150 |
|
|
? res_scheduler_last[2:0]
|
1151 |
|
|
: _) ==
|
1152 |
|
|
3'd4)
|
1153 |
|
|
? res_scheduler_last[3] ||
|
1154 |
|
|
(res_inFstHalf_usedReg_dataReg[14:12] == 3'd0)
|
1155 |
|
|
: (res_inFstHalf_usedReg_dataReg[14:12] == 3'd0)) ||
|
1156 |
|
|
res_inSndHalf_finishInit) &&
|
1157 |
|
|
(((! ((res_nextTokW.whas
|
1158 |
|
|
? res_nextTokW.wget[14:12]
|
1159 |
|
|
: _) ==
|
1160 |
|
|
3'd0)) &&
|
1161 |
|
|
(((res_scheduler_last[3]
|
1162 |
|
|
? res_scheduler_last[2:0]
|
1163 |
|
|
: _) ==
|
1164 |
|
|
3'd4)
|
1165 |
|
|
? (! res_scheduler_last[3]) &&
|
1166 |
|
|
(((res_scheduler_last[3]
|
1167 |
|
|
? res_scheduler_last[2:0]
|
1168 |
|
|
: _) ==
|
1169 |
|
|
3'd0)
|
1170 |
|
|
? ! (res_inFstHalf_usedReg_dataReg[2:0] == 3'd0)
|
1171 |
|
|
: (((res_scheduler_last___d1083(...)[3]
|
1172 |
|
|
? res_scheduler_last___d1083(...)[2:0]
|
1173 |
|
|
: _) ==
|
1174 |
|
|
3'd1)
|
1175 |
|
|
? ! (res_inFstHalf_usedReg_dataReg__h11884(...)[5:3] ==
|
1176 |
|
|
3'd0)
|
1177 |
|
|
: (((res_scheduler_last_36_BIT_3___d1029(...)
|
1178 |
|
|
? res_scheduler_last_36_BITS_2_TO_0___d1209(...)
|
1179 |
|
|
: _) ==
|
1180 |
|
|
3'd2)
|
1181 |
|
|
? ! (n__h36654(...) == 3'd0)
|
1182 |
|
|
: ((idx__h92163(...) == 3'd3)
|
1183 |
|
|
? ! res_inFstHalf_usedReg_dataReg_41_BITS_11_TO_9__ETC___d1018(...)
|
1184 |
|
|
: (IF_res_scheduler_last_36_BIT_3_37_THEN_res_sch_ETC___d1213(...)
|
1185 |
|
|
? NOT_res_inFstHalf_usedReg_dataReg_41_BITS_14_T_ETC___d1171(...)
|
1186 |
|
|
: IF_IF_res_scheduler_last_36_BIT_3_37_THEN_res__ETC___d181(...))))))
|
1187 |
|
|
: (! (res_inFstHalf_usedReg_dataReg[14:12] == 3'd0))) &&
|
1188 |
|
|
(! (res_inSndHalf_usedReg_dataReg[14:12] == 3'd0)))
|
1189 |
|
|
? res_inFstHalf_finishInit && res_inSndHalf_finishInit
|
1190 |
|
|
: ((((res_nextTokW.whas
|
1191 |
|
|
? res_nextTokW.wget[17:15]
|
1192 |
|
|
: _) ==
|
1193 |
|
|
3'd0) ||
|
1194 |
|
|
res_inFstHalf_finishInit) &&
|
1195 |
|
|
(((res_nextTokW.whas
|
1196 |
|
|
? res_nextTokW.wget[17:15]
|
1197 |
|
|
: _) ==
|
1198 |
|
|
3'd0) ||
|
1199 |
|
|
(((res_scheduler_last[3]
|
1200 |
|
|
? res_scheduler_last[2:0]
|
1201 |
|
|
: _) ==
|
1202 |
|
|
3'd5)
|
1203 |
|
|
? res_scheduler_last[3] ||
|
1204 |
|
|
(res_inFstHalf_usedReg_dataReg[17:15] == 3'd0)
|
1205 |
|
|
: (res_inFstHalf_usedReg_dataReg[17:15] == 3'd0)) ||
|
1206 |
|
|
res_inSndHalf_finishInit))) &&
|
1207 |
|
|
(((! ((res_nextTokW.whas
|
1208 |
|
|
? res_nextTokW.wget[14:12]
|
1209 |
|
|
: _) ==
|
1210 |
|
|
3'd0)) &&
|
1211 |
|
|
(((res_scheduler_last[3]
|
1212 |
|
|
? res_scheduler_last[2:0]
|
1213 |
|
|
: _) ==
|
1214 |
|
|
3'd4)
|
1215 |
|
|
? (! res_scheduler_last[3]) &&
|
1216 |
|
|
(((res_scheduler_last___d1083(...)[3]
|
1217 |
|
|
? res_scheduler_last___d1083(...)[2:0]
|
1218 |
|
|
: _) ==
|
1219 |
|
|
3'd0)
|
1220 |
|
|
? ! (res_inFstHalf_usedReg_dataReg__h11884(...)[2:0] ==
|
1221 |
|
|
3'd0)
|
1222 |
|
|
: (((res_scheduler_last_36_BIT_3___d1029(...)
|
1223 |
|
|
? res_scheduler_last_36_BITS_2_TO_0___d1209(...)
|
1224 |
|
|
: _) ==
|
1225 |
|
|
3'd1)
|
1226 |
|
|
? ! (n__h36666(...) == 3'd0)
|
1227 |
|
|
: ((idx__h92163(...) == 3'd2)
|
1228 |
|
|
? ! res_inFstHalf_usedReg_dataReg_41_BITS_8_TO_6_5_ETC___d1016(...)
|
1229 |
|
|
: (IF_res_scheduler_last_36_BIT_3_37_THEN_res_sch_ETC___d1212(...)
|
1230 |
|
|
? NOT_res_inFstHalf_usedReg_dataReg_41_BITS_11_T_ETC___d1170(...)
|
1231 |
|
|
: IF_IF_res_scheduler_last_36_BIT_3_37_THEN_res__ETC___d182(...)))))
|
1232 |
|
|
: (! (res_inFstHalf_usedReg_dataReg[14:12] == 3'd0))) &&
|
1233 |
|
|
(! (res_inSndHalf_usedReg_dataReg[14:12] == 3'd0))) ||
|
1234 |
|
|
((! ((res_nextTokW.whas
|
1235 |
|
|
? res_nextTokW.wget[17:15]
|
1236 |
|
|
: _) ==
|
1237 |
|
|
3'd0)) &&
|
1238 |
|
|
(((res_scheduler_last[3]
|
1239 |
|
|
? res_scheduler_last[2:0]
|
1240 |
|
|
: _) ==
|
1241 |
|
|
3'd5)
|
1242 |
|
|
? (! res_scheduler_last[3]) &&
|
1243 |
|
|
(((res_scheduler_last___d1083(...)[3]
|
1244 |
|
|
? res_scheduler_last___d1083(...)[2:0]
|
1245 |
|
|
: _) ==
|
1246 |
|
|
3'd0)
|
1247 |
|
|
? ! (res_inFstHalf_usedReg_dataReg__h11884(...)[2:0] ==
|
1248 |
|
|
3'd0)
|
1249 |
|
|
: (((res_scheduler_last_36_BIT_3___d1029(...)
|
1250 |
|
|
? res_scheduler_last_36_BITS_2_TO_0___d1209(...)
|
1251 |
|
|
: _) ==
|
1252 |
|
|
3'd1)
|
1253 |
|
|
? ! (n__h36666(...) == 3'd0)
|
1254 |
|
|
: ((idx__h92163(...) == 3'd2)
|
1255 |
|
|
? ! res_inFstHalf_usedReg_dataReg_41_BITS_8_TO_6_5_ETC___d1016(...)
|
1256 |
|
|
: (IF_res_scheduler_last_36_BIT_3_37_THEN_res_sch_ETC___d1212(...)
|
1257 |
|
|
? NOT_res_inFstHalf_usedReg_dataReg_41_BITS_11_T_ETC___d1170(...)
|
1258 |
|
|
: IF_IF_res_scheduler_last_36_BIT_3_37_THEN_res__ETC___d182(...)))))
|
1259 |
|
|
: (! (res_inFstHalf_usedReg_dataReg[17:15] == 3'd0))) &&
|
1260 |
|
|
(! (res_inSndHalf_usedReg_dataReg[17:15] == 3'd0))) ||
|
1261 |
|
|
((((res_nextTokW.whas
|
1262 |
|
|
? res_nextTokW.wget[20:18]
|
1263 |
|
|
: _) ==
|
1264 |
|
|
3'd0) ||
|
1265 |
|
|
res_inFstHalf_finishInit) &&
|
1266 |
|
|
(((res_nextTokW.whas
|
1267 |
|
|
? res_nextTokW.wget[20:18]
|
1268 |
|
|
: _) ==
|
1269 |
|
|
3'd0) ||
|
1270 |
|
|
(((res_scheduler_last[3]
|
1271 |
|
|
? res_scheduler_last[2:0]
|
1272 |
|
|
: _) ==
|
1273 |
|
|
3'd6)
|
1274 |
|
|
? res_scheduler_last[3] ||
|
1275 |
|
|
(res_inFstHalf_usedReg_dataReg[20:18] == 3'd0)
|
1276 |
|
|
: (res_inFstHalf_usedReg_dataReg[20:18] == 3'd0)) ||
|
1277 |
|
|
res_inSndHalf_finishInit))))))
|
1278 |
|
|
Blocking rules: (none)
|
1279 |
|
|
|
1280 |
|
|
Rule: res_inSndHalf_processDecrFree
|
1281 |
|
|
Predicate: res_inSndHalf_finishInit &&
|
1282 |
|
|
res_inSndHalf_decrFreeIdx.whas && res_inSndHalf_decrFreeIdx.wget[3]
|
1283 |
|
|
Blocking rules: (none)
|
1284 |
|
|
|
1285 |
|
|
Rule: res_inSndHalf_processFirstReq
|
1286 |
|
|
Predicate: res_inSndHalf_finishInit &&
|
1287 |
|
|
res_inSndHalf_firstIdx.whas && res_inSndHalf_firstIdx.wget[3]
|
1288 |
|
|
Blocking rules: (none)
|
1289 |
|
|
|
1290 |
|
|
Rule: res_inSndHalf_processDeq
|
1291 |
|
|
Predicate: res_inSndHalf_finishInit &&
|
1292 |
|
|
res_inSndHalf_deqIdx.whas && res_inSndHalf_deqIdx.wget[3]
|
1293 |
|
|
Blocking rules: (none)
|
1294 |
|
|
|
1295 |
|
|
Rule: res_inSndHalf_updateFreeReg
|
1296 |
|
|
Predicate: res_inSndHalf_lastDeqIdx[3]
|
1297 |
|
|
Blocking rules: (none)
|
1298 |
|
|
|
1299 |
|
|
Rule: res_inSndHalf_updateUsedReg
|
1300 |
|
|
Predicate: res_inSndHalf_lastEnqIdx[3]
|
1301 |
|
|
Blocking rules: (none)
|
1302 |
|
|
|
1303 |
|
|
Rule: res_inSndHalf_processEnq
|
1304 |
|
|
Predicate: res_inSndHalf_finishInit &&
|
1305 |
|
|
res_inSndHalf_enqIdx.whas && res_inSndHalf_enqIdx.wget[3]
|
1306 |
|
|
Blocking rules: (none)
|
1307 |
|
|
|
1308 |
|
|
Rule: res_inSndHalf_initialization
|
1309 |
|
|
Predicate: ! res_inSndHalf_finishInit
|
1310 |
|
|
Blocking rules: (none)
|
1311 |
|
|
|
1312 |
|
|
Rule: res_inSndHalf_lastDeqIdx__dreg_update
|
1313 |
|
|
Predicate: True
|
1314 |
|
|
Blocking rules: (none)
|
1315 |
|
|
|
1316 |
|
|
Rule: res_inSndHalf_lastEnqIdx__dreg_update
|
1317 |
|
|
Predicate: True
|
1318 |
|
|
Blocking rules: (none)
|
1319 |
|
|
|
1320 |
|
|
Rule: res_inSndHalf_freeReg_updateReg
|
1321 |
|
|
Predicate: True
|
1322 |
|
|
Blocking rules: (none)
|
1323 |
|
|
|
1324 |
|
|
Rule: res_inSndHalf_usedReg_updateReg
|
1325 |
|
|
Predicate: True
|
1326 |
|
|
Blocking rules: (none)
|
1327 |
|
|
|
1328 |
|
|
Rule: res_inFstHalf_processDecrFree
|
1329 |
|
|
Predicate: res_inFstHalf_finishInit &&
|
1330 |
|
|
res_inFstHalf_decrFreeIdx.whas && res_inFstHalf_decrFreeIdx.wget[3]
|
1331 |
|
|
Blocking rules: (none)
|
1332 |
|
|
|
1333 |
|
|
Rule: res_inFstHalf_processFirstReq
|
1334 |
|
|
Predicate: res_inFstHalf_finishInit &&
|
1335 |
|
|
res_inFstHalf_firstIdx.whas && res_inFstHalf_firstIdx.wget[3]
|
1336 |
|
|
Blocking rules: (none)
|
1337 |
|
|
|
1338 |
|
|
Rule: res_inFstHalf_processDeq
|
1339 |
|
|
Predicate: res_inFstHalf_finishInit &&
|
1340 |
|
|
res_inFstHalf_deqIdx.whas && res_inFstHalf_deqIdx.wget[3]
|
1341 |
|
|
Blocking rules: (none)
|
1342 |
|
|
|
1343 |
|
|
Rule: res_inFstHalf_updateFreeReg
|
1344 |
|
|
Predicate: res_inFstHalf_lastDeqIdx[3]
|
1345 |
|
|
Blocking rules: (none)
|
1346 |
|
|
|
1347 |
|
|
Rule: res_inFstHalf_updateUsedReg
|
1348 |
|
|
Predicate: res_inFstHalf_lastEnqIdx[3]
|
1349 |
|
|
Blocking rules: (none)
|
1350 |
|
|
|
1351 |
|
|
Rule: res_inFstHalf_processEnq
|
1352 |
|
|
Predicate: res_inFstHalf_finishInit &&
|
1353 |
|
|
res_inFstHalf_enqIdx.whas && res_inFstHalf_enqIdx.wget[3]
|
1354 |
|
|
Blocking rules: (none)
|
1355 |
|
|
|
1356 |
|
|
Rule: res_inFstHalf_initialization
|
1357 |
|
|
Predicate: ! res_inFstHalf_finishInit
|
1358 |
|
|
Blocking rules: (none)
|
1359 |
|
|
|
1360 |
|
|
Rule: res_inFstHalf_lastDeqIdx__dreg_update
|
1361 |
|
|
Predicate: True
|
1362 |
|
|
Blocking rules: (none)
|
1363 |
|
|
|
1364 |
|
|
Rule: res_inFstHalf_lastEnqIdx__dreg_update
|
1365 |
|
|
Predicate: True
|
1366 |
|
|
Blocking rules: (none)
|
1367 |
|
|
|
1368 |
|
|
Rule: res_inFstHalf_freeReg_updateReg
|
1369 |
|
|
Predicate: True
|
1370 |
|
|
Blocking rules: (none)
|
1371 |
|
|
|
1372 |
|
|
Rule: res_inFstHalf_usedReg_updateReg
|
1373 |
|
|
Predicate: True
|
1374 |
|
|
Blocking rules: (none)
|
1375 |
|
|
|
1376 |
|
|
Logical execution order: outStream_putTokInfo,
|
1377 |
|
|
inStream_putRecord,
|
1378 |
|
|
inStream_putDeqTok,
|
1379 |
|
|
inStream_getTokInfo,
|
1380 |
|
|
res_feedScheduler,
|
1381 |
|
|
res_nextToProcess,
|
1382 |
|
|
outStream_getDeqTok_snd,
|
1383 |
|
|
outStream_getDeqTok_fst,
|
1384 |
|
|
res_compares,
|
1385 |
|
|
outStream_getRecord_snd,
|
1386 |
|
|
outStream_getRecord_fst,
|
1387 |
|
|
res_inSndHalf_processFirstReq,
|
1388 |
|
|
res_inSndHalf_updateFreeReg,
|
1389 |
|
|
res_inSndHalf_processDecrFree,
|
1390 |
|
|
res_inSndHalf_updateUsedReg,
|
1391 |
|
|
res_inSndHalf_processDeq,
|
1392 |
|
|
res_inSndHalf_processEnq,
|
1393 |
|
|
res_inSndHalf_initialization,
|
1394 |
|
|
res_inSndHalf_lastDeqIdx__dreg_update,
|
1395 |
|
|
res_inSndHalf_lastEnqIdx__dreg_update,
|
1396 |
|
|
res_inSndHalf_freeReg_updateReg,
|
1397 |
|
|
res_inSndHalf_usedReg_updateReg,
|
1398 |
|
|
res_inFstHalf_processFirstReq,
|
1399 |
|
|
res_inFstHalf_updateFreeReg,
|
1400 |
|
|
res_inFstHalf_processDecrFree,
|
1401 |
|
|
res_inFstHalf_updateUsedReg,
|
1402 |
|
|
res_inFstHalf_processDeq,
|
1403 |
|
|
res_inFstHalf_processEnq,
|
1404 |
|
|
res_inFstHalf_initialization,
|
1405 |
|
|
res_inFstHalf_lastDeqIdx__dreg_update,
|
1406 |
|
|
res_inFstHalf_lastEnqIdx__dreg_update,
|
1407 |
|
|
res_inFstHalf_freeReg_updateReg,
|
1408 |
|
|
res_inFstHalf_usedReg_updateReg
|
1409 |
|
|
|
1410 |
|
|
==========================================================
|