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[/] [cryptosorter/] [trunk/] [memocodeDesignContest2008/] [xup/] [PLBMaster/] [PLBModel.bsv] - Blame information for rev 6

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/*
Copyright (c) 2007 MIT
 
Permission is hereby granted, free of charge, to any person
obtaining a copy of this software and associated documentation
files (the "Software"), to deal in the Software without
restriction, including without limitation the rights to use,
copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following
conditions:
 
The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.
 
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
OTHER DEALINGS IN THE SOFTWARE.
 
Author: Kermin Fleming
*/
 
import Types::*;
import Parameters::*;
import Interfaces::*;
import DebugFlags::*;
import PLBMasterWires::*;
import RegFile::*;
 
module mkPLBModel#(PLBMasterWires plb) ();
 
  RegFile#(Bit#(20), Bit#(32))  matrixA <- mkRegFileFullLoad("invert.hex");
  RegFile#(Bit#(20), Bit#(32))  matrixB <- mkRegFileFull();
  RegFile#(Bit#(20), Bit#(32))  matrixC <- mkRegFileFull();
  RegFile#(Bit#(20), Bit#(32))  scratch <- mkRegFileFull();
 
  Reg#(Bit#(PLBAddrSize)) curAddr <- mkReg(0);
  Reg#(Bit#(8)) transferSize      <- mkReg(0);
 
  Reg#(Bit#(32)) wrValue          <- mkReg(0);
 
  Reg#(Bool) doingRead            <- mkReg(False);
  Reg#(Bool) doingWrite           <- mkReg(False);
 
  Reg#(Maybe#(Bit#(64))) readValue <- mkReg(Nothing);
 
  Reg#(Bit#(PLBAddrSize)) mABus     <- mkReg(0);
  Reg#(Bit#(8))           mBE       <- mkReg(0);
  Reg#(Bool)              mRNW      <- mkReg(False);
  Reg#(Bit#(1))           mAbort    <- mkReg(0);
  Reg#(Bit#(1))           mBusLock  <- mkReg(0);
  Reg#(Bit#(1))           mCompress <- mkReg(0);
  Reg#(Bit#(1))           mGuarded  <- mkReg(0);
  Reg#(Bit#(1))           mLockErr  <- mkReg(0);
  Reg#(Bit#(2))           mMSize    <- mkReg(0);
  Reg#(Bit#(1))           mOrdered  <- mkReg(0);
  Reg#(Bit#(2))           mPriority <- mkReg(0);
  Reg#(Bool)              mRdBurst  <- mkReg(False);
  Reg#(Bool)              mRequest  <- mkReg(False);
  Reg#(Bit#(4))           mSize     <- mkReg(0);
  Reg#(Bit#(3))           mType     <- mkReg(0);
  Reg#(Bool)              mWrBurst  <- mkReg(False);
  Reg#(Bit#(64))          mWrDBus   <- mkReg(0);
 
 
  // State for running the golden test loop
  Reg#(Bit#(32))                   goldenElementCounter <- mkReg(0);
  Reg#(Bit#(64))                   totalTicks <- mkReg(0);
 
 
  rule latch(True);
    mABus     <= plb.mABus();     // Address Bus
    mBE       <= plb.mBE();       // Byte Enable
    mRNW      <= plb.mRNW() == 1;      // Read Not Write
    mAbort    <= plb.mAbort();    // Abort
    mBusLock  <= plb.mBusLock();  // Bus lock
    mCompress <= plb.mCompress(); // compressed transfer
    mGuarded  <= plb.mGuarded();  // guarded transfer
    mLockErr  <= plb.mLockErr();  // lock error
    mMSize    <= plb.mMSize();    // data bus width?
    mOrdered  <= plb.mOrdered();  // synchronize transfer
    mPriority <= plb.mPriority(); // priority
    mRdBurst  <= plb.mRdBurst() == 1;  // read burst
    mRequest  <= plb.mRequest() == 1;  // bus request
    mSize     <= plb.mSize();     // transfer size
    mType     <= plb.mType();     // transfer type (dma)
    mWrBurst  <= plb.mWrBurst() == 1;  // write burst
    mWrDBus   <= plb.mWrDBus();   // write data bus
  endrule
 
  rule doMagic(True);
    Bit#(1)  plb_mRst          = 0; // PLB reset
    Bit#(1)  plb_mAddrAck      = 0; // Addr Ack                      //*
    Bit#(1)  plb_mBusy         = 0; // Master Busy
    Bit#(1)  plb_mErr          = 0; // Slave Error
    Bit#(1)  plb_mRdBTerm      = 0; // Read burst terminate signal
    Bit#(1)  plb_mRdDAck       = 0; // Read data ack
    Bit#(64) plb_mRdDBus       = 64'hcafefeeddeadbeef; // Read data bus
    Bit#(3)  plb_mRdWdAddr     = 0; // Read word address
    Bit#(1)  plb_mRearbitrate  = 0; // Rearbitrate
    Bit#(1)  plb_mWrBTerm      = 0; // Write burst terminate
    Bit#(1)  plb_mWrDAck       = 0; // Write data ack                //*
    Bit#(1)  plb_mSSize        = 0; // Slave bus size
    Bit#(1)  plb_sMErr         = 0; // Slave error
    Bit#(1)  plb_sMBusy        = 0;
 
    //Terminating Previous Request
    //
    // Technically, it's "correct" for a burst of 1/2
    // We're ignoring this
 
    if(transferSize == 1 && doingRead) // penultimate read
      begin
        plb_mRdBTerm = 1; // Read burst terminate signal
      end
 
    if(transferSize == 1 && doingWrite)
      plb_mWrBTerm = 1;
 
 
    //Determine if there's a new request
 
    // new read if mReq + mRNW + we've at just terminated or aren't working
    Bool newRead = mRequest &&  mRNW && (!doingRead || (plb_mRdBTerm ==1));
    // new write if mReq + !mRNW + we've at hust terminated or aren't working
 
    Bool newWrite = mRequest && !mRNW && (!doingWrite || (plb_mWrBTerm ==1));
 
    ///////////////////////////////////////////////////////////////////
    //
    // Read access logic. One cycle Delay
    //
    ///////////////////////////////////////////////////////////////////
 
    //Get Request
    //Bool newRead   =  !doingRead  && mRequest &&  mRNW && !mWrBurst;
    //Bool newWrite  =  !doingWrite && mRequest && !mRNW && mWrBurst;
 
    plb_mAddrAck = pack(newRead || newWrite);
 
    plb_mWrDAck =  pack(newWrite || doingWrite);
 
 
    Bool error_wrBurst_dropped_early = (transferSize > 1) && doingWrite && !mWrBurst;
 
    if (error_wrBurst_dropped_early)
      $display("ERROR: wrBurst dropped early");
 
 
    if (newRead)
      transferSize <= mBE + 1;
    else if (newWrite)
      transferSize <= mBE +1;
    else if ((doingRead || doingWrite) && (transferSize > 0))
      transferSize <= transferSize - 1;
 
    if (newRead || newWrite)
      curAddr <= mABus;
    else
      curAddr <= curAddr + 4;
 
    if (doingWrite)
      begin
        let wAddr = newWrite ? mABus : curAddr;//(curAddr + 4);
        let wData = (wAddr[2] == 0) ? mWrDBus[63:32]:mWrDBus[31:0];
        case (wAddr[23:22])
          2'b00:  begin
                    debug(plbMasterDebug,$display("PLB: writing to matA %h",wAddr[21:2]));
                    debug(plbMasterDebug,$display("PLB: got %h expected %h",wData, ~matrixA.sub( wAddr[21:2])));
                    if(wData != ~matrixA.sub( wAddr[21:2]))
                      begin
                        $finish;
                      end
                    matrixA.upd(wAddr[21:2],wData);
                  end
          2'b01:  begin
                    debug(plbMasterDebug,$display("PLB: writing to matB %h",wAddr[21:2]));
                    $finish;
                  end
          2'b10:  begin
                    debug(plbMasterDebug,$display("PLB: writing to matC %h %h",wAddr[21:2],goldenElementCounter));
                    $finish;
                  end
 
          2'b11:  begin
                    debug(plbMasterDebug,$display("PLB: writing to scratch %h",wAddr[21:2]));
                    $finish;
                  end
        endcase
      end
 
    if(doingRead)
     case (curAddr[23:22])
       2'b00:  readValue <= Just({matrixA.sub({curAddr[21:3],1}),(matrixA.sub({curAddr[21:3],0}))});
       2'b01:  readValue <= Just({matrixB.sub({curAddr[21:3],1}),(matrixB.sub({curAddr[21:3],0}))});
       2'b10:  readValue <= Just({matrixC.sub({curAddr[21:3],1}),(matrixC.sub({curAddr[21:3],0}))});
       2'b11:  readValue <= Just({matrixC.sub({curAddr[21:3],1}),(matrixC.sub({curAddr[21:3],0}))});
     endcase
    else
      readValue <= Nothing;
 
    plb_mRdDBus = case(readValue) matches
                    tagged Nothing: return 64'hfeedcafedeadbeef;
                    tagged Just .x: return x;
                  endcase;
 
    plb_mRdDAck = isJust(readValue) ? 1 : 0;
 
    if (newRead)
      doingRead <= True;
    else if (transferSize == 1)
      doingRead <= False;
 
    if (newWrite)
      doingWrite <= True;
    else if (transferSize == 1)
      doingWrite <= False;
 
/*
    if(transferSize == 1 && (doingRead || newRead)) // penultimate read
      begin
        plb_mRdBTerm = 1; // Read burst terminate signal
      end
 
    if(transferSize == 1 && (doingWrite || newWrite))
      plb_mWrBTerm = 1;
*/
    //wrComp and rdComp don't exist?
 
    plb.plbIN(
      plb_mRst,
      plb_mAddrAck,
      plb_mBusy,
      plb_mErr,
      plb_mRdBTerm,
      plb_mRdDAck,
      plb_mRdDBus,
      plb_mRdWdAddr,
      plb_mRearbitrate,
      plb_mWrBTerm,
      plb_mWrDAck,
      plb_mSSize,
      plb_sMErr,
      plb_sMBusy
      );
 
  endrule
 
endmodule

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[/] [cryptosorter/] [trunk/] [memocodeDesignContest2008/] [xup/] [PLBMaster/] [PLBModel.bsv] - Blame information for rev 6

Line No.	Rev	Author	Line
1	3	kfleming	`/*`
2			`Copyright (c) 2007 MIT`
3
4			`Permission is hereby granted, free of charge, to any person`
5			`obtaining a copy of this software and associated documentation`
6			`files (the "Software"), to deal in the Software without`
7			`restriction, including without limitation the rights to use,`
8			`copy, modify, merge, publish, distribute, sublicense, and/or sell`
9			`copies of the Software, and to permit persons to whom the`
10			`Software is furnished to do so, subject to the following`
11			`conditions:`
12
13			`The above copyright notice and this permission notice shall be`
14			`included in all copies or substantial portions of the Software.`
15
16			`THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,`
17			`EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES`
18			`OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND`
19			`NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT`
20			`HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,`
21			`WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING`
22			`FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR`
23			`OTHER DEALINGS IN THE SOFTWARE.`
24
25			`Author: Kermin Fleming`
26			`*/`
27
28			`import Types::*;`
29			`import Parameters::*;`
30			`import Interfaces::*;`
31			`import DebugFlags::*;`
32			`import PLBMasterWires::*;`
33			`import RegFile::*;`
34
35			`module mkPLBModel#(PLBMasterWires plb) ();`
36
37			`RegFile#(Bit#(20), Bit#(32)) matrixA <- mkRegFileFullLoad("invert.hex");`
38			`RegFile#(Bit#(20), Bit#(32)) matrixB <- mkRegFileFull();`
39			`RegFile#(Bit#(20), Bit#(32)) matrixC <- mkRegFileFull();`
40			`RegFile#(Bit#(20), Bit#(32)) scratch <- mkRegFileFull();`
41
42			`Reg#(Bit#(PLBAddrSize)) curAddr <- mkReg(0);`
43			`Reg#(Bit#(8)) transferSize <- mkReg(0);`
44
45			`Reg#(Bit#(32)) wrValue <- mkReg(0);`
46
47			`Reg#(Bool) doingRead <- mkReg(False);`
48			`Reg#(Bool) doingWrite <- mkReg(False);`
49
50			`Reg#(Maybe#(Bit#(64))) readValue <- mkReg(Nothing);`
51
52			`Reg#(Bit#(PLBAddrSize)) mABus <- mkReg(0);`
53			`Reg#(Bit#(8)) mBE <- mkReg(0);`
54			`Reg#(Bool) mRNW <- mkReg(False);`
55			`Reg#(Bit#(1)) mAbort <- mkReg(0);`
56			`Reg#(Bit#(1)) mBusLock <- mkReg(0);`
57			`Reg#(Bit#(1)) mCompress <- mkReg(0);`
58			`Reg#(Bit#(1)) mGuarded <- mkReg(0);`
59			`Reg#(Bit#(1)) mLockErr <- mkReg(0);`
60			`Reg#(Bit#(2)) mMSize <- mkReg(0);`
61			`Reg#(Bit#(1)) mOrdered <- mkReg(0);`
62			`Reg#(Bit#(2)) mPriority <- mkReg(0);`
63			`Reg#(Bool) mRdBurst <- mkReg(False);`
64			`Reg#(Bool) mRequest <- mkReg(False);`
65			`Reg#(Bit#(4)) mSize <- mkReg(0);`
66			`Reg#(Bit#(3)) mType <- mkReg(0);`
67			`Reg#(Bool) mWrBurst <- mkReg(False);`
68			`Reg#(Bit#(64)) mWrDBus <- mkReg(0);`
69
70
71			`// State for running the golden test loop`
72			`Reg#(Bit#(32)) goldenElementCounter <- mkReg(0);`
73			`Reg#(Bit#(64)) totalTicks <- mkReg(0);`
74
75
76			`rule latch(True);`
77			`mABus <= plb.mABus(); // Address Bus`
78			`mBE <= plb.mBE(); // Byte Enable`
79			`mRNW <= plb.mRNW() == 1; // Read Not Write`
80			`mAbort <= plb.mAbort(); // Abort`
81			`mBusLock <= plb.mBusLock(); // Bus lock`
82			`mCompress <= plb.mCompress(); // compressed transfer`
83			`mGuarded <= plb.mGuarded(); // guarded transfer`
84			`mLockErr <= plb.mLockErr(); // lock error`
85			`mMSize <= plb.mMSize(); // data bus width?`
86			`mOrdered <= plb.mOrdered(); // synchronize transfer`
87			`mPriority <= plb.mPriority(); // priority`
88			`mRdBurst <= plb.mRdBurst() == 1; // read burst`
89			`mRequest <= plb.mRequest() == 1; // bus request`
90			`mSize <= plb.mSize(); // transfer size`
91			`mType <= plb.mType(); // transfer type (dma)`
92			`mWrBurst <= plb.mWrBurst() == 1; // write burst`
93			`mWrDBus <= plb.mWrDBus(); // write data bus`
94			`endrule`
95
96			`rule doMagic(True);`
97			`Bit#(1) plb_mRst = 0; // PLB reset`
98			`Bit#(1) plb_mAddrAck = 0; // Addr Ack //*`
99			`Bit#(1) plb_mBusy = 0; // Master Busy`
100			`Bit#(1) plb_mErr = 0; // Slave Error`
101			`Bit#(1) plb_mRdBTerm = 0; // Read burst terminate signal`
102			`Bit#(1) plb_mRdDAck = 0; // Read data ack`
103			`Bit#(64) plb_mRdDBus = 64'hcafefeeddeadbeef; // Read data bus`
104			`Bit#(3) plb_mRdWdAddr = 0; // Read word address`
105			`Bit#(1) plb_mRearbitrate = 0; // Rearbitrate`
106			`Bit#(1) plb_mWrBTerm = 0; // Write burst terminate`
107			`Bit#(1) plb_mWrDAck = 0; // Write data ack //*`
108			`Bit#(1) plb_mSSize = 0; // Slave bus size`
109			`Bit#(1) plb_sMErr = 0; // Slave error`
110			`Bit#(1) plb_sMBusy = 0;`
111
112			`//Terminating Previous Request`
113			`//`
114			`// Technically, it's "correct" for a burst of 1/2`
115			`// We're ignoring this`
116
117			`if(transferSize == 1 && doingRead) // penultimate read`
118			`begin`
119			`plb_mRdBTerm = 1; // Read burst terminate signal`
120			`end`
121
122			`if(transferSize == 1 && doingWrite)`
123			`plb_mWrBTerm = 1;`
124
125
126			`//Determine if there's a new request`
127
128			`// new read if mReq + mRNW + we've at just terminated or aren't working`
129			`Bool newRead = mRequest && mRNW && (!doingRead \|\| (plb_mRdBTerm ==1));`
130			`// new write if mReq + !mRNW + we've at hust terminated or aren't working`
131
132			`Bool newWrite = mRequest && !mRNW && (!doingWrite \|\| (plb_mWrBTerm ==1));`
133
134			`///////////////////////////////////////////////////////////////////`
135			`//`
136			`// Read access logic. One cycle Delay`
137			`//`
138			`///////////////////////////////////////////////////////////////////`
139
140			`//Get Request`
141			`//Bool newRead = !doingRead && mRequest && mRNW && !mWrBurst;`
142			`//Bool newWrite = !doingWrite && mRequest && !mRNW && mWrBurst;`
143
144			`plb_mAddrAck = pack(newRead \|\| newWrite);`
145
146			`plb_mWrDAck = pack(newWrite \|\| doingWrite);`
147
148
149			`Bool error_wrBurst_dropped_early = (transferSize > 1) && doingWrite && !mWrBurst;`
150
151			`if (error_wrBurst_dropped_early)`
152			`$display("ERROR: wrBurst dropped early");`
153
154
155			`if (newRead)`
156			`transferSize <= mBE + 1;`
157			`else if (newWrite)`
158			`transferSize <= mBE +1;`
159			`else if ((doingRead \|\| doingWrite) && (transferSize > 0))`
160			`transferSize <= transferSize - 1;`
161
162			`if (newRead \|\| newWrite)`
163			`curAddr <= mABus;`
164			`else`
165			`curAddr <= curAddr + 4;`
166
167			`if (doingWrite)`
168			`begin`
169			`let wAddr = newWrite ? mABus : curAddr;//(curAddr + 4);`
170			`let wData = (wAddr[2] == 0) ? mWrDBus[63:32]:mWrDBus[31:0];`
171			`case (wAddr[23:22])`
172			`2'b00: begin`
173			`debug(plbMasterDebug,$display("PLB: writing to matA %h",wAddr[21:2]));`
174			`debug(plbMasterDebug,$display("PLB: got %h expected %h",wData, ~matrixA.sub( wAddr[21:2])));`
175			`if(wData != ~matrixA.sub( wAddr[21:2]))`
176			`begin`
177			`$finish;`
178			`end`
179			`matrixA.upd(wAddr[21:2],wData);`
180			`end`
181			`2'b01: begin`
182			`debug(plbMasterDebug,$display("PLB: writing to matB %h",wAddr[21:2]));`
183			`$finish;`
184			`end`
185			`2'b10: begin`
186			`debug(plbMasterDebug,$display("PLB: writing to matC %h %h",wAddr[21:2],goldenElementCounter));`
187			`$finish;`
188			`end`
189
190			`2'b11: begin`
191			`debug(plbMasterDebug,$display("PLB: writing to scratch %h",wAddr[21:2]));`
192			`$finish;`
193			`end`
194			`endcase`
195			`end`
196
197			`if(doingRead)`
198			`case (curAddr[23:22])`
199			`2'b00: readValue <= Just({matrixA.sub({curAddr[21:3],1}),(matrixA.sub({curAddr[21:3],0}))});`
200			`2'b01: readValue <= Just({matrixB.sub({curAddr[21:3],1}),(matrixB.sub({curAddr[21:3],0}))});`
201			`2'b10: readValue <= Just({matrixC.sub({curAddr[21:3],1}),(matrixC.sub({curAddr[21:3],0}))});`
202			`2'b11: readValue <= Just({matrixC.sub({curAddr[21:3],1}),(matrixC.sub({curAddr[21:3],0}))});`
203			`endcase`
204			`else`
205			`readValue <= Nothing;`
206
207			`plb_mRdDBus = case(readValue) matches`
208			`tagged Nothing: return 64'hfeedcafedeadbeef;`
209			`tagged Just .x: return x;`
210			`endcase;`
211
212			`plb_mRdDAck = isJust(readValue) ? 1 : 0;`
213
214			`if (newRead)`
215			`doingRead <= True;`
216			`else if (transferSize == 1)`
217			`doingRead <= False;`
218
219			`if (newWrite)`
220			`doingWrite <= True;`
221			`else if (transferSize == 1)`
222			`doingWrite <= False;`
223
224			`/*`
225			`if(transferSize == 1 && (doingRead \|\| newRead)) // penultimate read`
226			`begin`
227			`plb_mRdBTerm = 1; // Read burst terminate signal`
228			`end`
229
230			`if(transferSize == 1 && (doingWrite \|\| newWrite))`
231			`plb_mWrBTerm = 1;`
232			`*/`
233			`//wrComp and rdComp don't exist?`
234
235			`plb.plbIN(`
236			`plb_mRst,`
237			`plb_mAddrAck,`
238			`plb_mBusy,`
239			`plb_mErr,`
240			`plb_mRdBTerm,`
241			`plb_mRdDAck,`
242			`plb_mRdDBus,`
243			`plb_mRdWdAddr,`
244			`plb_mRearbitrate,`
245			`plb_mWrBTerm,`
246			`plb_mWrDAck,`
247			`plb_mSSize,`
248			`plb_sMErr,`
249			`plb_sMBusy`
250			`);`
251
252			`endrule`
253
254			`endmodule`