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kfleming |
/*
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Copyright (c) 2007 MIT
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Permission is hereby granted, free of charge, to any person
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obtaining a copy of this software and associated documentation
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files (the "Software"), to deal in the Software without
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restriction, including without limitation the rights to use,
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copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following
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conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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OTHER DEALINGS IN THE SOFTWARE.
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Author: Nirav Dave
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*/
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module sorttester(CLK,
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RST,
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plbMasterWires_mABus,
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plbMasterWires_mBE,
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plbMasterWires_mRNW,
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plbMasterWires_mAbort,
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plbMasterWires_mBusLock,
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plbMasterWires_mCompress,
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plbMasterWires_mGuarded,
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plbMasterWires_mLockErr,
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plbMasterWires_mMSize,
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plbMasterWires_mOrdered,
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plbMasterWires_mPriority,
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plbMasterWires_mRdBurst,
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plbMasterWires_mRequest,
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plbMasterWires_mSize,
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plbMasterWires_mType,
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plbMasterWires_mWrBurst,
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plbMasterWires_mWrDBus,
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plbMasterWires_mRst,
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plbMasterWires_mAddrAck,
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plbMasterWires_mBusy,
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plbMasterWires_mErr,
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plbMasterWires_mRdBTerm,
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plbMasterWires_mRdDAck,
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plbMasterWires_mRdDBus,
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plbMasterWires_mRdWdAddr,
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plbMasterWires_mRearbitrate,
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plbMasterWires_mWrBTerm,
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plbMasterWires_mWrDAck,
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plbMasterWires_mSSize,
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plbMasterWires_sMErr,
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plbMasterWires_sMBusy,
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bramInitiatorWires_bramRST,
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bramInitiatorWires_bramAddr,
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bramInitiatorWires_bramDout,
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bramInitiatorWires_bramWEN,
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bramInitiatorWires_bramEN,
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bramInitiatorWires_bramCLK,
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bramInitiatorWires_bramDin);
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input CLK;
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input RST;
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// value method plbMasterWires_mABus
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output [31 : 0] plbMasterWires_mABus;
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// value method plbMasterWires_mBE
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output [7 : 0] plbMasterWires_mBE;
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// value method plbMasterWires_mRNW
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output plbMasterWires_mRNW;
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// value method plbMasterWires_mAbort
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output plbMasterWires_mAbort;
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// value method plbMasterWires_mBusLock
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output plbMasterWires_mBusLock;
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// value method plbMasterWires_mCompress
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output plbMasterWires_mCompress;
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// value method plbMasterWires_mGuarded
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output plbMasterWires_mGuarded;
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// value method plbMasterWires_mLockErr
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output plbMasterWires_mLockErr;
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// value method plbMasterWires_mMSize
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output [1 : 0] plbMasterWires_mMSize;
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// value method plbMasterWires_mOrdered
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output plbMasterWires_mOrdered;
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// value method plbMasterWires_mPriority
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output [1 : 0] plbMasterWires_mPriority;
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// value method plbMasterWires_mRdBurst
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output plbMasterWires_mRdBurst;
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// value method plbMasterWires_mRequest
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output plbMasterWires_mRequest;
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// value method plbMasterWires_mSize
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output [3 : 0] plbMasterWires_mSize;
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// value method plbMasterWires_mType
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output [2 : 0] plbMasterWires_mType;
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// value method plbMasterWires_mWrBurst
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output plbMasterWires_mWrBurst;
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// value method plbMasterWires_mWrDBus
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output [63 : 0] plbMasterWires_mWrDBus;
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// action method plbMasterWires_plbIN
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input plbMasterWires_mRst;
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input plbMasterWires_mAddrAck;
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input plbMasterWires_mBusy;
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input plbMasterWires_mErr;
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input plbMasterWires_mRdBTerm;
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input plbMasterWires_mRdDAck;
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input [63 : 0] plbMasterWires_mRdDBus;
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input [2 : 0] plbMasterWires_mRdWdAddr;
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input plbMasterWires_mRearbitrate;
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input plbMasterWires_mWrBTerm;
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input plbMasterWires_mWrDAck;
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input plbMasterWires_mSSize;
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input plbMasterWires_sMErr;
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input plbMasterWires_sMBusy;
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// action method bramTargetWires_bramIN
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output [31 : 0] bramInitiatorWires_bramAddr;
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output [31 : 0] bramInitiatorWires_bramDout;
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output [3 : 0] bramInitiatorWires_bramWEN;
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output bramInitiatorWires_bramEN;
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output bramInitiatorWires_bramCLK;
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output bramInitiatorWires_bramRST;
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// value method bramTargetWires_bramOUT
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input [31 : 0] bramInitiatorWires_bramDin;
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wire [13:0] bramInitiatorWires_bramAddr_our;
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assign bramInitiatorWires_bramAddr = {16'h00000,bramInitiatorWires_bramAddr_our, 2'b00};
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// signals for module outputs
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wire [31 : 0] bramTargetWires_dinBRAM,plbMasterWires_mABus;
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wire [63 : 0] plbMasterWires_mWrDBus;
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wire [7 : 0] plbMasterWires_mBE;
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wire [3 : 0] plbMasterWires_mSize;
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wire [2 : 0] plbMasterWires_mType;
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wire [1 : 0] plbMasterWires_mMSize, plbMasterWires_mPriority;
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wire plbMasterWires_mAbort,
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plbMasterWires_mBusLock,
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plbMasterWires_mCompress,
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plbMasterWires_mGuarded,
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plbMasterWires_mLockErr,
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plbMasterWires_mOrdered,
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plbMasterWires_mRNW,
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plbMasterWires_mRdBurst,
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plbMasterWires_mRequest,
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plbMasterWires_mWrBurst;
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wire RST_N;
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assign RST_N = ~RST;
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mkSortTester m(
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.CLK(CLK),
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.RST_N(RST_N),
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.plbMasterWires_mABus(plbMasterWires_mABus),
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.plbMasterWires_mBE(plbMasterWires_mBE),
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.plbMasterWires_mRNW(plbMasterWires_mRNW),
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.plbMasterWires_mAbort(plbMasterWires_mAbort),
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.plbMasterWires_mBusLock(plbMasterWires_mBusLock),
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.plbMasterWires_mCompress(plbMasterWires_mCompress),
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.plbMasterWires_mGuarded(plbMasterWires_mGuarded),
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.plbMasterWires_mLockErr(plbMasterWires_mLockErr),
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.plbMasterWires_mMSize(plbMasterWires_mMSize),
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.plbMasterWires_mOrdered(plbMasterWires_mOrdered),
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.plbMasterWires_mPriority(plbMasterWires_mPriority),
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.plbMasterWires_mRdBurst(plbMasterWires_mRdBurst),
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.plbMasterWires_mRequest(plbMasterWires_mRequest),
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.plbMasterWires_mSize(plbMasterWires_mSize),
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.plbMasterWires_mType(plbMasterWires_mType),
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.plbMasterWires_mWrBurst(plbMasterWires_mWrBurst),
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.plbMasterWires_mWrDBus(plbMasterWires_mWrDBus),
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.plbMasterWires_mRst(plbMasterWires_mRst),
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.plbMasterWires_mAddrAck(plbMasterWires_mAddrAck),
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.plbMasterWires_mBusy(plbMasterWires_mBusy),
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.plbMasterWires_mErr(plbMasterWires_mErr),
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.plbMasterWires_mRdBTerm(plbMasterWires_mRdBTerm),
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.plbMasterWires_mRdDAck(plbMasterWires_mRdDAck),
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.plbMasterWires_mRdDBus(plbMasterWires_mRdDBus),
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.plbMasterWires_mRdWdAddr(plbMasterWires_mRdWdAddr),
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.plbMasterWires_mRearbitrate(plbMasterWires_mRearbitrate),
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.plbMasterWires_mWrBTerm(plbMasterWires_mWrBTerm),
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.plbMasterWires_mWrDAck(plbMasterWires_mWrDAck),
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.plbMasterWires_mSSize(plbMasterWires_mSSize),
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.plbMasterWires_sMErr(plbMasterWires_sMErr),
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.plbMasterWires_sMBusy(plbMasterWires_sMBusy),
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.bramInitiatorWires_bramAddr(bramInitiatorWires_bramAddr_our),
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.bramInitiatorWires_bramDout(bramInitiatorWires_bramDout),
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.bramInitiatorWires_bramWEN(bramInitiatorWires_bramWEN),
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.bramInitiatorWires_bramEN(bramInitiatorWires_bramEN),
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.bramInitiatorWires_bramCLK(bramInitiatorWires_bramCLK),
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.bramInitiatorWires_bramRST(bramInitiatorWires_bramRST),
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.bramInitiatorWires_din(bramInitiatorWires_bramDin)
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);
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endmodule
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