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[/] [csa/] [trunk/] [bench/] [makefile] - Blame information for rev 27

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PROJ_NAME ?= key_schedule
DEBUG     ?= y
 
MODELSIM_DIR=/opt/modeltech
 
ifeq ($(DEBUG),y)
CFLAGS=-DDEBUG
else
CFLAGS=
endif
 
all:csa_pli.vpi $(PROJ_NAME).vvp csa_pli_modelsim
 
csa_pli.vpi:csa_pli.c
        iverilog-vpi $(CFLAGS) --name=csa_pli  $^ >/dev/null
        rm -fr csa_pli.o
 
csa_pli_modelsim:csa_pli.sl
 
%.sl:%.o
        ld -shared -E -o $@ $^
        rm -fr csa_pli.o
 
%.o:%.c
        gcc -c -g -I$(MODELSIM_DIR)/include $^
 
 
%.vvp:%_tb.v ../rtl/%.v
        iverilog $(CFLAGS) -tvvp -o$@ $^
 
test:csa_pli.vpi $(PROJ_NAME).vvp
        vvp -M. -mcsa_pli $(PROJ_NAME).vvp
 
clean:
        rm -fr *.o *.vvp *.vpi *.log *.key *.sl
 
key_schedule.vvp:key_schedule_tb.v ../rtl/key_schedule.v ../rtl/key_perm.v
 
block_decypher.vvp:block_decypher_tb.v ../rtl/block_decypher.v ../rtl/block_perm.v ../rtl/block_sbox.v
 
decrypt.vvp:decrypt_tb.v                             \
                        ../rtl/decrypt.v             \
                        ../rtl/key_schedule.v        \
                        ../rtl/block_perm.v          \
                        ../rtl/key_perm.v            \
                        ../rtl/stream_cypher.v       \
                        ../rtl/sbox1.v               \
                        ../rtl/sbox2.v               \
                        ../rtl/sbox3.v               \
                        ../rtl/sbox4.v               \
                        ../rtl/sbox5.v               \
                        ../rtl/sbox6.v               \
                        ../rtl/sbox7.v               \
                        ../rtl/sboxes.v              \
                        ../rtl/stream_iteration.v    \
                        ../rtl/stream_byte.v         \
                        ../rtl/stream_8bytes.v       \
                        ../rtl/block_sbox.v  \
                        ../rtl/block_decypher.v
 
stream_cypher.vvp:stream_cypher_tb.v                 \
                        ../rtl/stream_cypher.v       \
                        ../rtl/sbox1.v               \
                        ../rtl/sbox2.v               \
                        ../rtl/sbox3.v               \
                        ../rtl/sbox4.v               \
                        ../rtl/sbox5.v               \
                        ../rtl/sbox6.v               \
                        ../rtl/sbox7.v               \
                        ../rtl/sboxes.v              \
                        ../rtl/stream_iteration.v    \
                        ../rtl/stream_byte.v         \
                        ../rtl/stream_8bytes.v
 
veriwell_test:
        veriwell key_schedule_tb.v ../rtl/key_schedule.v ../rtl/key_perm.v

Line No.	Rev	Author	Line
1	9	simon111
2	23	simon111	`PROJ_NAME ?= key_schedule`
3	15	simon111	`DEBUG ?= y`
4	9	simon111
5	20	simon111	`MODELSIM_DIR=/opt/modeltech`
6
7	15	simon111	`ifeq ($(DEBUG),y)`
8			`CFLAGS=-DDEBUG`
9			`else`
10			`CFLAGS=`
11			`endif`
12	9	simon111
13	20	simon111	`all:csa_pli.vpi $(PROJ_NAME).vvp csa_pli_modelsim`
14	15	simon111
15	12	simon111	`csa_pli.vpi:csa_pli.c`
16	15	simon111	`iverilog-vpi $(CFLAGS) --name=csa_pli $^ >/dev/null`
17	20	simon111	`rm -fr csa_pli.o`
18	12	simon111
19	20	simon111	`csa_pli_modelsim:csa_pli.sl`
20
21			`%.sl:%.o`
22			`ld -shared -E -o $@ $^`
23			`rm -fr csa_pli.o`
24
25			`%.o:%.c`
26			`gcc -c -g -I$(MODELSIM_DIR)/include $^`
27
28
29	9	simon111	`%.vvp:%_tb.v ../rtl/%.v`
30	15	simon111	`iverilog $(CFLAGS) -tvvp -o$@ $^`
31	9	simon111
32	12	simon111	`test:csa_pli.vpi $(PROJ_NAME).vvp`
33			`vvp -M. -mcsa_pli $(PROJ_NAME).vvp`
34	9	simon111
35			`clean:`
36	20	simon111	`rm -fr .o .vvp .vpi .log .key .sl`
37	9	simon111
38	12	simon111	`key_schedule.vvp:key_schedule_tb.v ../rtl/key_schedule.v ../rtl/key_perm.v`
39
40	17	simon111	`block_decypher.vvp:block_decypher_tb.v ../rtl/block_decypher.v ../rtl/block_perm.v ../rtl/block_sbox.v`
41	18	simon111
42	22	simon111	`decrypt.vvp:decrypt_tb.v \`
43			`../rtl/decrypt.v \`
44			`../rtl/key_schedule.v \`
45			`../rtl/block_perm.v \`
46			`../rtl/key_perm.v \`
47			`../rtl/stream_cypher.v \`
48			`../rtl/sbox1.v \`
49			`../rtl/sbox2.v \`
50			`../rtl/sbox3.v \`
51			`../rtl/sbox4.v \`
52			`../rtl/sbox5.v \`
53			`../rtl/sbox6.v \`
54			`../rtl/sbox7.v \`
55			`../rtl/sboxes.v \`
56			`../rtl/stream_iteration.v \`
57			`../rtl/stream_byte.v \`
58	23	simon111	`../rtl/stream_8bytes.v \`
59			`../rtl/block_sbox.v \`
60			`../rtl/block_decypher.v`
61	20	simon111
62			`stream_cypher.vvp:stream_cypher_tb.v \`
63			`../rtl/stream_cypher.v \`
64			`../rtl/sbox1.v \`
65			`../rtl/sbox2.v \`
66			`../rtl/sbox3.v \`
67			`../rtl/sbox4.v \`
68			`../rtl/sbox5.v \`
69			`../rtl/sbox6.v \`
70			`../rtl/sbox7.v \`
71			`../rtl/sboxes.v \`
72			`../rtl/stream_iteration.v \`
73			`../rtl/stream_byte.v \`
74			`../rtl/stream_8bytes.v`
75	23	simon111
76			`veriwell_test:`
77			`veriwell key_schedule_tb.v ../rtl/key_schedule.v ../rtl/key_perm.v`

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[/] [csa/] [trunk/] [bench/] [makefile] - Blame information for rev 27