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simon111 |
# Copyright (C) 1991-2008 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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# The default values for assignments are stored in the file
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# csa_assignment_defaults.qdf
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# If this file doesn't exist, and for assignments not listed, see file
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# assignment_defaults.qdf
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# Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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set_global_assignment -name FAMILY Cyclone
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set_global_assignment -name DEVICE EP1C6Q240C8
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set_global_assignment -name TOP_LEVEL_ENTITY csa_fpga
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:03:51 APRIL 15, 2009"
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set_global_assignment -name LAST_QUARTUS_VERSION 8.1
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set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name LL_ROOT_REGION ON -entity csa -section_id "Root Region"
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set_global_assignment -name LL_MEMBER_STATE LOCKED -entity csa -section_id "Root Region"
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set_global_assignment -name VERILOG_FILE ../rtl/sbox1.v
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set_global_assignment -name VERILOG_FILE ../rtl/sbox2.v
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set_global_assignment -name VERILOG_FILE ../rtl/sbox3.v
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set_global_assignment -name VERILOG_FILE ../rtl/sbox4.v
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set_global_assignment -name VERILOG_FILE ../rtl/sbox5.v
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set_global_assignment -name VERILOG_FILE ../rtl/sbox6.v
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set_global_assignment -name VERILOG_FILE ../rtl/sbox7.v
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set_global_assignment -name VERILOG_FILE ../rtl/sboxes.v
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set_global_assignment -name VERILOG_FILE ../rtl/stream_iteration.v
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set_global_assignment -name VERILOG_FILE ../rtl/stream_byte.v
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set_global_assignment -name VERILOG_FILE ../rtl/stream_8bytes.v
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set_global_assignment -name VERILOG_FILE ../rtl/key_perm.v
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set_global_assignment -name VERILOG_FILE ../rtl/block_perm.v
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set_global_assignment -name VERILOG_FILE ../rtl/block_sbox.v
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set_global_assignment -name VERILOG_FILE ../rtl/stream_cypher.v
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set_global_assignment -name VERILOG_FILE ../rtl/key_schedule.v
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set_global_assignment -name VERILOG_FILE ../rtl/block_decypher.v
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set_global_assignment -name VERILOG_FILE ../rtl/decrypt.v
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set_global_assignment -name VERILOG_FILE csa_fpga.v
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