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[/] [csa/] [trunk/] [quartus10/] [csa_fpga.v] - Blame information for rev 37

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// this file is the test circuit
// author: Simom Panti
//
 
 
module csa_fpga(
                          output              bell
                        , input               clk
                        , input               rst
                        , input               flaga
                        , input               flagb
                        , input               flagc
                        , output              slcs
                        , output              pktend
                        , output reg          sloe
                        , output reg          slwr
                        , output reg          slrd
                        , output reg [ 1:0]   fifoadr
                        , inout      [15:0]   fd
                        , input               ifclk
                        , output     [ 7:0]   led
                        , output     [ 3:0]   ledseg
                        , output     [ 7:0]   seg_d
             );
 
 
        wire usbclk = ifclk;
        wire ep6_havedata = flaga;
        wire ep2_haveroom = flagc;
        wire ep8_havedata = flagb;
 
        assign bell = 1'h1;
 
`define CNT_WIDTH 25
`define STA_WIDTH 4
 
        ////////////////////////////////////////////////////////////////////////////////
        // led segement control
        ////////////////////////////////////////////////////////////////////////////////
 
        ledseg_cnt ledseg_cnt(
                         .clk      (usbclk)
                       , .rst      (rst)
                       , .data     (usb_dat_in)
                       , .seg      (ledseg)
                       , .segd     (seg_d)
                        );
 
        ////////////////////////////////////////////////////////////////////////////////
        // usb interface
        ////////////////////////////////////////////////////////////////////////////////
        assign slcs  =1'h0;
        assign pktend=1'h1;
 
`define EP2_W  2'h0
`define EP6_R  2'h1
`define EP8_R  2'h2
`define NO_ACT 2'h3
 
        reg [ 1:0] last_action;
        reg [15:0] usb_dat_out;
        reg [15:0] usb_dat_in;
 
        always @(posedge usbclk)
                if(ep6_havedata)
                begin
                        sloe<=1'h0;
                        fifoadr<=2'h2;
                        slrd<=1'h0;
                        slwr<=1'h1;
                        last_action<=`EP6_R;
                end
                else
                if(ep8_havedata)
                begin
                        sloe<=1'h0;
                        fifoadr<=2'h3;
                        slrd<=1'h0;
                        slwr<=1'h1;
                        last_action<=`EP8_R;
                end
                else
                if(ep2_haveroom)
                begin
                        // ouput data
                        sloe<=1'h1;
                        fifoadr<=2'h0;
                        slwr<=1'h0;
                        slrd<=1'h1;
                        last_action<=`EP2_W;
 
                end
                else
                begin
                        sloe<=1'h1;
                        fifoadr<=2'h0;
                        slwr<=1'h1;
                        slrd<=1'h1;
                        last_action<=`NO_ACT;
                end
 
        always @(posedge usbclk)
                if(last_action==`EP8_R )
                        usb_dat_in<=fd;
 
        assign fd=(sloe)?usb_dat_out:16'hzzzz;
 
        ////////////////////////////////////////////////////////////////////////////////
        // csa decrypt module
        ////////////////////////////////////////////////////////////////////////////////
        decrypt csa_decrypt(
                                 . clk            (usbclk)
                                ,. rst            (rst)
                                ,. ck             (64'h0000000000000000)
                                ,. key_en         (1'h0)
                                ,. even_odd       (1'h0)
                                ,. en             ()
                                ,. encrypted      ()
                                ,. decrypted      ()
                                ,. invalid        ()
                    );
 
 
endmodule
 

Line No.	Rev	Author	Line
1	28	simon111
2
3			`// this file is the test circuit`
4			`// author: Simom Panti`
5			`//`
6
7
8			`module csa_fpga(`
9			`output bell`
10			`, input clk`
11			`, input rst`
12			`, input flaga`
13			`, input flagb`
14			`, input flagc`
15			`, output slcs`
16			`, output pktend`
17			`, output reg sloe`
18			`, output reg slwr`
19			`, output reg slrd`
20			`, output reg [ 1:0] fifoadr`
21			`, inout [15:0] fd`
22			`, input ifclk`
23			`, output [ 7:0] led`
24			`, output [ 3:0] ledseg`
25			`, output [ 7:0] seg_d`
26			`);`
27
28
29			`wire usbclk = ifclk;`
30			`wire ep6_havedata = flaga;`
31			`wire ep2_haveroom = flagc;`
32	30	simon111	`wire ep8_havedata = flagb;`
33	28	simon111
34			`assign bell = 1'h1;`
35
36			`define CNT_WIDTH 25
37			`define STA_WIDTH 4
38
39			`////////////////////////////////////////////////////////////////////////////////`
40	33	simon111	`// led segement control`
41	28	simon111	`////////////////////////////////////////////////////////////////////////////////`
42
43	33	simon111	`ledseg_cnt ledseg_cnt(`
44	28	simon111	`.clk (usbclk)`
45			`, .rst (rst)`
46	30	simon111	`, .data (usb_dat_in)`
47	28	simon111	`, .seg (ledseg)`
48			`, .segd (seg_d)`
49			`);`
50
51			`////////////////////////////////////////////////////////////////////////////////`
52			`// usb interface`
53			`////////////////////////////////////////////////////////////////////////////////`
54	30	simon111	`assign slcs =1'h0;`
55			`assign pktend=1'h1;`
56	28	simon111
57	30	simon111	`define EP2_W 2'h0
58			`define EP6_R 2'h1
59			`define EP8_R 2'h2
60			`define NO_ACT 2'h3
61	28	simon111
62	30	simon111	`reg [ 1:0] last_action;`
63			`reg [15:0] usb_dat_out;`
64			`reg [15:0] usb_dat_in;`
65	28	simon111
66	30	simon111	`always @(posedge usbclk)`
67			`if(ep6_havedata)`
68			`begin`
69			`sloe<=1'h0;`
70			`fifoadr<=2'h2;`
71			`slrd<=1'h0;`
72			`slwr<=1'h1;`
73			last_action<=`EP6_R;
74			`end`
75			`else`
76			`if(ep8_havedata)`
77			`begin`
78			`sloe<=1'h0;`
79			`fifoadr<=2'h3;`
80			`slrd<=1'h0;`
81			`slwr<=1'h1;`
82			last_action<=`EP8_R;
83			`end`
84			`else`
85			`if(ep2_haveroom)`
86			`begin`
87			`// ouput data`
88			`sloe<=1'h1;`
89			`fifoadr<=2'h0;`
90			`slwr<=1'h0;`
91			`slrd<=1'h1;`
92			last_action<=`EP2_W;
93
94			`end`
95			`else`
96			`begin`
97			`sloe<=1'h1;`
98			`fifoadr<=2'h0;`
99			`slwr<=1'h1;`
100			`slrd<=1'h1;`
101			last_action<=`NO_ACT;
102			`end`
103
104			`always @(posedge usbclk)`
105			if(last_action==`EP8_R )
106			`usb_dat_in<=fd;`
107
108			`assign fd=(sloe)?usb_dat_out:16'hzzzz;`
109
110	28	simon111	`////////////////////////////////////////////////////////////////////////////////`
111			`// csa decrypt module`
112			`////////////////////////////////////////////////////////////////////////////////`
113			`decrypt csa_decrypt(`
114	30	simon111	`. clk (usbclk)`
115	28	simon111	`,. rst (rst)`
116			`,. ck (64'h0000000000000000)`
117			`,. key_en (1'h0)`
118			`,. even_odd (1'h0)`
119			`,. en ()`
120			`,. encrypted ()`
121			`,. decrypted ()`
122			`,. invalid ()`
123			`);`
124
125
126			`endmodule`
127

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[/] [csa/] [trunk/] [quartus10/] [csa_fpga.v] - Blame information for rev 37