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[/] [csa/] [trunk/] [quartus10/] [usb_cnt.v] - Blame information for rev 39

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// the usb controler module
 
// now this control support 3 endpoint
// ep2, output data
// ep6, input data
// ep8, input data
 
module usb_cnt  (
                         input               clk
                       , output              pktend  // 
                       , output  reg         sloe    // output enable , high active
                       , output  reg         slwr    // fifo write signal, low active
                       , output              slcs    // fifo chip select, low active
                       , output  reg         slrd    // fifo read , low active
                       , output  reg  [ 1:0] fifoadr // fifo address, 00-ep2 01 -- ep4 10--ep6 11--pe8
                       , inout        [15:0] fd      // data bus
                    // endpoint data ports
                    // ep2
                       , input               ep2_t    // ep2 full flag, low active
                       , output              ep2_busy // ep2 busy, high active
                       , input               ep2_wr   // ep2 write signal
                       , input        [15:0] ep2_data
                    // ep6
                       , input               ep6_t   // ep6 empty flag, low active
                       , output              ep6_f   // ep6 have data coming
                       , output       [15:0] ep6_data
                    // ep8
                       , input               ep8_t   // ep8 empty flag, low active
                       , output              ep8_f   // ep8 have data coming
                       , output       [15:0] ep8_data
                );
 
`define EP2_W  2'h3
`define EP6_R  2'h2
`define EP8_R  2'h1
`define NO_ACT 2'h0
 
                reg [1:0] last_action;      // the active in lost clck
 
                reg [15:0] usb_dat_in;      // the data coming from fd
                reg [15:0] usb_dat_out;     // the data upgoing to fd
                reg        oe;
 
                assign pktend = 1'h1;
                assign slcs   =1'h0;
 
                always @(posedge clk)
                        if(ep2_t&ep2_wr)
                        begin
                                sloe <= 1'h0;
                                oe <= 1'h1;
                                slrd<=1'h1;
                                slwr<=1'h0;
                                last_action<=`EP2_W;
                                fifoadr<=2'h0;
                        end
                        else if(ep6_t)
                        begin
                                sloe <= 1'h0;
                                oe <= 1'h0;
                                slrd<=1'h0;
                                slwr<=1'h1;
                                last_action<=`EP6_R;
                                fifoadr<=2'h2;
                        end
                        else if(ep8_t)
                        begin
                                sloe <= 1'h0;
                                oe <= 1'h0;
                                slrd<=1'h0;
                                slwr<=1'h1;
                                last_action<=`EP8_R;
                                fifoadr<=2'h3;
                        end
                        else
                        begin
                                sloe <= 1'h1;
                                oe <= 1'h1;
                                slrd<=1'h1;
                                slwr<=1'h1;
                                last_action<=`NO_ACT;
                                fifoadr<=2'h0;
                        end
 
                assign ep6_data=fd;
                assign ep6_f=last_action==`EP6_R;
                assign ep8_data=fd;
                assign ep8_f=last_action==`EP8_R;
                assign fd=(oe)?ep2_data:16'hzzzz;
                assign ep2_busy=~ep2_t;
 
endmodule

Line No.	Rev	Author	Line
1	39	simon111	`// the usb controler module`
2
3			`// now this control support 3 endpoint`
4			`// ep2, output data`
5			`// ep6, input data`
6			`// ep8, input data`
7
8			`module usb_cnt (`
9			`input clk`
10			`, output pktend //`
11			`, output reg sloe // output enable , high active`
12			`, output reg slwr // fifo write signal, low active`
13			`, output slcs // fifo chip select, low active`
14			`, output reg slrd // fifo read , low active`
15			`, output reg [ 1:0] fifoadr // fifo address, 00-ep2 01 -- ep4 10--ep6 11--pe8`
16			`, inout [15:0] fd // data bus`
17			`// endpoint data ports`
18			`// ep2`
19			`, input ep2_t // ep2 full flag, low active`
20			`, output ep2_busy // ep2 busy, high active`
21			`, input ep2_wr // ep2 write signal`
22			`, input [15:0] ep2_data`
23			`// ep6`
24			`, input ep6_t // ep6 empty flag, low active`
25			`, output ep6_f // ep6 have data coming`
26			`, output [15:0] ep6_data`
27			`// ep8`
28			`, input ep8_t // ep8 empty flag, low active`
29			`, output ep8_f // ep8 have data coming`
30			`, output [15:0] ep8_data`
31			`);`
32
33			`define EP2_W 2'h3
34			`define EP6_R 2'h2
35			`define EP8_R 2'h1
36			`define NO_ACT 2'h0
37
38			`reg [1:0] last_action; // the active in lost clck`
39
40			`reg [15:0] usb_dat_in; // the data coming from fd`
41			`reg [15:0] usb_dat_out; // the data upgoing to fd`
42			`reg oe;`
43
44			`assign pktend = 1'h1;`
45			`assign slcs =1'h0;`
46
47			`always @(posedge clk)`
48			`if(ep2_t&ep2_wr)`
49			`begin`
50			`sloe <= 1'h0;`
51			`oe <= 1'h1;`
52			`slrd<=1'h1;`
53			`slwr<=1'h0;`
54			last_action<=`EP2_W;
55			`fifoadr<=2'h0;`
56			`end`
57			`else if(ep6_t)`
58			`begin`
59			`sloe <= 1'h0;`
60			`oe <= 1'h0;`
61			`slrd<=1'h0;`
62			`slwr<=1'h1;`
63			last_action<=`EP6_R;
64			`fifoadr<=2'h2;`
65			`end`
66			`else if(ep8_t)`
67			`begin`
68			`sloe <= 1'h0;`
69			`oe <= 1'h0;`
70			`slrd<=1'h0;`
71			`slwr<=1'h1;`
72			last_action<=`EP8_R;
73			`fifoadr<=2'h3;`
74			`end`
75			`else`
76			`begin`
77			`sloe <= 1'h1;`
78			`oe <= 1'h1;`
79			`slrd<=1'h1;`
80			`slwr<=1'h1;`
81			last_action<=`NO_ACT;
82			`fifoadr<=2'h0;`
83			`end`
84
85			`assign ep6_data=fd;`
86			assign ep6_f=last_action==`EP6_R;
87			`assign ep8_data=fd;`
88			assign ep8_f=last_action==`EP8_R;
89			`assign fd=(oe)?ep2_data:16'hzzzz;`
90			`assign ep2_busy=~ep2_t;`
91
92			`endmodule`

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[/] [csa/] [trunk/] [quartus10/] [usb_cnt.v] - Blame information for rev 39