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[/] [csa/] [trunk/] [rtl/] [decrypt.v] - Blame information for rev 32

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1 18 simon111
 
2
// this module will do csa decrypt work
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4 21 simon111
module decrypt(clk,rst,ck,key_en,even_odd,en,encrypted,decrypted,invalid);
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input             clk;
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input             rst;
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input             key_en;    // signal high valid,
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input             even_odd;  // indiate the input ck is even or odd, 0 --- even odd ---odd
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input             en;        // decrypted
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input  [8*8-1:0]  ck;        // input ck
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input  [  8-1:0]  encrypted; // input ts stream
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output [  8-1:0]  decrypted; // decrypt ts stream
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output            invalid;   // thsi output data is invalid
14 20 simon111
 
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16 21 simon111
// key register 
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reg  [56*8-1 : 0] even_kk;
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reg  [56*8-1 : 0] odd_kk;
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reg  [ 8*8-1 : 0] even_ck;
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reg  [ 8*8-1 : 0] odd_ck;
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reg               even_odd_d;
22 20 simon111
 
23 21 simon111
wire [56*8-1 : 0] kk;
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wire              ks_busy;
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wire              ks_done;
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27 21 simon111
key_schedule ks(
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                        .clk  (clk)
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                      , .rst  (rst)
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                      , .start(key_en)
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                      , .busy (ks_busy)
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                      , .done (ks_done)
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                      , .i_ck (ck)
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                      , .o_kk (kk)
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               );
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37 21 simon111
always @(posedge clk)
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begin
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        if(rst)
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        begin
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                even_kk <=  448'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
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                odd_kk <=  448'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
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                even_ck <=  64'h0000000000000000;
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                odd_ck <=  64'h0000000000000000;
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        end
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        else
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        begin
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                if(key_en & ~ks_busy)
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                begin
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                        even_odd_d <= even_odd;
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                        if(even_odd)
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                        begin
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                                odd_ck <= ck;
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                        end
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                        else
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                        begin
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                                even_ck <= ck;
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                        end
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                end
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                else if (ks_done)
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                        if(even_odd_d)
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                                odd_kk <= kk;
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                        else
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                                even_kk <= kk;
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        end
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end
67 20 simon111
 
68 21 simon111
// word grouper
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reg  [8*8-1:0] group;    // 32bits
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reg            sync;     // find sync
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reg  [8-1:0]   ts_cnt;   // ts packet count
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reg            using_even_odd_key; // 0 --- using even key; 1 --- using odd key
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reg            need_dec;
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reg            group_valid;
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reg            group_valid_d;
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reg            head;
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reg   [5:0]    group_id;
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reg [4*8-1:0] group_d;
79 20 simon111
 
80 21 simon111
 
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always @(posedge clk)
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        if (rst)
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        begin
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                group  <= 64'h00000000;
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                sync   <= 1'h0;
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                ts_cnt <= 8'h00;
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                using_even_odd_key <= 1'h0;
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                need_dec <= 1'h0;
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                group_valid_d <=1'h0;
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                head <= 1'h0;
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        end
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        else
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        begin
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                group_valid <=1'h0;
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                group_valid_d <= group_valid;
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                head <= 1'h0;
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                group_d <= group;
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                if(sync)
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                begin
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                        if(en)
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                                ts_cnt <= ts_cnt + 8'h01;
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                        if(ts_cnt == 8'hb7 ) // 0xb8=188-4
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                        begin
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                                sync <= 1'h0;
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                                ts_cnt<=8'h0;
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                                group_valid<=1'h1;
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                                group_id<=ts_cnt[7:3];
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                        end
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                        if(ts_cnt[2:0]==3'h7 && en )
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                        begin
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                                group_valid<=1'h1;
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                                group_id<=ts_cnt[7:3];
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                        end
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                end
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                if(en)
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                begin
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                        group  <= {  encrypted, group [8*8-1:1*8] };
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                        if(group[5*8-1:4*8]==8'h47)
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                        begin
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                                sync   <= 1;
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                                ts_cnt <= 8'h00;
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                                using_even_odd_key <= group[62];
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                                head  <= 1'h1;
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                                group_d <= {1'h0,group[62:32]};
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                        end
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                end
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        end
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// decrypt
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reg  [8*8-1:0] db;
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reg            db_valid;
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wire [56*8-1:0]kk_decrypt;
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wire [ 8*8-1:0]ck_decrypt;
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assign   kk_decrypt = (using_even_odd_key) ? odd_kk : even_kk ;
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assign   ck_decrypt = (using_even_odd_key) ? odd_ck : even_ck ;
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wire [8*8-1:0] sc_sb;
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wire [8*8-1:0] sc_cb;
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wire           init;
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wire           sc_en;
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wire           last;
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assign sc_sb = group;
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assign init  = group_id == 5'h00;
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assign last  = group_id == 5'd22;
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reg     [2:0] last_cnt;
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reg     last_run;
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assign sc_en = group_valid;
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stream_cypher sc(
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                    .clk   (clk)
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                  , .rst   (rst)
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                  , .en    (sc_en)
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                  , .init  (init)
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                  , .ck    (ck_decrypt)
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                  , .sb    (sc_sb)
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                  , .cb    (sc_cb)
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                  );
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wire [ 8*8-1:0]   bco;
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reg  [ 8*8-1:0]   bc;
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reg  [ 8*8-1:0]   ib;
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block_decypher bcm(
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                          .kk (kk_decrypt)
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                        , .ib (ib[8*8-1:0])
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                        , .bd (bco)
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                        );
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always @(posedge clk)
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if(rst)
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begin
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        db <= 64'h00;
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        ib <= 128'h00000000000000000000000000000000;
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        bc <= 64'hffffffffffffffff;
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        last_cnt<=3'h0;
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        last_run<=1'h0;
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end
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else
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begin
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        db_valid<=1'h0;
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        if(group_valid_d)
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        begin
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                bc<=bco;
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                if(init)
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                begin
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                        ib<={ ib[8*8-1:0],sc_cb };
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                        db<=bco^sc_cb;
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                end
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                else
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                begin
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                        ib<={ ib[8*8-1:0],sc_cb^sc_sb };
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                        db<=bco^sc_cb^sc_sb;
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                end
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                if(group_id>1'h0)
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                begin
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                        db_valid<=1'h1;
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                end
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                if(last)
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                        last_run<=1'h1;
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        end
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        if(last_run)
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        begin
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                last_cnt<=last_cnt+3'h1;
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                if(last_cnt==3'h7)
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                begin
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                        db_valid<=1'h1;
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                        db<=bco;
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                        last_run<=1'h0;
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                end
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216
        end
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end
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// degrouper
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reg [2:0]     cnt;
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reg           invalid;
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reg [7:0]     decrypted;
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reg [7*8-1:0] dec_group_ouput;
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225
always @(posedge clk)
226
        if(rst)
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        begin
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                dec_group_ouput <= 32'h00000000;
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                cnt <= 2'h0;
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        end
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        else
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        begin
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                invalid <= 1'h0;
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                if(db_valid)
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                begin
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                        dec_group_ouput <= db[8*8-1:1*8];
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                        decrypted <= db[7:0];
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                        cnt <= 3'h7;
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                        invalid <= 1'h1;
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                end
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                if(cnt)
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                begin
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                        invalid <= 1'h1;
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                        dec_group_ouput <= {dec_group_ouput [7:0],dec_group_ouput[7*8-1:1*8]};
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                        decrypted <= dec_group_ouput [ 7:0 ];
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                        cnt <= cnt - 2'h1;
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                end
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                if(head)
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                begin
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                        dec_group_ouput <= group_d[4*8-1:1*8];
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                        decrypted <= group_d[7:0];
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                        cnt <= 2'h3;
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                        invalid <= 1'h1;
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                end
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        end
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259 18 simon111
endmodule

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