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[/] [csa/] [trunk/] [rtl/] [key_cnt.v] - Blame information for rev 41

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`include "../bench/timescale.v"
 
// this module manage two keys (odd even)
 
module key_cnt(
                  input                    clk
                , input                    rst
                , input                    en
                , input                    evenodd
                , input         [8*8-1:0]  ck_in
                , output                   busy
                , output  reg   [8*8-1:0]  odd_ck
                , output  reg  [56*8-1:0]  odd_kk
                , output  reg   [8*8-1:0]  even_ck
                , output  reg  [56*8-1:0]  even_kk
                 );
 
        reg           evenodd_d;
        wire          done;
        wire [56*8-1:0] kk;
 
        always @(posedge clk)
                if(rst)
                begin
                        even_ck <=  64'h0000000000000000;
                        odd_ck <=  64'h0000000000000000;
                end
                else
                if(en & ~busy)
                begin
                        evenodd_d<=evenodd;
                        if(evenodd)
                                odd_ck<=ck_in;
                        else
                                even_ck<=ck_in;
                end
 
        always @(posedge clk)
                if(rst)
                begin
                        even_kk <=  448'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
                        odd_kk <=  448'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
                end
                else
                if(done)
                begin
                        if(evenodd_d)
                                odd_kk<=kk;
                        else
                                even_kk<=kk;
                end
 
 
key_schedule key_schedule(
                        .clk  (clk)
                      , .rst  (rst)
                      , .start(en&~busy)
                      , .busy (busy)
                      , .done (done)
                      , .i_ck (ck_in)
                      , .o_kk (kk)
               );
 
endmodule

Line No.	Rev	Author	Line
1	41	simon111	`include "../bench/timescale.v"
2
3			`// this module manage two keys (odd even)`
4
5			`module key_cnt(`
6			`input clk`
7			`, input rst`
8			`, input en`
9			`, input evenodd`
10			`, input [8*8-1:0] ck_in`
11			`, output busy`
12			`, output reg [8*8-1:0] odd_ck`
13			`, output reg [56*8-1:0] odd_kk`
14			`, output reg [8*8-1:0] even_ck`
15			`, output reg [56*8-1:0] even_kk`
16			`);`
17
18			`reg evenodd_d;`
19			`wire done;`
20			`wire [56*8-1:0] kk;`
21
22			`always @(posedge clk)`
23			`if(rst)`
24			`begin`
25			`even_ck <= 64'h0000000000000000;`
26			`odd_ck <= 64'h0000000000000000;`
27			`end`
28			`else`
29			`if(en & ~busy)`
30			`begin`
31			`evenodd_d<=evenodd;`
32			`if(evenodd)`
33			`odd_ck<=ck_in;`
34			`else`
35			`even_ck<=ck_in;`
36			`end`
37
38			`always @(posedge clk)`
39			`if(rst)`
40			`begin`
41			`even_kk <= 448'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;`
42			`odd_kk <= 448'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;`
43			`end`
44			`else`
45			`if(done)`
46			`begin`
47			`if(evenodd_d)`
48			`odd_kk<=kk;`
49			`else`
50			`even_kk<=kk;`
51			`end`
52
53
54			`key_schedule key_schedule(`
55			`.clk (clk)`
56			`, .rst (rst)`
57			`, .start(en&~busy)`
58			`, .busy (busy)`
59			`, .done (done)`
60			`, .i_ck (ck_in)`
61			`, .o_kk (kk)`
62			`);`
63
64			`endmodule`

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[/] [csa/] [trunk/] [rtl/] [key_cnt.v] - Blame information for rev 41