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[/] [csa/] [trunk/] [rtl/] [ts_sync.v] - Blame information for rev 49

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`include "../bench/timescale.v"
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// this module probe the ts sync head,
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module ts_sync(
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               input                 clk
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             , input                 rst
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             , input                 en
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             , input         [8-1:0] datain
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             , output  reg           valid
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             , output  reg           head     // find ts packet head
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             , output  reg           init     // the first dec ts packet
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             , output  reg           dec      // this ts group need decrypt
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             , output  reg           evenodd  // the current key type
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             , output  reg [8*8-1:0] group
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             , output  reg     [3:0] bytes    // valid bytes in group
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        );
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        reg sync;
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        reg need_dec; // current packet need decrypt;
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        reg [8*8-1:0] group_d;
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        reg [7:0] ts_cnt; // 
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        always @(posedge clk)
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                if(rst)
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                begin
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                        valid<=1'h0;
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                        head<=1'h0;
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                        dec<=1'h0;
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                        sync<=1'h0;
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                        need_dec<=1'h0;
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                        ts_cnt<=8'h0;
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                        init<=1'h0;
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                end
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                else
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                begin
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                        head<=1'h0;
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                        dec<=1'h0;
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                        valid<=1'h0;
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                        init<=1'h0;
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                        if(en)
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                        begin
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                                group_d <= {datain, group_d[8*8-1:1*8] };
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                        end
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                        if(sync)
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                        begin
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                                if(ts_cnt==8'h1&&en)
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                                begin
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                                        need_dec<=1'h0;
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                                        sync<=1'h0; // ts packet end
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                                end
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                                if(ts_cnt[2:0]==3'h1&&en)
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                                begin
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                                        valid<=1'h1;
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                                        dec<=need_dec;
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                                        bytes<=4'h8;
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                                        group   <={datain, group_d[8*8-1:1*8] } ;
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                                end
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                                if(ts_cnt==8'hb1&en)
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                                        init<=1'h1;
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                                if(en)
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                                        ts_cnt <= ts_cnt - 8'h1;
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                        end
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                        if(en)
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                        begin
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                                if(group_d[6*8-1:5*8]==8'h47)
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                                begin
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                                        sync<=1'h1;
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                                        valid<=1'h1;
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                                        head<=1'h1;
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                                        bytes<=4'h4;
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                                        group <= {32'h000,1'h0,datain[6:0],group_d[8*8-1:5*8]};
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                                        evenodd <= datain[6];
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                                        need_dec<=datain[7];
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                                        ts_cnt <= 8'hb8;
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                                end
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                        end
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                end
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endmodule

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