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regttycomi |
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 10:31:51 12/08/2008
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// Design Name:
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// Module Name: DMA_RAM - Behavioral
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module D_RAM(
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input CLK4 ,
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input DMA_ARM ,
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input PS2WrIDE , // High if PS2 DMA write to IDE bus
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//// =====
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input CRC_ARM ,
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input CRC_ENB , // the enable for the CRC circuit
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output [15:0] CRC_Q ,
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//// =====
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output [3:0] BufSize , // data size in 512 bytes ready
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output BufEmpty , // set when no words in the FIFO buffer
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//// =====
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input [15:0] DInA ,
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output [15:0] DOutA ,
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input [31:0] DInB ,
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output [31:0] DOutB ,
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//// =====
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output PA_HvSpace ,
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output PA_OD_Rdy , // some data availabe for output from Port A
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output PA_AlmostFull , // set when buffer has only 4 words left
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output PA_Empty, // set when buffer is all drained
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output PA_Full, // Register is full.
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output WithinABlock ,
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output reg A0, // A0 to put signal to IDE_DMA
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input HWOE, // select high order word to output
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input RegEA,
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input IncAddrA ,
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input EnbA , // enable and the control signal
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input WrA ,
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//// =====
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output PB_HvSpace ,
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output PB_OD_Rdy , // some data availabe for output from Port B
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output WithinBBlock , // high if (AddrB[6] | AddrB[5]) = 1
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output BBurstEnd , // high if AddrB = xxxx11111 = 1F
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input IncAddrB ,
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input RegEB ,
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input EnbB ,
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input WrB
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);
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//////////////////////////////////////////////////////
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wire R0Enb,R1Enb,R0Wr,R1Wr,RegEA0,RegEA1;
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wire [15:0] DOutA0,DOutA1,DInBL,DInBH,DOutBL,DOutBH;
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reg [9:0] AddrA,AddrB;
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reg [3:0] Page;
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wire IncPgA,IncPgB;
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wire PageNZ,PageZR;
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wire HvSpaceA,HvSpaceB;
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wire A_Zero,B_Zero;
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////-=========================================================================
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RAM1 RAM_Lo (
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.clka (CLK4),
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.dina (DInA), // IDE side data bits
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.addra (AddrA),
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.ena (R0Enb),
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.wea (R0Wr),
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.regcea (RegEA0),
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.douta (DOutA0),
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//
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.clkb (CLK4),
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.dinb (DInBL), // PS2 side data bus
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.addrb (AddrB),
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.enb (EnbB),
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.regceb (RegEB),
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.web (WrB),
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.doutb (DOutBL)
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);
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//// =========================================
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RAM1 RAM_Hi(
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.clka (CLK4),
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.dina (DInA), // IDE side data bits
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.addra (AddrA),
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.ena (R1Enb),
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.wea (R1Wr),
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.regcea (RegEA1),
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.douta (DOutA1),
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//
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.clkb (CLK4),
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.dinb (DInBH), // PS2 side data bus
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.addrb (AddrB),
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.enb (EnbB),
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.regceb (RegEB),
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.web (WrB),
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.doutb (DOutBH)
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);
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//// =========================================
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CRC_CAL CRC(
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.CLK4 (CLK4), // same as RAM clock
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.D (DInA), //- same as the RAM data
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.CRC_ARM (CRC_ARM), //- from the controller unit
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.CRC_ENB (CRC_ENB),
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.CRC_Q (CRC_Q)
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);
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//-=============================================================================
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//-==== Connect the RAM
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assign DOutA[15:0] = (HWOE == 1'b1) ? DOutA1[15:0] : DOutA0[15:0];
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assign DOutB[31:16] = DOutBH[15:0];
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assign DOutB[15:0] = DOutBL[15:0];
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assign DInBH[15:0] = DInB[31:16];
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assign DInBL[15:0] = DInB[15:0];
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assign R0Enb = EnbA & ~A0;
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assign R1Enb = EnbA & A0;
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assign R0Wr = WrA & ~A0;
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assign R1Wr = WrA & A0;
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assign RegEA0 = RegEA & ~A0;
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assign RegEA1 = RegEA & A0;
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////
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//// = the page counter ////
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assign IncPgA = IncAddrA & AddrA[6] & AddrA[5] & AddrA[4] & AddrA[3] & AddrA[2] & AddrA[1] & AddrA[0] & A0;
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assign IncPgB = IncAddrB & AddrB[6] & AddrB[5] & AddrB[4] & AddrB[3] & AddrB[2] & AddrB[1] & AddrB[0];
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assign BufEmpty = PageZR & A_Zero & B_Zero;
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////////-=======================================================
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assign HvSpaceA = ~Page[3] & ( ~(Page[2] & Page[1] & Page[0]) | A_Zero );
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assign HvSpaceB = ~Page[3] & ( ~(Page[2] & Page[1] & Page[0]) | B_Zero );
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assign PageNZ = Page[3] | Page[2] | Page[1] | Page[0];
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assign PageZR = ~(Page[3] | Page[2] | Page[1] | Page[0]);
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assign A_Zero = ~(AddrA[6] | AddrA[5] | AddrA[4] | AddrA[3] | AddrA[2] | AddrA[1] | AddrA[0]);
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assign PA_Empty = PageZR & A_Zero & ~A0;
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assign B_Zero = ~(AddrB[6] | AddrB[5] | AddrB[4] | AddrB[3] | AddrB[2] | AddrB[1] | AddrB[0]);
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assign PA_OD_Rdy = PageNZ;
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assign PA_HvSpace = HvSpaceA; // have 512 byte space at least
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assign PA_AlmostFull = Page[3] | (Page[2] & Page[1] & Page[0] & AddrA[6] & AddrA[5] & AddrA[4] & AddrA[3]);
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// PA_Full - a signal set high to indicate all buffer area is used up and until clear one page, should
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// not start DMA read into Port A
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// This signal will be high if incremented and will keep high until PortB dec it
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assign PA_Full = Page[3];
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assign WithinABlock = AddrA[6] | AddrA[5] | AddrA[4] | AddrA[3] | AddrA[2] | AddrA[1] | AddrA[0] | A0;
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////
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assign PB_OD_Rdy = PageNZ; // if there is more than one page of data
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assign PB_HvSpace = HvSpaceB; // if there is space in buffer
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assign WithinBBlock = AddrB[6] | AddrB[5] | AddrB[4] | AddrB[3] | AddrB[2] | AddrB[1] | AddrB[0];
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assign BBurstEnd = AddrB[4] & AddrB[3] & AddrB[2] & AddrB[1] & AddrB[0]; // high if AddrB = xxxx11111 = 1F
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////////
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assign BufSize[3:0] = Page[3:0];
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////- ============================================================================
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always @(posedge CLK4) begin
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if (DMA_ARM == 1'b0)
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AddrB <= 10'b00_0000_0000;
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else
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if(IncAddrB == 1'b1)
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AddrB <= AddrB + 1;
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end
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always @(posedge CLK4) begin
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if (DMA_ARM == 1'b0) begin
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AddrA <= 10'b00_0000_0000;
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A0 <= 1'b0;
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end else begin
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if(IncAddrA == 1'b1) begin
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if (A0 == 1'b1) begin
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AddrA <= AddrA + 1;
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A0 <= 1'b0;
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end else begin
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A0 <= 1'b1;
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end
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end
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end
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end
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always @(posedge CLK4) begin
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if (DMA_ARM == 1'b0) begin
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Page <= 4'b0000;
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end else begin
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if (PS2WrIDE == 1'b1) begin // PS2 writes to drive
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if (IncPgB == 1'b1) begin
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if (IncPgA == 1'b0) Page <= Page + 1; // buffer increase in size
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end else begin
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if (IncPgA == 1'b1) Page <= Page - 1; // buffer decrease in size
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end
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end else begin
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if (IncPgA == 1'b1) begin
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if (IncPgB == 1'b0) Page <= Page + 1; // buffer has increase in size
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end else begin
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if (IncPgB == 1'b1) Page <= Page - 1; // buffer decrease in size
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end
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end // PS2WrIDE
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end // DMA_ARM
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end // always
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endmodule
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