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regttycomi |
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 13:53:18 09/05/2008
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// Design Name:
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// Module Name: chip - Behavioral
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module chip(
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inout [15:0] iD ,
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// iD15..8 = LQFP(32);LQFP(31);LQFP(30);LQFP(29);LQFP(28);LQFP(27);LQFP(25);LQFP(24);
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// iD7..0 = LQFP(49);LQFP(48);LQFP(47);LQFP(46);LQFP(21);LQFP(20);LQFP(19);LQFP(42);
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output [2:0] iA,
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// iA2 = I50(3)/LQFP(8); iA1 = I50(5)/LQFP(5); iA0 = I50(4)/LQFP(7);
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output ibCS0 , // LQFP(10)/I50(2)
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output ibCS1 , // LQFP(11)/I50(1)
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output ibRST , // LQFP(121)/I50(50)
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input iIRQ , // LQFP(12)/I50(6) ( needs pull up)
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output ibWr , // LQFP(3)/I50(14)
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output ibRd , // LQFP(6)/I50(12)
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input iDQ , // LQFP(18)/I50(16)(1) DMA request - (need pull low) drive inform chip that it wishes to do DMA
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output ibDK , // LQFP(4)/I50(8)(0) DMA acknoledge - chip inform drive that DMA is in progress
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input iRdy , // LQFP(16)/I50(10)(1) high - will means IO channel ready, (needs pull up)
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input ibDASP , // LQFP(13)/I50(7)(0) low - will shows drive is active
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//////- the CN110 interface
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input CLKin , // LQFP(129)/J110(81) = 36.6MHz (27.27nS clock pulses)
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input bCSRST , // LQFP(69)/J110(49)power on is high
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input bCRST , // LQFP(70)/J110(52)actual reset signal
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inout [15:0] cDP , // data bus
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// cDP(15..8) = LQFP/J110 = (114/2,113/6,112/8,111/12,110/14,105/18,104/20,103/24)
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// cDP(7 ..0) = LQFP/J100 = (102/26,101/30,99/32,98/36,120/38,117/42,116/44,115/48)
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inout [15:0] cAP , // address bus
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// cAP(15..8) = LQFP/J110 = (96/1,93/3,92/7,91/9,90/13,88/15,87/19,85/21)
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// cAP(7 ..0) = LQFP/J110 = (84/25,83/27,82/31,79/33,78/37,77/39,76/43,75/45)
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//
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input bcCS , // LQFP(50)/J110(72)
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input bcWr , // LQFP(60)/J110(73)
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input bcRd , // LQFP(58)/J110(77)
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input bCRT , // LQFP(51)/J110(70)
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//
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output bcWait , // LQFP(64)/J110(59) ** high a 120ns pulse
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output bcIRQ , // LQFP(68)/J110(55) ** high at int9
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output cDQ , // LQFP(54)/J110(66)
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input cDK , // LQFP(55)/J110(62)
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//
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output DR245 , // LQFP(45)
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output OE245 , // LQFP(43)
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//
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////- the following signals are connected but never change
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input ACS_LED , // LQFP(63)/J110(90) measured high always (pull-high)
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input HDD_ACK , // LQFP(59)/J110(92) measured high always (pull-high)
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////- the following signals are unconnected in the original board
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// input INP1 , // LQFP(33)
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// input INP2 , // LQFP(35)
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// input INP3 , // LQFP(53)
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// input INP4 , // LQFP(80)
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// input INP5 , // LQFP(97)
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// input INP6 , // LQFP(123)
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// input INP7 , // LQFP(140)
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inout TFD0 , // LQFP(124) TFlash SD D0 (I/OPP) or SPI Data Out (OPP)
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inout TFD1 , // LQFP(125) TFlash SD D1 (I/OPP) or SPI reserve
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inout TFD2 , // LQFP(126) TFlash SD D2 (I/OPP) or SPI reserve
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inout TFD3 , // LQFP(127) TFlash SD D3 (I/OPP) or SPI Chip Select bCS (I)
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output TFCLK , // LQFP(130) TFlash CLK
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input TFSENSE , // LQFP(131) TFlash Sense ( low if TF inserted )
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output TFCMD , // LQFP(132) TFlash Command or SPI Data In (I)
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// Fixed signals for connecting the SPI external flash
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// FbCS,FMOSI,FDIN,FCCLK {LQFP(41,62,71,72)}
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//
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// testing signals
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//
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output JT_Result , // LQFP(44)
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output JT_Pin1 , // LQFP(37)
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input JT_bTest // LQFP(38)
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);
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wire DCM_RST,CLK1,CLK4,DCM_LOCKED ;
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reg DWrite;
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wire IDERd,IDEWr;
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reg iIRQ1;
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reg iDQ1,SiIRQ,SiDQ;
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wire iDMARd,iDMAWr ;
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wire BufEmpty ;
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wire PA_HvSpace,PA_OD_Rdy ;
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wire PB_HvSpace,PB_OD_Rdy ;
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wire WithinBBlock,BBurstEnd;
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wire WithinABlock;
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wire iCS0,iCS1,cWr,cRd,iWr,iRd,iDK ;
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wire [15:0] RegData;
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wire [31:0] DMARAMQ;
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reg [31:0] DMARAMD;
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reg [15:0] DIn1,DIn2;
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wire cDMA_OE ;
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wire cRdt; // tri-state control signal
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wire RegEB; // the register control signal
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//////
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//wire RegSC,RegCMD _vector(7 downto 0);
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//////-=============================================
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//// read only registers ( logical wire groups )
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wire [7:0] Reg0038 ;
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//// wire Reg0002,Reg0004,Reg000E _vector(7 downto 0);
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wire [15:0] Reg0028 ;
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//// write only registers
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//wire Reg002C,Reg0070,Reg0072,Reg0074 _vector(7 downto 0);
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////- read write registers //// =====================
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reg [7:0] Reg002A;
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wire [7:0] Reg002E;
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reg [7:0] Reg0064;
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////////- ===========================================
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//wire AICtrl,DICtrl ;
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wire cDOE,cAOE ;
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wire IDE_CS;
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reg DMA_ARM,DMARMC,PS2WrIDE ;
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wire PA_AlmostFull ;
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wire [3:0] BufSize;
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reg [2:0] R44;
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wire INT9,INT9OE,DMA_IrqCond;
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reg DMA_IrqMask, DMA_IrqFF; // set high if DMA IRQ condition met
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wire DMA_IrqCTRL ;
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wire bHardReset;
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reg ATV1,ATV2,ATV;
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wire UDMAC,CmdIsEF,UDMA_SEL,MDMA_SEL,D_UnChg ;
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reg R42Is03,R44Is2X,R44Is4X;
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wire [2:0] UDMA,MDMA;
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reg [2:0] UDO;
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reg [2:1] MDO;
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wire Combo_CS,Combo_OE ;
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reg cWr1,cRd1,ScWr,ScRd,ScWr1,ScRd1 ;
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wire [15:0] cAi,cDi,CRC_Q,iDi,iDO,DOutA;
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wire iDOEnb,CRC_MUX ;
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wire IDEiOE,iDMA_OE ;
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reg [6:0] cRgA;
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reg [7:0] cRgD;
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wire cRgRd2E,cRgWr;
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reg bcRd2E;
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reg cRgWrEnb ;
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reg [5:0] Rd2ECnt;
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reg [3:0] cWaitCnt;
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reg cWait;
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//// wire BusMatch ;
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wire iD_245_In,IDE_Rd_Env ; // standard logic for envelop
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reg SiRdy2,SiRdy1; // a short input buffer
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reg IgnoreIRdyPin; // if IORDY from the drive is always low, then ignore it in normal IDE IO-Read Write cycles
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reg Ph0,Ph1,Ph2,Phase3;
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wire Reg002E_0, Reg002E_1, Reg002E_2, Reg002E_3, Reg002E_5, Reg002E_6, Reg002E_7;
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reg Reg002E_4;
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assign Reg002E = {Reg002E_7, Reg002E_6, Reg002E_5, Reg002E_4, Reg002E_3, Reg002E_2, Reg002E_1, Reg002E_0};
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//wire ProbeOut ;
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//wire ClrDMAPulse,ClrD1,ClrD2 ;
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//// =====================
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//wire IDE_INTF_STATE,IDE_DMA_STATE,PS2_DMA_STATE _vector(15 downto 0);
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//wire D_RAM_ReportOut _vector(15 downto 0);
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//wire D_RAM_ReportIn _vector(1 downto 0);
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//wire ReportOut _vector(15 downto 0);
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//wire ReportC _vector(5 downto 0);
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//wire R380016 _VECTOR(15 DOWNTO 0);
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//wire iRdd1,iRdd2,DOEnb ;
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//// ================================================
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//wire [63:0] dna64bits;
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//reg [7:0] dnac;
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wire DNA_Pass,DNA_RST;
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wire [3:0] KILL; // 4 bit killer signals
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//reg DNAS0,DNAS1,DNAS2; // the DNA output control
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//wire DNA_CS,DNA_OE; // signal to show the DNA value to IDE bus
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//wire [15:0] DNAO;
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//// =========== test stubs ========================
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//ReportOut <= X"AAAA" when (ReportC(5 downto 2) = "0010") else
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// X"5555" when (ReportC(5 downto 2) = "0011") else
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// D_RAM_ReportOut when (ReportC(5 downto 4) = "01") else
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// PS2_DMA_STATE when (ReportC(5 downto 2) = "1000") else
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// IDE_DMA_STATE when (ReportC(5 downto 2) = "1001") else
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// IDE_INTF_STATE when (ReportC(5 downto 2) = "1010") else
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// Reg0028 when (ReportC(5 downto 2) = "1011") else
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// R380016 when (ReportC(5 downto 2) = "1100") else
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// X"CCCC";
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//D_RAM_ReportIn(1 downto 0) <= ReportC(3 downto 2);
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//R380016(15 DOWNTO 8) <= X"00";
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//R380016(7 DOWNTO 0) <= Reg0038;
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////////////////////////////////////////////////////-
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////////////////////////////////////////////////////-
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dcm3 Inst_DCM(
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.CLKIN_IN (CLKin),
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.RST_IN (DCM_RST),
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.CLKFX_OUT (CLK4),
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.CLKIN_IBUFG_OUT(), // same phase as CLKin
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.CLK0_OUT (CLK1), // same phase as CLK
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.LOCKED_OUT (DCM_LOCKED)
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);
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////- ===== TF machine ======
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TF_Stub Inst_TF_Stub(
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.RESET (DNA_RST),
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.CLK4 (CLK4),
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.TFD0 (TFD0),
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.TFD1 (TFD1),
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.TFD2 (TFD2),
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.TFD3 (TFD3), // same phase as CLKin
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.TF_CLK (TFCLK), // same pahse as CLK
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.TF_CMD (TFCMD),
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.TF_SENSE (TFSENSE)
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);
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////- ===== DNA
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Top dna1 (
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.reset(DNA_RST),
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.clk4(CLK4),
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.IDE_CS(IDE_CS),
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.dna_pass(DNA_Pass),
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.KILL(KILL)
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);
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////- ===============================================
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Reg38 R_38(
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.UDMAC (UDMAC),
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.PS2WrIDE (PS2WrIDE),
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.iIRQ (SiIRQ),
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.cDQ (cDQ),
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.iDQ (SiDQ), // synchronize iDQ
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.iDK (iDK),
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.BufEmpty (BufEmpty),
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.PB_HvSpace (PB_HvSpace),
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.BufSize (BufSize),
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.DOut (Reg0038)
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);
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////=========================================================
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PS2_DMA PS2DMA(
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// PS2_DMA_STATE (PS2_DMA_STATE),
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.CLK4 (CLK4),
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.Phase3 (Phase3), // the phases
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////// external pin interface
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.cDQ (cDQ), // DMA request output
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.cDK (cDK), // DMA acknowledge input
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.cRd (cRd), // read signal pulse
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.DWrite (DWrite), // write and counter pulse
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////// controlling signal
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.DMA_ARM (DMA_ARM), // signal from ctrllr to inits DMA
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.PS2WrIDE (PS2WrIDE), // level indicating that PS2 is DMA writing IDE bus
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//// PS2 DMA connecting to RAM interface
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.PB_HvSpace (PB_HvSpace), // there is empty space for Port B
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.PB_OD_Rdy (PB_OD_Rdy), // some data availabe for output from Port B
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////
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.WithinBBlock (WithinBBlock), // high if (AddrB(6) OR AddrB(5)) = 1
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.BBurstEnd (BBurstEnd), // high if AddrB = xxxx11111 = 1F
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.IncAddrB (IncAddrB),
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.RegEB (RegEB),
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.EnbB (EnbB),
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.WrB (WrB ) // write pulse
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);
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////-======================================================
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D_RAM DMARAM(
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.CLK4 (CLK4),
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.DMA_ARM (DMA_ARM),
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.PS2WrIDE (PS2WrIDE), // High if PS2 DMA write to IDE bus
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//// =====
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.CRC_ARM (CRC_ARM),
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.CRC_ENB (CRC_ENB),
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.CRC_Q (CRC_Q),
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//// =====
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.PA_HvSpace (PA_HvSpace), // there is empty space for Port A
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.PA_OD_Rdy (PA_OD_Rdy), // some data availabe for output from Port A
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.PA_AlmostFull (PA_AlmostFull),
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.PA_Full (PA_Full),
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.PA_Empty (PA_Empty),
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.WithinABlock (WithinABlock),
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//// =====
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.PB_HvSpace (PB_HvSpace), // there is empty space for Port B
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.PB_OD_Rdy (PB_OD_Rdy), // some data availabe for output from Port B
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//// =====
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.BufSize (BufSize),
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.BufEmpty (BufEmpty), // set when no words in the FIFO buffer
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//// =====
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.DInA (DIn2),
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.DOutA (DOutA),
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.DInB (DMARAMD),
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//// ==== 1st port RAM access
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.A0 (A0),
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|
|
.HWOE (HWOE),
|
304 |
|
|
.IncAddrA (IncAddrA),
|
305 |
|
|
.EnbA (EnbA),
|
306 |
|
|
.WrA (WrA),
|
307 |
|
|
.RegEA (RegEA),
|
308 |
|
|
//// ==== 2nd port RAM access
|
309 |
|
|
.WithinBBlock (WithinBBlock), // high if (AddrB(6) OR AddrB(5)) = 1
|
310 |
|
|
.BBurstEnd (BBurstEnd), // high if AddrB = xxxx11111 = 1F
|
311 |
|
|
.IncAddrB (IncAddrB),
|
312 |
|
|
.EnbB (EnbB),
|
313 |
|
|
.RegEB (RegEB),
|
314 |
|
|
.WrB (WrB),
|
315 |
|
|
.DOutB (DMARAMQ)
|
316 |
|
|
);
|
317 |
|
|
//// =========================================
|
318 |
|
|
IDE_DMA IDEDMA (
|
319 |
|
|
// IDE_DMA_STATE (IDE_DMA_STATE),
|
320 |
|
|
.CLK4 (CLK4),
|
321 |
|
|
.Phase3 (Phase3),
|
322 |
|
|
////// external pin interface
|
323 |
|
|
.iDK (iDK), // (o) DMA acknowledge output to harddisk
|
324 |
|
|
.iDQ (SiDQ), // (i) DMA request input from harddisk
|
325 |
|
|
.SiRdy1 (SiRdy1), // (i) IDE bus ready signal
|
326 |
|
|
.SiRdy2 (SiRdy2),
|
327 |
|
|
////// system signal
|
328 |
|
|
.DMA_ARM(DMA_ARM), // do not request transaction if this is not armed
|
329 |
|
|
.PS2WrIDE (PS2WrIDE), // (i) '1' if direction is from PS2 to IDE
|
330 |
|
|
.UDMA (UDMA),
|
331 |
|
|
.MDMA (MDMA),
|
332 |
|
|
.iDMARd (iDMARd), // (o) active high signal to indicate DMA read
|
333 |
|
|
.iDMAWr (iDMAWr), // (o) active high signal to indicate DMA write
|
334 |
|
|
.iDMA_OE (iDMA_OE), // (o) active high signal showing DMA wishes to drive iD bus
|
335 |
|
|
.iD_245_In (iD_245_In), // (o) active high envelop signal to drive output bus
|
336 |
|
|
.CRC_MUX (CRC_MUX), // inform system that need to drive the CRC Q to IDE bus
|
337 |
|
|
.CRC_ARM (CRC_ARM), // a signal indicate that to clear the CRC state
|
338 |
|
|
.CRC_ENB (CRC_ENB),
|
339 |
|
|
////// interface the RAM buffer), DMA machine will act according to buffer
|
340 |
|
|
.PA_HvSpace (PA_HvSpace), // there is empty space for Port A
|
341 |
|
|
.PA_OD_Rdy (PA_OD_Rdy), // some data availabe for output from Port A
|
342 |
|
|
.WithinABlock (WithinABlock),
|
343 |
|
|
.PA_AlmostFull(PA_AlmostFull),
|
344 |
|
|
.PA_Full (PA_Full),
|
345 |
|
|
.PA_Empty (PA_Empty),
|
346 |
|
|
.IDE_DSTB (IDE_DSTB),
|
347 |
|
|
.IncAddrA (IncAddrA),
|
348 |
|
|
.A0 (A0),
|
349 |
|
|
.HWOE (HWOE),
|
350 |
|
|
.EnbA (EnbA),
|
351 |
|
|
.WrA (WrA),
|
352 |
|
|
.RegEA (RegEA)
|
353 |
|
|
);
|
354 |
|
|
//// =========================================
|
355 |
|
|
|
356 |
|
|
//- Probes
|
357 |
|
|
// (I/P) JT_bTest is the tester control port, during config, this is high; this should be DONE signal inverted by a 74LS04
|
358 |
|
|
// (I/P) JT_Pin1 is the selection port of ROM
|
359 |
|
|
// (O/P) JT_Result is the result port (if DNA_Pass then it is low)
|
360 |
|
|
assign JT_Result = (JT_bTest == 1'b0) ? ( ~DNA_Pass ) : ( HDD_ACK | ACS_LED | ibDASP | bCRT ); // will output low if DNA_Pass
|
361 |
|
|
assign JT_Pin1 = TFCLK; // pull low for 50A, left high for 50AN
|
362 |
|
|
|
363 |
|
|
/// ===========================================================================
|
364 |
|
|
/// ===========================================================================
|
365 |
|
|
// ClrDMAPulse = ~(bcCS) & ~(bcWr) & ClrD1 & ClrD2;
|
366 |
|
|
// ClrD1 = '1' when (cAi(15 downto 0) = X"0032") else '0';
|
367 |
|
|
// ClrD2 = '1' when (cDi(15 downto 0) = X"0003") else '0';
|
368 |
|
|
|
369 |
|
|
////- === CLOCK & reset signals ===========================================
|
370 |
|
|
assign DCM_RST = ~bCRST | ~bCSRST; // drive high if any pin is low
|
371 |
|
|
assign bHardReset = bCRST & DCM_LOCKED; // the lowest level of reset
|
372 |
|
|
assign DNA_RST = ~DCM_LOCKED; // active high reset signal
|
373 |
|
|
/// ===== Phase generation logic ==================================
|
374 |
|
|
always @(negedge CLK1) begin
|
375 |
|
|
if (DCM_LOCKED == 1'b0) begin
|
376 |
|
|
Ph0 <= 1'b0;
|
377 |
|
|
end else begin
|
378 |
|
|
Ph0 <= ~Ph0; // a toggling signal
|
379 |
|
|
end
|
380 |
|
|
end
|
381 |
|
|
|
382 |
|
|
always @(negedge CLK4) begin
|
383 |
|
|
Ph1 <= Ph0;
|
384 |
|
|
Ph2 <= Ph1;
|
385 |
|
|
end
|
386 |
|
|
|
387 |
|
|
always @(posedge CLK4) begin
|
388 |
|
|
Phase3 <= Ph1 ^ Ph2;
|
389 |
|
|
end
|
390 |
|
|
//// ==========================================================================
|
391 |
|
|
|
392 |
|
|
|
393 |
|
|
//// ==========================================================================
|
394 |
|
|
// output signal
|
395 |
|
|
//// Register 64 signals
|
396 |
|
|
assign ibRST = ~(Reg0064[7]);
|
397 |
|
|
assign ibCS0 = ~(iCS0); // convert to correct pin polarity
|
398 |
|
|
assign ibCS1 = ~(iCS1);
|
399 |
|
|
assign ibRd = ~(iRd);
|
400 |
|
|
assign ibWr = ~(iWr);
|
401 |
|
|
assign ibDK = ~(iDK); // DMA acknowledge output, active low
|
402 |
|
|
//// IDE Data bus control signal
|
403 |
|
|
assign iRd = ( IDERd & ~iDK ) | (iDMARd & iDK);
|
404 |
|
|
assign iWr = ( IDEWr & ~iDK ) | (iDMAWr & iDK);
|
405 |
|
|
//////- the CN110 interface
|
406 |
|
|
// input signal
|
407 |
|
|
assign cRd = ~bcRd & ~KILL[0];
|
408 |
|
|
assign cRdt = ~bCRT & ~KILL[0]; // tristate control circuit
|
409 |
|
|
assign cWr = ~bcWr & ~KILL[0];
|
410 |
|
|
//// ============================================================================================
|
411 |
|
|
//// Interrupt signal
|
412 |
|
|
// interrupt will be set either by IDE interrupt line | an interrupt signal by DMA F/F
|
413 |
|
|
assign INT9OE = Reg002A[1] | Reg002A[0];
|
414 |
|
|
assign bcIRQ = (INT9OE == 1'b1) ? ~(INT9) : 1'bZ;
|
415 |
|
|
assign INT9 = (SiIRQ & Reg002A[0]) | (DMA_IrqFF & DMA_IrqCTRL);
|
416 |
|
|
////============= c-Connector data bus =======================
|
417 |
|
|
assign cDMA_OE = cRdt & cDK; // output the data bus
|
418 |
|
|
assign cDOE = ATV & (cDMA_OE | Combo_OE); // DMA/CS PS2 read will drive the bus
|
419 |
|
|
assign cDP = (cDOE == 1'b0) ? {16{1'bZ}} :
|
420 |
|
|
(cDK == 1'b1) ? DMARAMQ[15:0] :
|
421 |
|
|
(IDE_CS == 1'b1) ? iDi[15:0] : RegData[15:0];
|
422 |
|
|
assign cDi = cDP;
|
423 |
|
|
//- c-Connector Address bus
|
424 |
|
|
assign cAOE = ATV & cDMA_OE; // DMA PS2 read will drive the bus
|
425 |
|
|
assign cAP = (cAOE == 1'b0) ? {16{1'bZ}} : DMARAMQ[31:16];
|
426 |
|
|
assign cAi = cAP;
|
427 |
|
|
////
|
428 |
|
|
//// ============================================================================================
|
429 |
|
|
//// Control signals // must wait until bus matching for IDE signals
|
430 |
|
|
// assign BusMatch = ((cDi[15] ~^ iDi[15]) & (cDi[14] ~^ iDi[14]) & (cDi[13] ~^ iDi[13]) &
|
431 |
|
|
// (cDi[12] ~^ iDi[12]) & (cDi[11] ~^ iDi[11]) & (cDi[10] ~^ iDi[10]) &
|
432 |
|
|
// (cDi[9] ~^ iDi[9]) & (cDi[8] ~^ iDi[8]) & (cDi[7] ~^ iDi[7]) &
|
433 |
|
|
// (cDi[6] ~^ iDi[6]) & (cDi[5] ~^ iDi[5]) & (cDi[4] ~^ iDi[4]) &
|
434 |
|
|
// (cDi[3] ~^ iDi[3]) & (cDi[2] ~^ iDi[2]) & (cDi[1] ~^ iDi[1]) &
|
435 |
|
|
// (cDi[0] ~^ iDi[0]));
|
436 |
|
|
//- the combo chip select range = 0x0000-0x007F
|
437 |
|
|
assign Combo_CS = ATV & ~cDK & ~(bcCS | cAi[15] | cAi[14] | cAi[13] | cAi[12] |
|
438 |
|
|
cAi[11] | cAi[10] | cAi[9] | cAi[8] | cAi[7]);
|
439 |
|
|
assign Combo_OE = cRd & Combo_CS; // asynchronous active reading signal
|
440 |
|
|
|
441 |
|
|
//// ================== IDE interface section =================================================
|
442 |
|
|
|
443 |
|
|
//====== iDE data bus ================================
|
444 |
|
|
// IDE data bus control
|
445 |
|
|
// ProbeOut = (cWr | cRd) & ~(IDE_CS) & ~(iDK) & ~(cDK);
|
446 |
|
|
// iDOEnb = IDEiOE | iDMA_OE | ProbeOut; // signal we can drive the bus
|
447 |
|
|
//
|
448 |
|
|
// 090313
|
449 |
|
|
// The ORIGINAL signal
|
450 |
|
|
assign iD[15:0] = (iDOEnb == 1'b1) ? iDO[15:0] : {16{1'bZ}};
|
451 |
|
|
assign iDOEnb = IDEiOE | iDMA_OE; // signal we can drive the bus
|
452 |
|
|
assign iDi[15:0] = iD[15:0];
|
453 |
|
|
assign iDO[15:0] = (IDE_CS == 1'b1) ? cDi[15:0] :
|
454 |
|
|
(CRC_MUX == 1'b1) ? CRC_Q[15:0] : DOutA[15:0];
|
455 |
|
|
//
|
456 |
|
|
//// --- iD out also output DNA data
|
457 |
|
|
//// ==== The DNA showing session ====
|
458 |
|
|
// assign iDOEnb = 1'b1;
|
459 |
|
|
// assign iD[15:0] = iDO[15:0];
|
460 |
|
|
// assign iDO[15:0] = (dnac[7] == 1'b0) ?
|
461 |
|
|
// ((dnac[6] == 1'b0) ? dna64bits[63:48] : dna64bits[47:32] ) :
|
462 |
|
|
// ((dnac[6] == 1'b0) ? dna64bits[31:16] : dna64bits[15:0] );
|
463 |
|
|
// assign iDi[15:0] = iD[15:0];
|
464 |
|
|
////
|
465 |
|
|
//
|
466 |
|
|
// 090313
|
467 |
|
|
//
|
468 |
|
|
//
|
469 |
|
|
// 0000 0000 010* **** = 0x0040-0x005F
|
470 |
|
|
assign IDE_CS = Combo_CS & ~iDK & cAi[6] & ~cAi[5]; //- if address range is correct and we are not doing iDK
|
471 |
|
|
assign iCS1 = IDE_CS & cAi[4] & ~KILL[2];
|
472 |
|
|
assign iCS0 = IDE_CS & ~cAi[4] & ~KILL[2];
|
473 |
|
|
assign iA[2] = IDE_CS & cAi[3] & ~KILL[1];
|
474 |
|
|
assign iA[1] = IDE_CS & cAi[2] & ~KILL[2];
|
475 |
|
|
assign iA[0] = IDE_CS & cAi[1] & ~KILL[3];
|
476 |
|
|
assign IDERd = IDE_CS & cRd & ~KILL[1];
|
477 |
|
|
assign IDEWr = IDE_CS & cWr & ~KILL[2]; // narrow down the write pulse
|
478 |
|
|
assign IDEiOE = IDE_CS & cWr; // writing IDE, we drive the IDE i Bus
|
479 |
|
|
// IDE_Rd_Env = (IDE_CS & cRd) | IDERd1; // reading, we drive the 245 inwards
|
480 |
|
|
assign IDE_Rd_Env = IDE_CS & cRd;
|
481 |
|
|
//////////////////////////////////////////////////////////////////////
|
482 |
|
|
//- Local Register Block
|
483 |
|
|
//// ===== Read only registers
|
484 |
|
|
// Reg0002(7 downto 2) = "000100"; // prepare to be 13
|
485 |
|
|
// Reg0002(1) = ~(DNA_Fail); // should always be 1 ( ~ fail)
|
486 |
|
|
// Reg0002(0) = DNA_Pass; // should always be 1 (pass)
|
487 |
|
|
// Reg0002[7:0] = "00010011"; // fixed at 13
|
488 |
|
|
// Reg0004 = X"0B";
|
489 |
|
|
// Reg000E = X"02";
|
490 |
|
|
// Reg0028 has many bits being zero ////////////////////////
|
491 |
|
|
// Reg0028 is probably the DMA RAM Buffer register
|
492 |
|
|
// assign Reg0028[15] = Reg2815; // set when buffer is full
|
493 |
|
|
assign Reg0028[15] = BufSize[3]; // set when buffer is full
|
494 |
|
|
assign Reg0028[14] = BufEmpty;
|
495 |
|
|
// Reg0028(14) = (~(PS2WrIDE) & BufEmpty) | (PS2WrIDE & (AlmostEmpty | BufEmpty)); // BufEmpty
|
496 |
|
|
// Reg0028(14) = (~(PS2WrIDE) & (AlmostEmpty | BufEmpty)) | (PS2WrIDE & HaveSpace); // Performs much better than BufEmpty in xboot writing
|
497 |
|
|
// Reg0028(14) = AlmostEmpty; // Performs much better than BufEmpty in xboot writing
|
498 |
|
|
assign Reg0028[13:2] = 12'b0000_0000_0000;
|
499 |
|
|
assign Reg0028[1] = cDQ;
|
500 |
|
|
assign Reg0028[0] = SiIRQ; // the interrupt condition of external
|
501 |
|
|
//// Reg002A the interrupt control register ///////////////////////////////////////////
|
502 |
|
|
//// local registers //////////////////////////
|
503 |
|
|
assign RegData[15:8] = (cAi[6:0] == 7'h28) ? Reg0028[15:8] : 8'h00;
|
504 |
|
|
////////////////////////////////////////
|
505 |
|
|
assign RegData[7:0] = (cAi[6:0] == 7'h02) ? 8'h13 :
|
506 |
|
|
(cAi[6:0] == 7'h04) ? 8'h0B :
|
507 |
|
|
(cAi[6:0] == 7'h0E) ? 8'h02 :
|
508 |
|
|
(cAi[6:0] == 7'h28) ? Reg0028[7:0] :
|
509 |
|
|
(cAi[6:0] == 7'h2A) ? Reg002A[7:0] :
|
510 |
|
|
// (cAi[6:0] == 7'h2C) ? Reg002C[7:0] :
|
511 |
|
|
(cAi[6:0] == 7'h2E) ? Reg002E[7:0] :
|
512 |
|
|
(cAi[6:0] == 7'h38) ? Reg0038[7:0] :
|
513 |
|
|
(cAi[6:0] == 7'h64) ? Reg0064[7:0] : 8'h00;
|
514 |
|
|
////- Reg0064 has zero bits write 4C then will write IDECmd87 to set direction
|
515 |
|
|
// Probably Reg0064 is the reset & interrupt control
|
516 |
|
|
// if reading & PortB have data
|
517 |
|
|
// | Writing & PortA have space
|
518 |
|
|
assign DMA_IrqCond = (~(PS2WrIDE) & PB_OD_Rdy) | (PS2WrIDE & PB_HvSpace);
|
519 |
|
|
assign DMA_IrqCTRL = Reg002A[1];
|
520 |
|
|
|
521 |
|
|
////- ====================================
|
522 |
|
|
assign UDMAC = UDO[2] | UDO[1] | UDO[0];
|
523 |
|
|
//////////////////////////////////////////////////////////////////
|
524 |
|
|
|
525 |
|
|
|
526 |
|
|
//- ===== selecting the drive mode is by ===
|
527 |
|
|
//- ATA command set features (EF,xx,xx,xx,xx,Table20,03)
|
528 |
|
|
assign CmdIsEF = cRgD[7] & cRgD[6] & cRgD[5] & ~(cRgD[4]) & cRgD[3] & cRgD[2] & cRgD[1] & cRgD[0];
|
529 |
|
|
assign UDMA_SEL = CmdIsEF & R44Is4X & R42Is03;
|
530 |
|
|
assign MDMA_SEL = CmdIsEF & R44Is2X & R42Is03;
|
531 |
|
|
assign D_UnChg = ~(UDMA_SEL | MDMA_SEL); // do not change the data if both control are low
|
532 |
|
|
assign UDMA[2:0] = UDO[2:0];
|
533 |
|
|
assign MDMA[2] = MDO[2];
|
534 |
|
|
assign MDMA[1] = MDO[1];
|
535 |
|
|
assign MDMA[0] = ~(UDO[2] | UDO[1] | UDO[0] | MDO[2] | MDO[1]);
|
536 |
|
|
//////- =======================================
|
537 |
|
|
assign Reg002E_7 = 1'b1;
|
538 |
|
|
assign Reg002E_6 = 1'b1;
|
539 |
|
|
assign Reg002E_5 = 1'b0;
|
540 |
|
|
|
541 |
|
|
assign Reg002E_3 = 1'b1;
|
542 |
|
|
assign Reg002E_2 = 1'b1;
|
543 |
|
|
assign Reg002E_1 = 1'b1;
|
544 |
|
|
assign Reg002E_0 = 1'b0;
|
545 |
|
|
// Reg002E is always CE | DE
|
546 |
|
|
|
547 |
|
|
//////- =======================================
|
548 |
|
|
assign cRgWr = ATV & ScWr1 & ~(ScWr) & cRgWrEnb; // old time is 1, new is off
|
549 |
|
|
assign cRgRd2E = ATV & ScRd1 & ~(ScRd) & bcRd2E; // the single read pulse for 2E
|
550 |
|
|
//////- =============== control the direction of the buffers ============
|
551 |
|
|
assign OE245 = ~(ATV); // almost always valid
|
552 |
|
|
assign DR245 = ~(IDE_Rd_Env | iD_245_In); // high = 3V3 bus drives disk I/O, = iWR |
|
553 |
|
|
//- low when ( iRd for MDMA and normal, or iDK AND UDI mode)
|
554 |
|
|
////- ===================================================================
|
555 |
|
|
always @(posedge bcWr) begin
|
556 |
|
|
cRgWrEnb <= Combo_CS & ScWr & ScWr1; // if selecting the register, then we might have write pulse
|
557 |
|
|
cRgA[6:0] <= cAi[6:0];
|
558 |
|
|
cRgD[7:0] <= cDi[7:0];
|
559 |
|
|
end
|
560 |
|
|
|
561 |
|
|
always @(posedge bcRd) begin
|
562 |
|
|
bcRd2E <= Combo_CS & ScRd & ScRd1 & ~(cAi[6]) & cAi[5] & ~(cAi[4]) & cAi[3] & cAi[2] & cAi[1] & ~(cAi[0]);
|
563 |
|
|
end
|
564 |
|
|
|
565 |
|
|
//// =============================
|
566 |
|
|
//always @(negedge CLK1) begin
|
567 |
|
|
// DMARAMD[15:0] <= cDi[15:0]; // lower word to RAM
|
568 |
|
|
// DMARAMD[31:16] <= cAi[15:0]; // upper word to RAM
|
569 |
|
|
//end
|
570 |
|
|
always @(posedge CLK4) begin
|
571 |
|
|
if ((Ph1 ^ Ph2) == 1'b1) begin
|
572 |
|
|
DMARAMD[15:0] <= cDi[15:0]; // lower word to RAM
|
573 |
|
|
DMARAMD[31:16] <= cAi[15:0]; // upper word to RAM
|
574 |
|
|
end
|
575 |
|
|
end
|
576 |
|
|
//// =============================
|
577 |
|
|
always @(posedge CLK1) begin
|
578 |
|
|
DWrite <= cWr & cDK;
|
579 |
|
|
end
|
580 |
|
|
|
581 |
|
|
//// ============================================================================================
|
582 |
|
|
//// ===== IDE bus interface wait engine ========================================================
|
583 |
|
|
//// ============================================================================================
|
584 |
|
|
assign bcWait = (IDE_CS == 1'b1) ? ~cWait : 1'bZ; // will output low if cWait = '1'
|
585 |
|
|
|
586 |
|
|
always @(posedge CLK4) begin
|
587 |
|
|
if (IDE_CS == 1'b0) begin
|
588 |
|
|
cWaitCnt <= 4'b0000; // clear wait counter
|
589 |
|
|
cWait <= 1'b1; // must wait
|
590 |
|
|
IgnoreIRdyPin <= ~SiRdy2; // if IORDY is always low then ignore it, it will not affect our engine
|
591 |
|
|
end else begin
|
592 |
|
|
if (cWaitCnt == 4'b1010) begin
|
593 |
|
|
// if ((SiRdy2 == 1'b1) && (BusMatch == 1'b1)) begin
|
594 |
|
|
if ((IgnoreIRdyPin == 1'b1) || (SiRdy2 == 1'b1)) begin
|
595 |
|
|
cWait <= 1'b0; // end if
|
596 |
|
|
end
|
597 |
|
|
end else begin
|
598 |
|
|
cWaitCnt <= cWaitCnt + 1;
|
599 |
|
|
end
|
600 |
|
|
end
|
601 |
|
|
end
|
602 |
|
|
//// ============================================================================================
|
603 |
|
|
//// ============================================================================================
|
604 |
|
|
|
605 |
|
|
always @(posedge CLK4) begin
|
606 |
|
|
//// synchronous Reset section
|
607 |
|
|
if (bHardReset == 1'b0) begin
|
608 |
|
|
////
|
609 |
|
|
Reg002A <= 8'h00;
|
610 |
|
|
Reg002E_4 <= 1'b0; // first data is CE, next data can be CE or DE
|
611 |
|
|
Rd2ECnt <= 6'b000001; // clear the Rd2E counter
|
612 |
|
|
Reg0064 <= 8'h80; // activate the IDE reset signal
|
613 |
|
|
DMA_IrqMask <= 1'b0;
|
614 |
|
|
DMA_IrqFF <= 1'b0; // clear the DMA request flipflop
|
615 |
|
|
PS2WrIDE <= 1'b0; // set up the direction
|
616 |
|
|
MDO[2] <= 1'b0; // DMA mode is multiword mode 0
|
617 |
|
|
MDO[1] <= 1'b0;
|
618 |
|
|
UDO <= 3'b000; // not UDMA mode
|
619 |
|
|
DMARMC <= 1'b0;
|
620 |
|
|
DMA_ARM <= 1'b0;
|
621 |
|
|
////--- first filter
|
622 |
|
|
iDQ1 <= 1'b0;
|
623 |
|
|
iIRQ1 <= 1'b0;
|
624 |
|
|
cWr1 <= 1'b0;
|
625 |
|
|
cRd1 <= 1'b0;
|
626 |
|
|
SiRdy1 <= 1'b1;
|
627 |
|
|
//// ======== 2nd filter ========
|
628 |
|
|
SiDQ <= 1'b0;
|
629 |
|
|
SiIRQ <= 1'b0;
|
630 |
|
|
ScWr <= 1'b0;
|
631 |
|
|
ScRd <= 1'b0;
|
632 |
|
|
SiRdy2 <= 1'b1;
|
633 |
|
|
//// ========= 3rd filter ======
|
634 |
|
|
ScRd1 <= 1'b0;
|
635 |
|
|
ScWr1 <= 1'b0;
|
636 |
|
|
//// =============================
|
637 |
|
|
ATV1 <= 1'b0;
|
638 |
|
|
ATV2 <= 1'b0;
|
639 |
|
|
ATV <= 1'b0;
|
640 |
|
|
//// =========
|
641 |
|
|
// DNAS0 <= 1'b0;
|
642 |
|
|
// DNAS1 <= 1'b0;
|
643 |
|
|
end else begin
|
644 |
|
|
ATV1 <= 1'b1;
|
645 |
|
|
ATV2 <= ATV1;
|
646 |
|
|
ATV <= ATV2; // 2 filter for ATV signal
|
647 |
|
|
//// ======== first filter =====
|
648 |
|
|
iDQ1 <= iDQ; // try to synchronize the system clock
|
649 |
|
|
iIRQ1 <= iIRQ; // synchronize again
|
650 |
|
|
cWr1 <= cWr;
|
651 |
|
|
cRd1 <= cRd;
|
652 |
|
|
SiRdy1 <= iRdy;
|
653 |
|
|
DIn1 <= iDi; // get the data
|
654 |
|
|
// IDERd1 <= IDERd; // one delay signal to control output buffer direction
|
655 |
|
|
//// ======== 2nd filter ========
|
656 |
|
|
SiDQ <= iDQ1;
|
657 |
|
|
SiIRQ <= iIRQ1;
|
658 |
|
|
ScWr <= cWr1;
|
659 |
|
|
ScRd <= cRd1;
|
660 |
|
|
SiRdy2 <= SiRdy1;
|
661 |
|
|
if (IDE_DSTB == 1'b1) DIn2 <= DIn1;
|
662 |
|
|
//// ========= 3rd filter ======
|
663 |
|
|
ScRd1 <= ScRd;
|
664 |
|
|
ScWr1 <= ScWr;
|
665 |
|
|
//// =============================
|
666 |
|
|
// The DNA output counter value
|
667 |
|
|
// if (((ScRd1 == 1'b1) && (ScRd == 1'b0)) || ((ScWr1 == 1'b1) && (ScWr == 1'b0))) begin
|
668 |
|
|
// DNAS0 <= ~DNAS0;
|
669 |
|
|
// DNAS1 <= DNAS1 ^ DNAS0;
|
670 |
|
|
// end
|
671 |
|
|
// Reg2815 <= PS2WrIDE & (PA_AlmostFull | (~(PA_HvSpace) & Reg2815));
|
672 |
|
|
//// =======================================
|
673 |
|
|
if (cRgRd2E == 1'b1) begin // read pulse post processing, check which register is read
|
674 |
|
|
if ((Rd2ECnt == 6'b000110) || (Rd2ECnt == 6'b010010) || (Rd2ECnt == 6'b010011) || (Rd2ECnt == 6'b010101) ||
|
675 |
|
|
(Rd2ECnt == 6'b010111) || (Rd2ECnt == 6'b011100) || (Rd2ECnt == 6'b011101) || (Rd2ECnt == 6'b011110) ||
|
676 |
|
|
(Rd2ECnt == 6'b011111) || (Rd2ECnt == 6'b100000) || (Rd2ECnt == 6'b100011) || (Rd2ECnt == 6'b100100) ||
|
677 |
|
|
(Rd2ECnt == 6'b100101) || (Rd2ECnt == 6'b100110) || (Rd2ECnt == 6'b100111) || (Rd2ECnt == 6'b101000) ||
|
678 |
|
|
(Rd2ECnt == 6'b101001) || (Rd2ECnt == 6'b101110) || (Rd2ECnt == 6'b110000) || (Rd2ECnt == 6'b110001) ||
|
679 |
|
|
(Rd2ECnt == 6'b110011) || (Rd2ECnt == 6'b110101) || (Rd2ECnt == 6'b110110) || (Rd2ECnt == 6'b111000) ||
|
680 |
|
|
(Rd2ECnt == 6'b111001) || (Rd2ECnt == 6'b111011) || (Rd2ECnt == 6'b111110))
|
681 |
|
|
begin
|
682 |
|
|
Reg002E_4 <= 1'b1; // Reg002E <= x"DE";
|
683 |
|
|
end else begin
|
684 |
|
|
Reg002E_4 <= 1'b0; // Reg002E <= x"CE";
|
685 |
|
|
end
|
686 |
|
|
Rd2ECnt <= Rd2ECnt + 1;
|
687 |
|
|
end
|
688 |
|
|
////- ==============================
|
689 |
|
|
if (cRgWr == 1'b0) begin
|
690 |
|
|
//// Always running section the DMA controller reset section ////
|
691 |
|
|
DMARMC <= ATV; // DMA_ARM is two clock width
|
692 |
|
|
DMA_ARM <= DMARMC; // DMA_ARM is two clock width, put to clear register
|
693 |
|
|
//// The interrupt controller section always running after hard reset////
|
694 |
|
|
if (DMA_IrqMask == 1'b1) begin
|
695 |
|
|
DMA_IrqMask <= DMA_IrqCond; // only interrupt once until the condition is remove
|
696 |
|
|
end
|
697 |
|
|
if ((DMA_IrqCond == 1'b1) && (DMA_IrqMask == 1'b0)) begin
|
698 |
|
|
DMA_IrqMask <= DMA_IrqCTRL; // no more retrigger
|
699 |
|
|
DMA_IrqFF <= DMA_IrqCTRL; // the DMA interrupt request pulse from DMA/IDE unit
|
700 |
|
|
end
|
701 |
|
|
end else begin // only one write pulse
|
702 |
|
|
//// 002A
|
703 |
|
|
case (cRgA[6:0])
|
704 |
|
|
7'b0101010: begin // 002A
|
705 |
|
|
Reg002A[7:0] <= cRgD[7:0];
|
706 |
|
|
if (cRgD[7:0] == 8'h00) DMA_IrqFF <= 1'b0; // clear the DMA_IrqFF
|
707 |
|
|
end
|
708 |
|
|
//// 002C
|
709 |
|
|
7'b0101100: begin // 002C
|
710 |
|
|
if (cRgD == 8'hE1) begin
|
711 |
|
|
Rd2ECnt <= 6'b00_0001; // start up the counter
|
712 |
|
|
// Reg002C[7:0] <= cRgD[7:0];
|
713 |
|
|
end
|
714 |
|
|
end
|
715 |
|
|
//// 0032
|
716 |
|
|
7'b0110010: begin // 0032
|
717 |
|
|
DMARMC <= 1'b0;
|
718 |
|
|
DMA_ARM <= 1'b0; //// clear the ARM signal
|
719 |
|
|
DMA_IrqFF <= 1'b0; // clear all possible old DMA interrupt
|
720 |
|
|
Reg0064[2] <= 1'b0;
|
721 |
|
|
PS2WrIDE <= cRgD[0]; // set the direction
|
722 |
|
|
end
|
723 |
|
|
//// 0038
|
724 |
|
|
// if (cRgA[6:0]= "0111000") begin // 0038
|
725 |
|
|
// if (cRgD = X"03") begin
|
726 |
|
|
// DMA_ARM <= 1'b0;
|
727 |
|
|
// end if;
|
728 |
|
|
// end if;
|
729 |
|
|
//// 0042
|
730 |
|
|
7'b1000010: begin // 0042
|
731 |
|
|
R42Is03 <= ~(cRgD[7] | cRgD[6] | cRgD[5] | cRgD[4] | cRgD[3] | cRgD[2]) & cRgD[1] & cRgD[0];
|
732 |
|
|
end
|
733 |
|
|
//// 0044
|
734 |
|
|
7'b1000100: begin // 0044
|
735 |
|
|
R44Is2X <= ~(cRgD[7] | cRgD[6] | cRgD[4] | cRgD[3]) & cRgD[5];
|
736 |
|
|
R44Is4X <= ~(cRgD[7] | cRgD[5] | cRgD[4] | cRgD[3]) & cRgD[6];
|
737 |
|
|
R44[2] <= cRgD[2];
|
738 |
|
|
R44[1] <= cRgD[1];
|
739 |
|
|
R44[0] <= cRgD[0];
|
740 |
|
|
end
|
741 |
|
|
//// 004E
|
742 |
|
|
7'b1001110: begin // 004E
|
743 |
|
|
UDO[2] <= (D_UnChg & UDO[2]) | (~(D_UnChg) & UDMA_SEL & R44[2]);
|
744 |
|
|
UDO[1] <= (D_UnChg & UDO[1]) | (~(D_UnChg) & UDMA_SEL & R44[1]);
|
745 |
|
|
UDO[0] <= (D_UnChg & UDO[0]) | (~(D_UnChg) & UDMA_SEL & R44[0]);
|
746 |
|
|
MDO[2] <= (D_UnChg & MDO[2]) | (~(D_UnChg) & MDMA_SEL & R44[2]);
|
747 |
|
|
MDO[1] <= (D_UnChg & MDO[1]) | (~(D_UnChg) & MDMA_SEL & R44[1]);
|
748 |
|
|
end
|
749 |
|
|
//// 0064
|
750 |
|
|
7'b1100100: begin // 0064
|
751 |
|
|
Reg0064[7:0] <= cRgD[7:0];
|
752 |
|
|
end
|
753 |
|
|
endcase
|
754 |
|
|
end // Write Pulse group
|
755 |
|
|
end // bcRST group
|
756 |
|
|
end // clock
|
757 |
|
|
endmodule
|