OpenCores
URL https://opencores.org/ocsvn/dallas_one-wire/dallas_one-wire/trunk

Subversion Repositories dallas_one-wire

[/] [dallas_one-wire/] [tags/] [arelease/] [one_wire.vhd] - Blame information for rev 4

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 bretthowar 
library ieee;
2 
use ieee.std_logic_1164.all;
3 
use ieee.numeric_unsigned.all;
4 
 
5 
entity one_wire is
6 
        port (
7 
                        clk, reset, read, write         : IN std_logic;
8 
                        DQ                                              : INOUT std_logic;
9 
                        rddata                                  : OUT std_logic_vector(7 downto 0);
10 
                        wrdata                                  : IN std_logic_vector(7 downto 0);
11 
                        ready                                   : INOUT std_logic
12 
                );
13 
end entity one_wire;
14 
 
15 
architecture structural of one_wire is
16 
        signal iCount : integer range 0 to 500;
17 
        signal iCntRst : bit;
18 
        signal iD : std_logic;
19 
begin
20 
 
21 
        --This counter is used in the state machine to count micro seconds
22 
        --it is assumed that the clock edges are coming in at 1uS intervals
23 
        counter: process
24 
        begin
25 
                wait until (clk'event and clk = '0');
26 
                        if(iCntRst = '1') then
27 
                                iCount <= 0;
28 
                        else
29 
                                iCount <= iCount + 1;
30 
                        end if;
31 
        end process counter;
32 
 
33 
        init_statemachine : block
34 
 
35 
        type states is (init1, init2, init3, rdy, begin_read, begin_write, rd_bit, finish_read, wr_bit);
36 
        signal state : states;
37 
        begin
38 
                nxt_state_decoder: process(state, clk)
39 
                        variable next_state : states;
40 
                        variable iBits : integer range 0 to 8;
41 
                begin
42 
                if clk 'event and clk = '1' then
43 
                        case (state) is
44 
                                when INIT1 =>
45 
                                        iCntRst <= '0';
46 
                                        iD <= '0';
47 
                                        ready <= '0';
48 
                                        if (iCount = 500) then
49 
                                                next_state := INIT2;
50 
                                                iCntRst <= '1';         --stop the timer
51 
                                        else
52 
                                                next_state := INIT1;
53 
                                        end if;
54 
                                when INIT2 =>
55 
                                        iCntRst <= '0';                  --start the timer
56 
                                        iD <= '1';
57 
                                        ready <= '0';
58 
                                        if (iCount = 15) then
59 
                                                next_state := INIT3;
60 
                                                iCntRst <= '1';         --stop the timer
61 
                                        else
62 
                                                next_state := INIT2;
63 
                                        end if;
64 
                                when INIT3 =>
65 
                                        iCntRst <= '0';                  --start the timer (not needed)
66 
                                        ready <= '0';
67 
                                        if (DQ = '0') then
68 
                                                next_state := RDY;
69 
                                                iCntRst <= '1';         --stop the timer (not needed)
70 
                                        else
71 
                                                next_state := INIT3;
72 
                                        end if;
73 
                                when RDY =>
74 
                                        iCntRst <= '0';          --start the timer
75 
                                        iBits := 0;
76 
                                        iD <= '1';
77 
                                        if(iCount >= 240 and ready = '0') then
78 
                                                ready <= '1';
79 
                                        end if;
80 
                                        if(Read = '1' and iCount >= 240) then
81 
                                                ready <= '0';
82 
                                                iCntRst <= '1';                 --stop timer
83 
                                                next_state := BEGIN_READ;
84 
                                        elsif(Write = '1' and iCount >= 240) then
85 
                                                ready <= '0';
86 
                                                iCntRst <= '1';                 --stop timer
87 
                                                next_state := BEGIN_WRITE;
88 
                                        else
89 
                                                next_state := RDY;
90 
                                        end if;
91 
                                when BEGIN_READ =>
92 
                                        iCntRst <= '0';          --start timer
93 
                                        iD <= '0';
94 
                                        if (iCount = 2) then                                                    --this number used to be a 5
95 
                                                iCntRst <= '1';         --stop timer
96 
                                                next_state := RD_BIT;
97 
                                        end if;
98 
                                when RD_BIT =>
99 
                                        iD <= '1';
100 
                                        iCntRst <= '0'; --start timer
101 
 
102 
                                        case ibits is
103 
                                                when 0 =>
104 
                                                        rddata(0) <= DQ;
105 
                                                when 1 =>
106 
                                                        rddata(1) <= DQ;
107 
                                                when 2 =>
108 
                                                        rddata(2) <= DQ;
109 
                                                when 3 =>
110 
                                                        rddata(3) <= DQ;
111 
                                                when 4 =>
112 
                                                        rddata(4) <= DQ;
113 
                                                when 5 =>
114 
                                                        rddata(5) <= DQ;
115 
                                                when 6 =>
116 
                                                        rddata(6) <= DQ;
117 
                                                when 7 =>
118 
                                                        rddata(7) <= DQ;
119 
                                                when others =>
120 
                                        end case;
121 
                                                if(iCount >= 6) then
122 
                                                        next_state := FINISH_READ;
123 
                                                end if;
124 
                                when FINISH_READ =>
125 
                                        if(iBits <= 6 and iCount >= 55) then            --this second number used to be 55
126 
                                                iD <= '1';
127 
                                                iBits := iBits + 1;
128 
                                                iCntRst <= '1'; --stop timer
129 
                                                next_state := BEGIN_READ;
130 
                                        elsif(iBits = 7) then
131 
                                                iCntRst <= '1'; -- stop timer
132 
                                                next_state := RDY;
133 
                                        end if;
134 
                                when BEGIN_WRITE =>
135 
                                        iCntRst <= '0';
136 
                                        if(iBits <= 7) then
137 
                                                iD <= '0';                                       --start timer
138 
                                        end if;
139 
                                        if (iCount = 1) then
140 
                                                iCntRst <= '1';  --stop timer
141 
                                                next_state := WR_BIT;
142 
                                        end if;
143 
                                when WR_BIT =>
144 
                                        iCntRst <= '0';
145 
 
146 
                                        --The below code is what is being accomplished by the huge if elseif structure
147 
                                        --if(data(iBits) = "001") then
148 
                                        --      iD := '1';
149 
                                        --end if;
150 
 
151 
                                        if(iBits = 0 and wrdata(0) = '1') then
152 
                                                iD <= '1';
153 
                                        elsif(iBIts = 0 and wrdata(0) = '0') then
154 
                                                iD <= '0';
155 
                                        elsif(iBits = 1 and wrdata(1) = '1') then
156 
                                                iD <= '1';
157 
                                        elsif(iBIts = 1 and wrdata(1) = '0') then
158 
                                                iD <= '0';
159 
                                        elsif(iBits = 2 and wrdata(2) = '1') then
160 
                                                iD <= '1';
161 
                                        elsif(iBIts = 2 and wrdata(2) = '0') then
162 
                                                iD <= '0';
163 
                                        elsif(iBits = 3 and wrdata(3) = '1') then
164 
                                                iD <= '1';
165 
                                        elsif(iBIts = 3 and wrdata(3) = '0') then
166 
                                                iD <= '0';
167 
                                        elsif(iBits = 4 and wrdata(4) = '1') then
168 
                                                iD <= '1';
169 
                                        elsif(iBIts = 4 and wrdata(4) = '0') then
170 
                                                iD <= '0';
171 
                                        elsif(iBits = 5 and wrdata(5) = '1') then
172 
                                                iD <= '1';
173 
                                        elsif(iBIts = 5 and wrdata(5) = '0') then
174 
                                                iD <= '0';
175 
                                        elsif(iBits = 6 and wrdata(6) = '1') then
176 
                                                iD <= '1';
177 
                                        elsif(iBIts = 6 and wrdata(6) = '0') then
178 
                                                iD <= '0';
179 
                                        elsif(iBits = 7 and wrdata(7) = '1') then
180 
                                                iD <= '1';
181 
                                        elsif(iBIts = 7 and wrdata(7) = '0') then
182 
                                                iD <= '0';
183 
                                        end if;
184 
                                        if(iCount >= 60 and iBits <= 7) then
185 
                                                iBits := iBits + 1;
186 
                                                iD <= '1';
187 
                                                iCntRst <= '1'; --stop timer
188 
                                                next_state := BEGIN_WRITE;
189 
                                        elsif(iBits = 8) then
190 
                                                iD <= '1';
191 
                                                iCntRst <= '1'; --stop timer
192 
                                                next_state := RDY;
193 
                                        end if;
194 
                        end case;
195 
 
196 
                        state <= next_state;
197 
                        if(reset = '1') then
198 
                                state <= init1;
199 
                        end if;
200 
                end if;
201 
 
202 
                end process nxt_state_decoder;
203 
        end block init_statemachine;
204 
 
205 
        trictrl: process(iD)
206 
        begin
207 
                if( iD = '0' ) then
208 
                        DQ <= '0';
209 
                else
210 
                        DQ <= 'Z';
211 
                end if;
212 
        end process trictrl;
213 
 
214 
end architecture structural;
215 
 
216 
PACKAGE PROTOCOL_PKG IS
217 
                COMPONENT one_wire
218 
                END COMPONENT;
219 
END PROTOCOL_PKG;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.