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marcelos |
/* Copyright (c) 2018, Marcelo Samsoniuk
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* * Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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Memory Architectures:
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- Harvard: separate instruction (ROM) and data (RAM), has the
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advantage that is possible make the ROM memory readonly, in a way
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that bugs in the code cannot destruct the code. Also, the use of
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separate ROM and RAM makes possible share the dual-port ROM and/or
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RAM between two cores.
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- Von Neumann: unified instruction and data in a single memory
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(MEM), has the advantage that the .text and .data are contigous
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and without gaps, which means that the memory is better utilized.
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However, as long there is no physical separation, a bug in the
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code can destroy both data and code. Also, as long both ports of
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the dual-port MEM is already in use, there is no way to share to
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more than one core.
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*/
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MEMORY
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{
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IO (rw!x) : ORIGIN = 0x80000000, LENGTH = 0x10
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#if HARVARD
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ROM (x!rw) : ORIGIN = 0x00000000, LENGTH = 0x1000
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RAM (rw!x) : ORIGIN = 0x00001000, LENGTH = 0x1000
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#else
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MEM (rwx) : ORIGIN = 0x00000000, LENGTH = 0x2000
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#endif
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}
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SECTIONS
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{
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.io :
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{
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io.o(COMMON)
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} > IO
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.text :
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{
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boot.o(.text)
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*(.text)
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#if HARVARD
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} > ROM
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#else
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} > MEM
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#endif
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.data :
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{
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*(.sbss)
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*(.rodata*)
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*(.data)
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*(.bss)
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*(.rela*)
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*(COMMON)
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#if HARVARD
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} > RAM
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#else
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} > MEM
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#endif
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}
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