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[/] [datetime/] [trunk/] [rtl/] [verilog/] [sync2s.v] - Blame information for rev 2

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// two stage synchronizer
 
module sync2s(rst, clk, i, o);
        input rst;
        input clk;
        input i;
        output o;
 
        reg [1:0] s;
        always @(posedge clk)
                if (rst)
                        s <= 0;
                else
                        s <= {s[0],i};
 
        assign o = s[1];
 
endmodule

Line No.	Rev	Author	Line
1	2	robfinch	`// two stage synchronizer`
2
3			`module sync2s(rst, clk, i, o);`
4			`input rst;`
5			`input clk;`
6			`input i;`
7			`output o;`
8
9			`reg [1:0] s;`
10			`always @(posedge clk)`
11			`if (rst)`
12			`s <= 0;`
13			`else`
14			`s <= {s[0],i};`
15
16			`assign o = s[1];`
17
18			`endmodule`

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[/] [datetime/] [trunk/] [rtl/] [verilog/] [sync2s.v] - Blame information for rev 2