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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_cpu_registers.v                                         ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2004 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2004/01/17 17:01:14  mohor
// Almost finished.
//
// Revision 1.1  2004/01/16 14:53:33  mohor
// *** empty log message ***
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "dbg_cpu_defines.v"
 
module dbg_cpu_registers  (
                            data_i,
                            data_o,
                            addr_i,
                            we_i,
                            en_i,
                            clk_i,
                            bp_i,
                            rst_i,
                            cpu_clk_i,
                            cpu_stall_o,
                            cpu_stall_all_o,
                            cpu_sel_o,
                            cpu_rst_o
                          );
 
 
input            [7:0]  data_i;
input            [1:0]  addr_i;
 
input                   we_i;
input                   en_i;
input                   clk_i;
input                   bp_i;
input                   rst_i;
input                   cpu_clk_i;
 
output           [7:0]  data_o;
reg              [7:0]  data_o;
 
output                  cpu_stall_o;
output                  cpu_stall_all_o;
output [`CPU_NUM -1:0]  cpu_sel_o;
output                  cpu_rst_o;
 
wire                    cpu_stall_all;
wire                    cpu_reset;
wire             [2:1]  cpu_op_out;
wire   [`CPU_NUM -1:0]  cpu_sel_out;
 
wire                    cpuop_wr;
wire                    cpusel_wr;
 
reg                     cpusel_wr_sync, cpusel_wr_cpu;
reg                     stall_bp, stall_bp_sync, stall_bp_tck;
reg                     stall_reg, stall_reg_sync, stall_reg_cpu;
reg                     cpu_stall_all_sync;
reg                     cpu_stall_all_o;
reg                     cpu_reset_sync;
reg                     cpu_rst_o;
 
 
 
assign cpuop_wr      = en_i & we_i & (addr_i == `CPU_OP_ADR);
assign cpusel_wr     = en_i & we_i & (addr_i == `CPU_SEL_ADR);
 
 
// Synchronising we for cpu_sel register that works in cpu_clk clock domain
always @ (posedge cpu_clk_i or posedge rst_i)
begin
  if (rst_i)
    begin
      cpusel_wr_sync <= #1 1'b0;
      cpusel_wr_cpu  <= #1 1'b0;
    end
  else
    begin
      cpusel_wr_sync <= #1 cpusel_wr;
      cpusel_wr_cpu  <= #1 cpusel_wr_sync;
    end
end
 
 
// Breakpoint is latched and synchronized. Stall is set and latched.
always @ (posedge cpu_clk_i or posedge rst_i)
begin
  if(rst_i)
    stall_bp <= #1 1'b0;
  else if(bp_i)
    stall_bp <= #1 1'b1;
  else if(stall_reg_cpu)
    stall_bp <= #1 1'b0;
end
 
 
// Synchronizing
always @ (posedge clk_i or posedge rst_i)
begin
  if (rst_i)
    begin
      stall_bp_sync <= #1 1'b0;
      stall_bp_tck  <= #1 1'b0;
    end
  else
    begin
      stall_bp_sync <= #1 stall_bp;
      stall_bp_tck  <= #1 stall_bp_sync;
    end
end
 
 
always @ (posedge clk_i or posedge rst_i)
begin
  if (rst_i)
    stall_reg <= #1 1'b0;
  else if (stall_bp_tck)
    stall_reg <= #1 1'b1;
  else if (cpuop_wr)
    stall_reg <= #1 data_i[0];
end
 
 
always @ (posedge cpu_clk_i or posedge rst_i)
begin
  if (rst_i)
    begin
      stall_reg_sync <= #1 1'b0;
      stall_reg_cpu  <= #1 1'b0;
    end
  else
    begin
      stall_reg_sync <= #1 stall_reg;
      stall_reg_cpu  <= #1 stall_reg_sync;
    end
end
 
 
assign cpu_stall_o = bp_i | stall_bp | stall_reg_cpu;
 
 
 
dbg_register #(2, 0)          CPUOP  (.data_in(data_i[2:1]),           .data_out(cpu_op_out[2:1]), .write(cpuop_wr),       .clk(clk_i),     .reset(rst_i));
dbg_register #(`CPU_NUM, 0)   CPUSEL (.data_in(data_i[`CPU_NUM-1:0]),  .data_out(cpu_sel_out),     .write(cpusel_wr_cpu),  .clk(cpu_clk_i), .reset(rst_i)); // cpu_cli_i
 
 
always @ (posedge clk_i)
begin
  case (addr_i)         // Synthesis parallel_case
    `CPU_OP_ADR  : data_o <= #1 {5'h0, cpu_op_out[2:1], stall_reg};
    `CPU_SEL_ADR : data_o <= #1 {{(8-`CPU_NUM){1'b0}}, cpu_sel_out};
    default      : data_o <= #1 8'h0;
  endcase
end
 
 
assign cpu_stall_all      = cpu_op_out[2];       // this signal is used to stall all the cpus except the one that is selected in cpusel register
assign cpu_sel_o          = cpu_sel_out;
assign cpu_reset          = cpu_op_out[1];
 
 
 
 
// Synchronizing signals from registers
always @ (posedge cpu_clk_i or posedge rst_i)
begin
  if (rst_i)
    begin
      cpu_stall_all_sync  <= #1 1'b0;
      cpu_stall_all_o     <= #1 1'b0;
      cpu_reset_sync      <= #1 1'b0;
      cpu_rst_o           <= #1 1'b0;
    end
  else
    begin
      cpu_stall_all_sync  <= #1 cpu_stall_all;
      cpu_stall_all_o     <= #1 cpu_stall_all_sync;
      cpu_reset_sync      <= #1 cpu_reset;
      cpu_rst_o           <= #1 cpu_reset_sync;
    end
end
 
 
 
endmodule
 

Line No.	Rev	Author	Line
1	100	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_cpu_registers.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7			`//// http://www.opencores.org/projects/DebugInterface/ ////`
8			`//// ////`
9			`//// Author(s): ////`
10			`//// Igor Mohor (igorm@opencores.org) ////`
11			`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the README.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 - 2004 Authors ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46	119	mohor	`// Revision 1.2 2004/01/17 17:01:14 mohor`
47			`// Almost finished.`
48			`//`
49	101	mohor	`// Revision 1.1 2004/01/16 14:53:33 mohor`
50			`// * empty log message *`
51	100	mohor	`//`
52			`//`
53	101	mohor	`//`
54	100	mohor
55			`// synopsys translate_off`
56			`include "timescale.v"
57			`// synopsys translate_on`
58			`include "dbg_cpu_defines.v"
59
60			`module dbg_cpu_registers (`
61	101	mohor	`data_i,`
62			`data_o,`
63			`addr_i,`
64			`we_i,`
65			`en_i,`
66			`clk_i,`
67			`bp_i,`
68			`rst_i,`
69			`cpu_clk_i,`
70			`cpu_stall_o,`
71			`cpu_stall_all_o,`
72			`cpu_sel_o,`
73			`cpu_rst_o`
74	100	mohor	`);`
75
76
77	101	mohor	`input [7:0] data_i;`
78			`input [1:0] addr_i;`
79	100	mohor
80	101	mohor	`input we_i;`
81			`input en_i;`
82			`input clk_i;`
83			`input bp_i;`
84			`input rst_i;`
85			`input cpu_clk_i;`
86	100	mohor
87	101	mohor	`output [7:0] data_o;`
88			`reg [7:0] data_o;`
89	100	mohor
90	101	mohor	`output cpu_stall_o;`
91			`output cpu_stall_all_o;`
92			output [`CPU_NUM -1:0] cpu_sel_o;
93			`output cpu_rst_o;`
94	100	mohor
95	101	mohor	`wire cpu_stall_all;`
96			`wire cpu_reset;`
97	100	mohor	`wire [2:1] cpu_op_out;`
98			wire [`CPU_NUM -1:0] cpu_sel_out;
99
100			`wire cpuop_wr;`
101			`wire cpusel_wr;`
102
103	119	mohor	`reg cpusel_wr_sync, cpusel_wr_cpu;`
104			`reg stall_bp, stall_bp_sync, stall_bp_tck;`
105			`reg stall_reg, stall_reg_sync, stall_reg_cpu;`
106	101	mohor	`reg cpu_stall_all_sync;`
107			`reg cpu_stall_all_o;`
108			`reg cpu_reset_sync;`
109			`reg cpu_rst_o;`
110	100	mohor
111
112
113	101	mohor	assign cpuop_wr = en_i & we_i & (addr_i == `CPU_OP_ADR);
114			assign cpusel_wr = en_i & we_i & (addr_i == `CPU_SEL_ADR);
115	100	mohor
116
117	101	mohor	`// Synchronising we for cpu_sel register that works in cpu_clk clock domain`
118	119	mohor	`always @ (posedge cpu_clk_i or posedge rst_i)`
119	100	mohor	`begin`
120	119	mohor	`if (rst_i)`
121			`begin`
122			`cpusel_wr_sync <= #1 1'b0;`
123			`cpusel_wr_cpu <= #1 1'b0;`
124			`end`
125			`else`
126			`begin`
127			`cpusel_wr_sync <= #1 cpusel_wr;`
128			`cpusel_wr_cpu <= #1 cpusel_wr_sync;`
129			`end`
130	101	mohor	`end`
131
132
133	119	mohor	`// Breakpoint is latched and synchronized. Stall is set and latched.`
134			`always @ (posedge cpu_clk_i or posedge rst_i)`
135	101	mohor	`begin`
136			`if(rst_i)`
137	119	mohor	`stall_bp <= #1 1'b0;`
138			`else if(bp_i)`
139			`stall_bp <= #1 1'b1;`
140			`else if(stall_reg_cpu)`
141			`stall_bp <= #1 1'b0;`
142	100	mohor	`end`
143
144
145	119	mohor	`// Synchronizing`
146			`always @ (posedge clk_i or posedge rst_i)`
147			`begin`
148			`if (rst_i)`
149			`begin`
150			`stall_bp_sync <= #1 1'b0;`
151			`stall_bp_tck <= #1 1'b0;`
152			`end`
153			`else`
154			`begin`
155			`stall_bp_sync <= #1 stall_bp;`
156			`stall_bp_tck <= #1 stall_bp_sync;`
157			`end`
158			`end`
159
160
161			`always @ (posedge clk_i or posedge rst_i)`
162			`begin`
163			`if (rst_i)`
164			`stall_reg <= #1 1'b0;`
165			`else if (stall_bp_tck)`
166			`stall_reg <= #1 1'b1;`
167			`else if (cpuop_wr)`
168			`stall_reg <= #1 data_i[0];`
169			`end`
170
171
172			`always @ (posedge cpu_clk_i or posedge rst_i)`
173			`begin`
174			`if (rst_i)`
175			`begin`
176			`stall_reg_sync <= #1 1'b0;`
177			`stall_reg_cpu <= #1 1'b0;`
178			`end`
179			`else`
180			`begin`
181			`stall_reg_sync <= #1 stall_reg;`
182			`stall_reg_cpu <= #1 stall_reg_sync;`
183			`end`
184			`end`
185
186
187			`assign cpu_stall_o = bp_i \| stall_bp \| stall_reg_cpu;`
188
189
190
191			`dbg_register #(2, 0) CPUOP (.data_in(data_i[2:1]), .data_out(cpu_op_out[2:1]), .write(cpuop_wr), .clk(clk_i), .reset(rst_i));`
192	101	mohor	dbg_register #(`CPU_NUM, 0) CPUSEL (.data_in(data_i[`CPU_NUM-1:0]), .data_out(cpu_sel_out), .write(cpusel_wr_cpu), .clk(cpu_clk_i), .reset(rst_i)); // cpu_cli_i
193	100	mohor
194
195	101	mohor	`always @ (posedge clk_i)`
196	100	mohor	`begin`
197	101	mohor	`case (addr_i) // Synthesis parallel_case`
198	119	mohor	`CPU_OP_ADR : data_o <= #1 {5'h0, cpu_op_out[2:1], stall_reg};
199	101	mohor	`CPU_SEL_ADR : data_o <= #1 {{(8-`CPU_NUM){1'b0}}, cpu_sel_out};
200			`default : data_o <= #1 8'h0;`
201	100	mohor	`endcase`
202			`end`
203
204
205			`assign cpu_stall_all = cpu_op_out[2]; // this signal is used to stall all the cpus except the one that is selected in cpusel register`
206	101	mohor	`assign cpu_sel_o = cpu_sel_out;`
207	100	mohor	`assign cpu_reset = cpu_op_out[1];`
208
209	101	mohor
210
211
212			`// Synchronizing signals from registers`
213	119	mohor	`always @ (posedge cpu_clk_i or posedge rst_i)`
214	101	mohor	`begin`
215	119	mohor	`if (rst_i)`
216			`begin`
217			`cpu_stall_all_sync <= #1 1'b0;`
218			`cpu_stall_all_o <= #1 1'b0;`
219			`cpu_reset_sync <= #1 1'b0;`
220			`cpu_rst_o <= #1 1'b0;`
221			`end`
222			`else`
223			`begin`
224			`cpu_stall_all_sync <= #1 cpu_stall_all;`
225			`cpu_stall_all_o <= #1 cpu_stall_all_sync;`
226			`cpu_reset_sync <= #1 cpu_reset;`
227			`cpu_rst_o <= #1 cpu_reset_sync;`
228			`end`
229	101	mohor	`end`
230
231
232
233	100	mohor	`endmodule`
234

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[/] [dbg_interface/] [tags/] [asyst_2/] [rtl/] [verilog/] [dbg_cpu_registers.v] - Blame information for rev 119