URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [asyst_2/] [rtl/] [verilog/] [dbg_wb.v] - Blame information for rev 91

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_wb.v                                                    ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2003 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7  2004/01/08 17:53:36  mohor
// tmp version.
//
// Revision 1.6  2004/01/07 11:58:56  mohor
// temp4 version.
//
// Revision 1.5  2004/01/06 17:15:19  mohor
// temp3 version.
//
// Revision 1.4  2004/01/05 12:16:00  mohor
// tmp2 version.
//
// Revision 1.3  2003/12/23 16:22:46  mohor
// Tmp version.
//
// Revision 1.2  2003/12/23 15:26:26  mohor
// Small fix.
//
// Revision 1.1  2003/12/23 15:09:04  mohor
// New directory structure. New version of the debug interface.
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "dbg_wb_defines.v"
 
// Top module
module dbg_wb(
                // JTAG signals
                trst_i,     // trst_i is active high (inverted on higher layers)
                tck_i,
                tdi_i,
                tdo_o,
 
                // TAP states
                shift_dr_i,
                pause_dr_i,
                update_dr_i,
 
                wishbone_ce_i,
                crc_match_i,
                crc_en_o,
                shift_crc_o,
 
                // WISHBONE common signals
                wb_rst_i, wb_clk_i,
 
                // WISHBONE master interface
                wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,
                wb_we_o, wb_ack_i, wb_cab_o, wb_err_i, wb_cti_o, wb_bte_o
 
              );
 
// JTAG signals
input   trst_i;
input   tck_i;
input   tdi_i;
output  tdo_o;
 
// TAP states
input   shift_dr_i;
input   pause_dr_i;
input   update_dr_i;
 
input   wishbone_ce_i;
input   crc_match_i;
output  crc_en_o;
output  shift_crc_o;
 
// WISHBONE common signals
input         wb_rst_i;                   // WISHBONE reset
input         wb_clk_i;                   // WISHBONE clock
 
// WISHBONE master interface
output [31:0] wb_adr_o;
output [31:0] wb_dat_o;
input  [31:0] wb_dat_i;
output        wb_cyc_o;
output        wb_stb_o;
output  [3:0] wb_sel_o;
output        wb_we_o;
input         wb_ack_i;
output        wb_cab_o;
input         wb_err_i;
output  [2:0] wb_cti_o;
output  [1:0] wb_bte_o;
 
reg           wb_cyc_o;
reg    [31:0] wb_adr_o;
reg    [31:0] wb_dat_o;
reg     [3:0] wb_sel_o;
 
reg           tdo_o;
 
reg    [50:0] dr;
wire          enable;
wire          cmd_cnt_en;
reg     [1:0] cmd_cnt;
wire          cmd_cnt_end;
reg           cmd_cnt_end_q;
wire          addr_len_cnt_en;
reg     [5:0] addr_len_cnt;
reg     [5:0] addr_len_cnt_limit;
wire          addr_len_cnt_end;
wire          crc_cnt_en;
reg     [5:0] crc_cnt;
wire          crc_cnt_end;
reg           crc_cnt_end_q;
wire          data_cnt_en;
reg    [18:0] data_cnt;
reg    [18:0] data_cnt_limit;
wire          data_cnt_end;
reg           data_cnt_end_q;
reg           status_reset_en;
 
reg           crc_match_reg;
 
reg [2:0]  cmd, cmd_old, dr_cmd_latched;
reg [31:0] adr;
reg [15:0] len;
reg start_rd_tck;
reg start_rd_sync1;
reg start_wb_rd;
reg start_wb_rd_q;
reg start_wr_tck;
reg start_wr_sync1;
reg start_wb_wr;
reg start_wb_wr_q;
 
reg dr_write_latched;
reg dr_read_latched;
reg dr_go_latched;
 
wire status_cnt_end;
 
wire byte, half, long;
reg  byte_q, half_q, long_q;
reg  cmd_read;
reg  cmd_write;
reg  cmd_go;
reg  cmd_old_read;
 
reg  status_cnt1, status_cnt2, status_cnt3, status_cnt4;
 
 
assign enable = wishbone_ce_i & shift_dr_i;
assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);
assign shift_crc_o = enable & status_cnt_end;  // Signals dbg module to shift out the CRC
 
 
//always @ (posedge tck_i)
//begin
//  if (enable & ((~addr_len_cnt_end) | (~cmd_cnt_end) | (~data_cnt_end)))
//    dr <= #1 {dr[49:0], tdi_i};
//end
 
 
always @ (posedge tck_i)
begin
/*  if (cmd_old_read & cmd_go)
    begin
      case (cmd_old)  // synthesis parallel_case full_case
        `WB_READ8 : begin
                      if(byte & (~byte_q))
                        dr[31:24] <= #1 input_data[];
                      else
                        dr <= #1 dr<<1;
                    end
        `WB_READ16: begin
                      if(half & (~half_q))
                        start_rd_tck <= #1 1'b1;
                      else
                        start_rd_tck <= #1 1'b0;
                    end
        `WB_READ32: begin
                      if(long & (~long_q))
                        start_rd_tck <= #1 1'b1;
                      else
                        start_rd_tck <= #1 1'b0;
                    end
      endcase
    end
  else*/ if (enable & ((~addr_len_cnt_end) | (~cmd_cnt_end) | (~data_cnt_end)))
    dr <= #1 {dr[49:0], tdi_i};
end
 
 
assign cmd_cnt_en = enable & (~cmd_cnt_end);
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    cmd_cnt <= #1 'h0;
  else if (update_dr_i)
    cmd_cnt <= #1 'h0;
  else if (cmd_cnt_en)
    cmd_cnt <= #1 cmd_cnt + 1'b1;
end
 
 
assign addr_len_cnt_en = enable & cmd_cnt_end & (~addr_len_cnt_end);
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    addr_len_cnt <= #1 'h0;
  else if (update_dr_i)
    addr_len_cnt <= #1 'h0;
  else if (addr_len_cnt_en)
    addr_len_cnt <= #1 addr_len_cnt + 1'b1;
end
 
 
assign data_cnt_en = enable & cmd_cnt_end & (~data_cnt_end);
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    data_cnt <= #1 'h0;
  else if (update_dr_i)
    data_cnt <= #1 'h0;
  else if (data_cnt_en)
    data_cnt <= #1 data_cnt + 1'b1;
end
 
 
 
assign byte = data_cnt[2:0] == 3'h0;
assign half = data_cnt[3:0] == 4'h0;
assign long = data_cnt[4:0] == 5'h0;
 
 
always @ (posedge tck_i)
begin
  byte_q <= #1 byte;
  half_q <= #1 half;
  long_q <= #1 long;
end
 
 
 
//assign cmd_read = (cmd == `WB_READ8) | (cmd == `WB_READ16) | (cmd == `WB_READ32);
//assign cmd_write = (cmd == `WB_WRITE8) | (cmd == `WB_WRITE16) | (cmd == `WB_WRITE32);
//assign cmd_go = cmd == `WB_GO;
//assign cmd_old_read = (cmd_old == `WB_READ8) | (cmd_old == `WB_READ16) | (cmd_old == `WB_READ32);
 
 
wire dr_read;
wire dr_write;
wire dr_go;
 
assign dr_read = (dr[2:0] == `WB_READ8) | (dr[2:0] == `WB_READ16) | (dr[2:0] == `WB_READ32);
assign dr_write = (dr[2:0] == `WB_WRITE8) | (dr[2:0] == `WB_WRITE16) | (dr[2:0] == `WB_WRITE32);
assign dr_go = dr[2:0] == `WB_GO;
 
 
always @ (posedge tck_i)
begin
  if (update_dr_i)
    begin
      dr_cmd_latched = 3'h0;
      dr_read_latched  <= #1 1'b0;
      dr_write_latched  <= #1 1'b0;
      dr_go_latched  <= #1 1'b0;
    end
  else if (cmd_cnt_end & (~cmd_cnt_end_q))
    begin
      dr_cmd_latched = dr[2:0];
      dr_read_latched <= #1 dr_read;
      dr_write_latched <= #1 dr_write;
      dr_go_latched <= #1 dr_go;
    end
end
 
 
always @ (posedge tck_i)
begin
  if (cmd_cnt == 2'h2)
    begin
      if ((~dr[0])  & (~tdi_i))  // (current command is WB_STATUS or WB_GO)
        addr_len_cnt_limit = 6'd0;
      else                                                        // (current command is WB_WRITEx or WB_READx)
        addr_len_cnt_limit = 6'd48;
    end
end
 
 
 
always @ (posedge tck_i)
begin
  if (cmd_cnt == 2'h2)
    begin
      if (dr[1] & (~dr[0]) & (~tdi_i) & cmd_write)  // current command is WB_GO and previous command is WB_WRITEx)
        data_cnt_limit = (len<<3);
      else
        data_cnt_limit = 19'h0;
    end
  else if (crc_cnt == 6'd31)
    begin
      if (dr_go_latched & cmd_read)                 // current command is WB_GO and previous command is WB_READx)  
        data_cnt_limit = (len<<3);
      else
        data_cnt_limit = 19'h0;
    end
end
 
 
assign crc_cnt_en = enable & cmd_cnt_end & addr_len_cnt_end & data_cnt_end & (~crc_cnt_end);
 
// crc counter
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    crc_cnt <= #1 'h0;
  else if(crc_cnt_en)
    crc_cnt <= #1 crc_cnt + 1'b1;
  else if (update_dr_i)
    crc_cnt <= #1 'h0;
end
 
assign cmd_cnt_end  = cmd_cnt  == 2'h3;
assign addr_len_cnt_end = addr_len_cnt == addr_len_cnt_limit;
assign crc_cnt_end  = crc_cnt  == 6'd32;
assign data_cnt_end = (data_cnt == data_cnt_limit);
 
always @ (posedge tck_i)
begin
  crc_cnt_end_q  <= #1 crc_cnt_end;
  cmd_cnt_end_q  <= #1 cmd_cnt_end;
  data_cnt_end_q <= #1 data_cnt_end;
end
 
 
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    status_cnt1 <= #1 1'b0;
  else if (update_dr_i)
    status_cnt1 <= #1 1'b0;
  else if (data_cnt_end & (~data_cnt_end_q) & cmd_old_read & dr_go_latched |
           crc_cnt_end & (~crc_cnt_end_q) & (~(cmd_read & dr_go_latched))       // cmd is not changed, yet.
          )
    status_cnt1 <= #1 1'b1;
end
 
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    begin
      status_cnt2 <= #1 1'b0;
      status_cnt3 <= #1 1'b0;
      status_cnt4 <= #1 1'b0;
    end
  else if (update_dr_i)
    begin
      status_cnt2 <= #1 1'b0;
      status_cnt3 <= #1 1'b0;
      status_cnt4 <= #1 1'b0;
    end
  else
    begin
      status_cnt2 <= #1 status_cnt1;
      status_cnt3 <= #1 status_cnt2;
      status_cnt4 <= #1 status_cnt3;
    end
end
 
 
 
 
 
assign status_cnt_end = status_cnt4;
reg [`STATUS_LEN -1:0] status;
 
reg wb_error, wb_error_sync, wb_error_tck;
reg wb_overrun, wb_overrun_sync, wb_overrun_tck;
 
reg busy_wb;
reg busy_tck;
reg wb_end;
reg wb_end_rst;
reg wb_end_rst_sync;
reg wb_end_sync;
reg wb_end_tck;
reg busy_sync;
reg [799:0] TDO_WISHBONE;
 
 
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    status <= #1 'h0;
  else if(crc_cnt_end & (~crc_cnt_end_q) & (~dr_read_latched))
    status <= #1 {crc_match_i, wb_error_tck, wb_overrun_tck, busy_tck}; // igor !!! wb_overrun_tck bo uporabljen skupaj z wb_underrun_tck,
  else if (data_cnt_end & (~data_cnt_end_q) & dr_read_latched)
    status <= #1 {crc_match_reg, wb_error_tck, wb_overrun_tck, busy_tck}; // igor !!! wb_overrun_tck bo uporabljen skupaj z wb_underrun_tck,
  else if (shift_dr_i & (~status_cnt_end))
    status <= #1 {status[0], status[`STATUS_LEN -1:1]};
end
// Following status is shifted out:
// 1. bit:          1 if crc is OK, else 0
// 2. bit:          1 while WB access is in progress (busy_tck), else 0
// 3. bit:          1 if overrun occured during write (data couldn't be written fast enough)
// 4. bit:          1 if WB error occured, else 0
 
 
 
always @ (crc_cnt_end or crc_cnt_end_q or crc_match_i or status or pause_dr_i or busy_tck or cmd_read or data_cnt_end or data_cnt_end_q or crc_match_reg or dr_read_latched)
begin
  if (pause_dr_i)
    begin
    tdo_o = busy_tck;
    TDO_WISHBONE = "busy_tck";
    end
  else if (crc_cnt_end & (~crc_cnt_end_q) & (~(dr_go_latched & cmd_read)))      // cmd is updated not updated, yet
    begin
      tdo_o = crc_match_i;
      TDO_WISHBONE = "crc_match_i";
    end
  else if (data_cnt_end & (~data_cnt_end_q) & dr_go_latched & cmd_old_read)     // cmd is already updated
    begin
      tdo_o = crc_match_reg;
      TDO_WISHBONE = "crc_match_reg";
    end
  else if (crc_cnt_end & (~(dr_go_latched & cmd_old_read)) | data_cnt_end & dr_go_latched & cmd_old_read)  // cmd is already updated
    begin
      tdo_o = status[0];
      TDO_WISHBONE = "status";
    end
  else
    begin
      tdo_o = 1'b0;
      TDO_WISHBONE = "zero while CRC is shifted in";
    end
end
 
 
reg set_addr, set_addr_sync, set_addr_wb, set_addr_wb_q;
 
always @ (posedge tck_i)
begin
  if(crc_cnt_end & (~crc_cnt_end_q))
    crc_match_reg <= #1 crc_match_i;
end
 
/*
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    begin
      cmd <= #1 'h0;
      cmd_old <= #1 'h0;
    end
  else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
    begin
      if (dr_write_latched | dr_read_latched)
        cmd <= #1 dr[50:48];
      else
        cmd <= #1 dr[2:0];
 
      cmd_old <= #1 cmd;
    end
end
*/
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    begin
      cmd <= #1 'h0;
      cmd_old <= #1 'h0;
      cmd_read <= #1 1'b0;
      cmd_write <= #1 1'b0;
      cmd_go <= #1 1'b0;
      cmd_old_read <= #1 1'b0;
    end
  else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
    begin
      cmd <= #1 dr_cmd_latched;
      cmd_old <= #1 cmd;
      cmd_read <= #1 dr_read_latched;
      cmd_write <= #1 dr_write_latched;
      cmd_go <= #1 dr_go_latched;
      cmd_old_read <= #1 cmd_read;
    end
end
 
 
always @ (posedge tck_i)
begin
  if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
    begin
      if (dr_write_latched | dr_read_latched)
        begin
          adr <= #1 dr[47:16];
          len <= #1 dr[15:0];
          set_addr <= #1 1'b1;
        end
    end
  else
    set_addr <= #1 1'b0;
end
 
 
// Start wishbone read cycle
always @ (posedge tck_i)
begin
//  if (set_addr & dr_read_latched)
  if (cmd_cnt_end & (~cmd_cnt_end_q) & cmd_read & dr_go)
    start_rd_tck <= #1 1'b1;
  else if (cmd_old_read & cmd_go & crc_cnt_end_q & (~data_cnt_end))
    begin
      case (cmd_old)  // synthesis parallel_case full_case
        `WB_READ8 : begin
                      if(byte & (~byte_q))
                        start_rd_tck <= #1 1'b1;
                      else
                        start_rd_tck <= #1 1'b0;
                    end
        `WB_READ16: begin
                      if(half & (~half_q))
                        start_rd_tck <= #1 1'b1;
                      else
                        start_rd_tck <= #1 1'b0;
                    end
        `WB_READ32: begin
                      if(long & (~long_q))
                        start_rd_tck <= #1 1'b1;
                      else
                        start_rd_tck <= #1 1'b0;
                    end
      endcase
    end
  else
    start_rd_tck <= #1 1'b0;
end
 
 
 
// Start wishbone write cycle
always @ (posedge tck_i)
begin
  if (dr_go_latched & cmd_write)
    begin
      case (cmd)  // synthesis parallel_case full_case
        `WB_WRITE8  : begin
                        if (byte & (~byte_q))
                          begin
                            start_wr_tck <= #1 1'b1;
                            wb_dat_o <= #1 {4{dr[7:0]}};
                          end
                        else
                          begin
                            start_wr_tck <= #1 1'b0;
                          end
                      end
        `WB_WRITE16 : begin
                        if (half & (~half_q))
                          begin
                            start_wr_tck <= #1 1'b1;
                            wb_dat_o <= #1 {2{dr[15:0]}};
                          end
                        else
                          begin
                            start_wr_tck <= #1 1'b0;
                          end
                      end
        `WB_WRITE32 : begin
                        if (long & (~long_q))
                          begin
                            start_wr_tck <= #1 1'b1;
                            wb_dat_o <= #1 dr[31:0];
                          end
                        else
                          begin
                            start_wr_tck <= #1 1'b0;
                          end
                      end
      endcase
    end
  else
    start_wr_tck <= #1 1'b0;
end
 
 
always @ (posedge wb_clk_i)
begin
  start_rd_sync1  <= #1 start_rd_tck;
  start_wb_rd     <= #1 start_rd_sync1;
  start_wb_rd_q   <= #1 start_wb_rd;
 
  start_wr_sync1  <= #1 start_wr_tck;
  start_wb_wr     <= #1 start_wr_sync1;
  start_wb_wr_q   <= #1 start_wb_wr;
 
  set_addr_sync   <= #1 set_addr;
  set_addr_wb     <= #1 set_addr_sync;
  set_addr_wb_q   <= #1 set_addr_wb;
end
 
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    wb_cyc_o <= #1 1'b0;
  else if ((start_wb_wr & (~start_wb_wr_q)) | (start_wb_rd & (~start_wb_rd_q)))
    wb_cyc_o <= #1 1'b1;
  else if (wb_ack_i | wb_err_i)
    wb_cyc_o <= #1 1'b0;
end
 
 
 
always @ (posedge wb_clk_i)
begin
  if (set_addr_wb & (~set_addr_wb_q)) // Setting starting address
    wb_adr_o <= #1 adr;
  else if (wb_ack_i)
    begin
      if ((cmd == `WB_WRITE8) | (cmd_old == `WB_READ8))
        wb_adr_o <= #1 wb_adr_o + 1'd1;
      else if ((cmd == `WB_WRITE16) | (cmd_old == `WB_READ16))
        wb_adr_o <= #1 wb_adr_o + 2'd2;
      else
        wb_adr_o <= #1 wb_adr_o + 3'd4;
    end
end
 
 
 
 
 
 
//    adr   byte  |  short  |  long
//     0    1000     1100      1111
//     1    0100     err       err
//     2    0010     0011      err
//     3    0001     err       err
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    wb_sel_o[3:0] <= #1 4'h0;
  else if (cmd_write & dr_go_latched | cmd_read)   // write or first read
    begin
      wb_sel_o[0] <= #1 (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b11) |
                        (cmd[1:0] == 2'b10) & (wb_adr_o[1:0] == 2'b10);
      wb_sel_o[1] <= #1 (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd[1] ^ cmd[0]) & (wb_adr_o[1:0] == 2'b10);
      wb_sel_o[2] <= #1 (cmd[1]) & (wb_adr_o[1:0] == 2'b00) | (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b01);
      wb_sel_o[3] <= #1 (wb_adr_o[1:0] == 2'b00);
    end
  else                                            // read
    begin
      wb_sel_o[0] <= #1 (cmd_old[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd_old[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b11) |
                        (cmd_old[1:0] == 2'b10) & (wb_adr_o[1:0] == 2'b10);
      wb_sel_o[1] <= #1 (cmd_old[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd_old[1] ^ cmd_old[0]) & (wb_adr_o[1:0] == 2'b10);
      wb_sel_o[2] <= #1 (cmd_old[1]) & (wb_adr_o[1:0] == 2'b00) | (cmd_old[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b01);
      wb_sel_o[3] <= #1 (wb_adr_o[1:0] == 2'b00);
    end
end
 
 
assign wb_we_o = cmd_write & dr_go_latched;
assign wb_cab_o = 1'b0;
assign wb_stb_o = wb_cyc_o;
assign wb_cti_o = 3'h0;     // always performing single access
assign wb_bte_o = 2'h0;     // always performing single access
 
reg [31:0] input_data;
 
always @ (posedge wb_clk_i)
begin
  if(wb_ack_i)
    input_data <= #1 wb_dat_i;
end
 
 
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    wb_end <= #1 1'b0;
  else if (wb_ack_i | wb_err_i)
    wb_end <= #1 1'b1;
  else if (wb_end_rst)
    wb_end <= #1 1'b0;
end
 
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    begin
      wb_end_sync <= #1 1'b0;
      wb_end_tck  <= #1 1'b0;
    end
  else
    begin
      wb_end_sync <= #1 wb_end;
      wb_end_tck  <= #1 wb_end_sync;
    end
end
 
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    busy_wb <= #1 1'b0;
  else if (wb_end_rst)
    busy_wb <= #1 1'b0;
  else if (wb_cyc_o)
    busy_wb <= #1 1'b1;
end
 
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    begin
      busy_sync <= #1 1'b0;
      busy_tck <= #1 1'b0;
    end
  else
    begin
      busy_sync <= #1 busy_wb;
      busy_tck <= #1 busy_sync;
    end
end
 
 
always @ (posedge wb_clk_i)
begin
  wb_end_rst_sync <= #1 wb_end_tck;
  wb_end_rst  <= #1 wb_end_rst_sync;
end
 
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    wb_error <= #1 1'b0;
  else if(wb_err_i)
    wb_error <= #1 1'b1;
  else if(wb_ack_i & status_reset_en) // error remains active until STATUS read is performed
    wb_error <= #1 1'b0;
end
 
always @ (posedge tck_i)
begin
  wb_error_sync <= #1 wb_error;
  wb_error_tck  <= #1 wb_error_sync;
end
 
 
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    wb_overrun <= #1 1'b0;
  else if(start_wb_wr & (~start_wb_wr_q) & wb_cyc_o)
    wb_overrun <= #1 1'b1;
  else if((wb_ack_i | wb_err_i) & status_reset_en) // error remains active until STATUS read is performed
    wb_overrun <= #1 1'b0;
end
 
always @ (posedge tck_i)
begin
  wb_overrun_sync <= #1 wb_overrun;
  wb_overrun_tck  <= #1 wb_overrun_sync;
end
 
 
 
 
 
 
// wb_error is locked until WB_STATUS is performed
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    status_reset_en <= 1'b0;
  else if((cmd_old == `WB_STATUS) & (cmd !== `WB_STATUS))
    status_reset_en <= #1 1'b1;
  else
    status_reset_en <= #1 1'b0;
end
 
 
 
 
 
 
 
 
 
endmodule
 

Line No.	Rev	Author	Line
1	82	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_wb.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7			`//// http://www.opencores.org/projects/DebugInterface/ ////`
8			`//// ////`
9			`//// Author(s): ////`
10			`//// Igor Mohor (igorm@opencores.org) ////`
11			`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the README.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 - 2003 Authors ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46	91	mohor	`// Revision 1.7 2004/01/08 17:53:36 mohor`
47			`// tmp version.`
48			`//`
49	90	mohor	`// Revision 1.6 2004/01/07 11:58:56 mohor`
50			`// temp4 version.`
51			`//`
52	89	mohor	`// Revision 1.5 2004/01/06 17:15:19 mohor`
53			`// temp3 version.`
54			`//`
55	88	mohor	`// Revision 1.4 2004/01/05 12:16:00 mohor`
56			`// tmp2 version.`
57			`//`
58	87	mohor	`// Revision 1.3 2003/12/23 16:22:46 mohor`
59			`// Tmp version.`
60			`//`
61	86	mohor	`// Revision 1.2 2003/12/23 15:26:26 mohor`
62			`// Small fix.`
63			`//`
64	83	mohor	`// Revision 1.1 2003/12/23 15:09:04 mohor`
65			`// New directory structure. New version of the debug interface.`
66	82	mohor	`//`
67			`//`
68	83	mohor	`//`
69	82	mohor
70			`// synopsys translate_off`
71			`include "timescale.v"
72			`// synopsys translate_on`
73			`include "dbg_wb_defines.v"
74
75			`// Top module`
76			`module dbg_wb(`
77			`// JTAG signals`
78			`trst_i, // trst_i is active high (inverted on higher layers)`
79			`tck_i,`
80			`tdi_i,`
81			`tdo_o,`
82
83			`// TAP states`
84			`shift_dr_i,`
85			`pause_dr_i,`
86			`update_dr_i,`
87
88			`wishbone_ce_i,`
89			`crc_match_i,`
90			`crc_en_o,`
91			`shift_crc_o,`
92
93			`// WISHBONE common signals`
94			`wb_rst_i, wb_clk_i,`
95
96			`// WISHBONE master interface`
97			`wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,`
98			`wb_we_o, wb_ack_i, wb_cab_o, wb_err_i, wb_cti_o, wb_bte_o`
99
100			`);`
101
102			`// JTAG signals`
103			`input trst_i;`
104			`input tck_i;`
105			`input tdi_i;`
106			`output tdo_o;`
107
108			`// TAP states`
109			`input shift_dr_i;`
110			`input pause_dr_i;`
111			`input update_dr_i;`
112
113			`input wishbone_ce_i;`
114			`input crc_match_i;`
115			`output crc_en_o;`
116			`output shift_crc_o;`
117
118			`// WISHBONE common signals`
119			`input wb_rst_i; // WISHBONE reset`
120			`input wb_clk_i; // WISHBONE clock`
121
122			`// WISHBONE master interface`
123			`output [31:0] wb_adr_o;`
124			`output [31:0] wb_dat_o;`
125			`input [31:0] wb_dat_i;`
126			`output wb_cyc_o;`
127			`output wb_stb_o;`
128			`output [3:0] wb_sel_o;`
129			`output wb_we_o;`
130			`input wb_ack_i;`
131			`output wb_cab_o;`
132			`input wb_err_i;`
133			`output [2:0] wb_cti_o;`
134			`output [1:0] wb_bte_o;`
135
136			`reg wb_cyc_o;`
137			`reg [31:0] wb_adr_o;`
138	88	mohor	`reg [31:0] wb_dat_o;`
139	82	mohor	`reg [3:0] wb_sel_o;`
140
141			`reg tdo_o;`
142
143	88	mohor	`reg [50:0] dr;`
144			`wire enable;`
145	90	mohor	`wire cmd_cnt_en;`
146	88	mohor	`reg [1:0] cmd_cnt;`
147			`wire cmd_cnt_end;`
148			`reg cmd_cnt_end_q;`
149	90	mohor	`wire addr_len_cnt_en;`
150	88	mohor	`reg [5:0] addr_len_cnt;`
151			`reg [5:0] addr_len_cnt_limit;`
152			`wire addr_len_cnt_end;`
153	90	mohor	`wire crc_cnt_en;`
154	88	mohor	`reg [5:0] crc_cnt;`
155			`wire crc_cnt_end;`
156			`reg crc_cnt_end_q;`
157	90	mohor	`wire data_cnt_en;`
158	88	mohor	`reg [18:0] data_cnt;`
159			`reg [18:0] data_cnt_limit;`
160			`wire data_cnt_end;`
161	90	mohor	`reg data_cnt_end_q;`
162	88	mohor	`reg status_reset_en;`
163	82	mohor
164	90	mohor	`reg crc_match_reg;`
165	82	mohor
166	91	mohor	`reg [2:0] cmd, cmd_old, dr_cmd_latched;`
167	88	mohor	`reg [31:0] adr;`
168			`reg [15:0] len;`
169	89	mohor	`reg start_rd_tck;`
170			`reg start_rd_sync1;`
171			`reg start_wb_rd;`
172			`reg start_wb_rd_q;`
173			`reg start_wr_tck;`
174			`reg start_wr_sync1;`
175			`reg start_wb_wr;`
176			`reg start_wb_wr_q;`
177	88	mohor
178	90	mohor	`reg dr_write_latched;`
179			`reg dr_read_latched;`
180			`reg dr_go_latched;`
181	88	mohor
182	82	mohor	`wire status_cnt_end;`
183
184	89	mohor	`wire byte, half, long;`
185			`reg byte_q, half_q, long_q;`
186	91	mohor	`reg cmd_read;`
187			`reg cmd_write;`
188			`reg cmd_go;`
189			`reg cmd_old_read;`
190	89	mohor
191	90	mohor	`reg status_cnt1, status_cnt2, status_cnt3, status_cnt4;`
192
193
194	82	mohor	`assign enable = wishbone_ce_i & shift_dr_i;`
195	90	mohor	`assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);`
196	89	mohor	`assign shift_crc_o = enable & status_cnt_end; // Signals dbg module to shift out the CRC`
197	82	mohor
198
199	90	mohor	`//always @ (posedge tck_i)`
200			`//begin`
201			`// if (enable & ((~addr_len_cnt_end) \| (~cmd_cnt_end) \| (~data_cnt_end)))`
202			`// dr <= #1 {dr[49:0], tdi_i};`
203			`//end`
204
205
206	82	mohor	`always @ (posedge tck_i)`
207			`begin`
208	90	mohor	`/* if (cmd_old_read & cmd_go)`
209			`begin`
210			`case (cmd_old) // synthesis parallel_case full_case`
211			`WB_READ8 : begin
212			`if(byte & (~byte_q))`
213	91	mohor	`dr[31:24] <= #1 input_data[];`
214	90	mohor	`else`
215			`dr <= #1 dr<<1;`
216			`end`
217			`WB_READ16: begin
218			`if(half & (~half_q))`
219			`start_rd_tck <= #1 1'b1;`
220			`else`
221			`start_rd_tck <= #1 1'b0;`
222			`end`
223			`WB_READ32: begin
224			`if(long & (~long_q))`
225			`start_rd_tck <= #1 1'b1;`
226			`else`
227			`start_rd_tck <= #1 1'b0;`
228			`end`
229			`endcase`
230			`end`
231			`else*/ if (enable & ((~addr_len_cnt_end) \| (~cmd_cnt_end) \| (~data_cnt_end)))`
232	88	mohor	`dr <= #1 {dr[49:0], tdi_i};`
233	82	mohor	`end`
234
235
236	90	mohor	`assign cmd_cnt_en = enable & (~cmd_cnt_end);`
237	88	mohor
238	82	mohor	`always @ (posedge tck_i or posedge trst_i)`
239			`begin`
240			`if (trst_i)`
241	87	mohor	`cmd_cnt <= #1 'h0;`
242	82	mohor	`else if (update_dr_i)`
243	87	mohor	`cmd_cnt <= #1 'h0;`
244	90	mohor	`else if (cmd_cnt_en)`
245	87	mohor	`cmd_cnt <= #1 cmd_cnt + 1'b1;`
246	82	mohor	`end`
247
248
249	90	mohor	`assign addr_len_cnt_en = enable & cmd_cnt_end & (~addr_len_cnt_end);`
250
251	87	mohor	`always @ (posedge tck_i or posedge trst_i)`
252			`begin`
253			`if (trst_i)`
254	88	mohor	`addr_len_cnt <= #1 'h0;`
255			`else if (update_dr_i)`
256			`addr_len_cnt <= #1 'h0;`
257	90	mohor	`else if (addr_len_cnt_en)`
258	88	mohor	`addr_len_cnt <= #1 addr_len_cnt + 1'b1;`
259			`end`
260
261
262	90	mohor	`assign data_cnt_en = enable & cmd_cnt_end & (~data_cnt_end);`
263
264	88	mohor	`always @ (posedge tck_i or posedge trst_i)`
265			`begin`
266			`if (trst_i)`
267	87	mohor	`data_cnt <= #1 'h0;`
268			`else if (update_dr_i)`
269			`data_cnt <= #1 'h0;`
270	90	mohor	`else if (data_cnt_en)`
271	87	mohor	`data_cnt <= #1 data_cnt + 1'b1;`
272			`end`
273	82	mohor
274	87	mohor
275	88	mohor
276			`assign byte = data_cnt[2:0] == 3'h0;`
277			`assign half = data_cnt[3:0] == 4'h0;`
278			`assign long = data_cnt[4:0] == 5'h0;`
279
280
281			`always @ (posedge tck_i)`
282			`begin`
283			`byte_q <= #1 byte;`
284			`half_q <= #1 half;`
285			`long_q <= #1 long;`
286			`end`
287
288
289
290	91	mohor	//assign cmd_read = (cmd == `WB_READ8) \| (cmd == `WB_READ16) \| (cmd == `WB_READ32);
291			//assign cmd_write = (cmd == `WB_WRITE8) \| (cmd == `WB_WRITE16) \| (cmd == `WB_WRITE32);
292			//assign cmd_go = cmd == `WB_GO;
293			//assign cmd_old_read = (cmd_old == `WB_READ8) \| (cmd_old == `WB_READ16) \| (cmd_old == `WB_READ32);
294	88	mohor
295	90	mohor
296	89	mohor	`wire dr_read;`
297			`wire dr_write;`
298			`wire dr_go;`
299	88	mohor
300	89	mohor	assign dr_read = (dr[2:0] == `WB_READ8) \| (dr[2:0] == `WB_READ16) \| (dr[2:0] == `WB_READ32);
301			assign dr_write = (dr[2:0] == `WB_WRITE8) \| (dr[2:0] == `WB_WRITE16) \| (dr[2:0] == `WB_WRITE32);
302			assign dr_go = dr[2:0] == `WB_GO;
303	88	mohor
304
305			`always @ (posedge tck_i)`
306			`begin`
307			`if (update_dr_i)`
308	91	mohor	`begin`
309			`dr_cmd_latched = 3'h0;`
310			`dr_read_latched <= #1 1'b0;`
311			`dr_write_latched <= #1 1'b0;`
312			`dr_go_latched <= #1 1'b0;`
313			`end`
314	88	mohor	`else if (cmd_cnt_end & (~cmd_cnt_end_q))`
315	91	mohor	`begin`
316			`dr_cmd_latched = dr[2:0];`
317			`dr_read_latched <= #1 dr_read;`
318			`dr_write_latched <= #1 dr_write;`
319			`dr_go_latched <= #1 dr_go;`
320			`end`
321	88	mohor	`end`
322
323
324			`always @ (posedge tck_i)`
325			`begin`
326	90	mohor	`if (cmd_cnt == 2'h2)`
327	88	mohor	`begin`
328	90	mohor	`if ((~dr[0]) & (~tdi_i)) // (current command is WB_STATUS or WB_GO)`
329	88	mohor	`addr_len_cnt_limit = 6'd0;`
330	90	mohor	`else // (current command is WB_WRITEx or WB_READx)`
331	88	mohor	`addr_len_cnt_limit = 6'd48;`
332			`end`
333			`end`
334
335
336	90	mohor
337			`always @ (posedge tck_i)`
338	88	mohor	`begin`
339	90	mohor	`if (cmd_cnt == 2'h2)`
340	88	mohor	`begin`
341	90	mohor	`if (dr[1] & (~dr[0]) & (~tdi_i) & cmd_write) // current command is WB_GO and previous command is WB_WRITEx)`
342	88	mohor	`data_cnt_limit = (len<<3);`
343			`else`
344			`data_cnt_limit = 19'h0;`
345			`end`
346	90	mohor	`else if (crc_cnt == 6'd31)`
347			`begin`
348			`if (dr_go_latched & cmd_read) // current command is WB_GO and previous command is WB_READx)`
349			`data_cnt_limit = (len<<3);`
350			`else`
351			`data_cnt_limit = 19'h0;`
352			`end`
353	88	mohor	`end`
354
355
356	90	mohor	`assign crc_cnt_en = enable & cmd_cnt_end & addr_len_cnt_end & data_cnt_end & (~crc_cnt_end);`
357
358	82	mohor	`// crc counter`
359			`always @ (posedge tck_i or posedge trst_i)`
360			`begin`
361			`if (trst_i)`
362			`crc_cnt <= #1 'h0;`
363	90	mohor	`else if(crc_cnt_en)`
364	82	mohor	`crc_cnt <= #1 crc_cnt + 1'b1;`
365			`else if (update_dr_i)`
366			`crc_cnt <= #1 'h0;`
367			`end`
368
369	87	mohor	`assign cmd_cnt_end = cmd_cnt == 2'h3;`
370	88	mohor	`assign addr_len_cnt_end = addr_len_cnt == addr_len_cnt_limit;`
371	87	mohor	`assign crc_cnt_end = crc_cnt == 6'd32;`
372	89	mohor	`assign data_cnt_end = (data_cnt == data_cnt_limit);`
373	82	mohor
374			`always @ (posedge tck_i)`
375			`begin`
376	90	mohor	`crc_cnt_end_q <= #1 crc_cnt_end;`
377			`cmd_cnt_end_q <= #1 cmd_cnt_end;`
378			`data_cnt_end_q <= #1 data_cnt_end;`
379	82	mohor	`end`
380
381	90	mohor
382
383	82	mohor	`always @ (posedge tck_i or posedge trst_i)`
384			`begin`
385			`if (trst_i)`
386	90	mohor	`status_cnt1 <= #1 1'b0;`
387	82	mohor	`else if (update_dr_i)`
388	90	mohor	`status_cnt1 <= #1 1'b0;`
389			`else if (data_cnt_end & (~data_cnt_end_q) & cmd_old_read & dr_go_latched \|`
390			`crc_cnt_end & (~crc_cnt_end_q) & (~(cmd_read & dr_go_latched)) // cmd is not changed, yet.`
391			`)`
392			`status_cnt1 <= #1 1'b1;`
393	82	mohor	`end`
394
395	90	mohor
396			`always @ (posedge tck_i or posedge trst_i)`
397			`begin`
398			`if (trst_i)`
399			`begin`
400			`status_cnt2 <= #1 1'b0;`
401			`status_cnt3 <= #1 1'b0;`
402			`status_cnt4 <= #1 1'b0;`
403			`end`
404			`else if (update_dr_i)`
405			`begin`
406			`status_cnt2 <= #1 1'b0;`
407			`status_cnt3 <= #1 1'b0;`
408			`status_cnt4 <= #1 1'b0;`
409			`end`
410			`else`
411			`begin`
412			`status_cnt2 <= #1 status_cnt1;`
413			`status_cnt3 <= #1 status_cnt2;`
414			`status_cnt4 <= #1 status_cnt3;`
415			`end`
416			`end`
417
418
419
420
421
422			`assign status_cnt_end = status_cnt4;`
423	82	mohor	reg [`STATUS_LEN -1:0] status;
424
425			`reg wb_error, wb_error_sync, wb_error_tck;`
426	88	mohor	`reg wb_overrun, wb_overrun_sync, wb_overrun_tck;`
427	82	mohor
428	86	mohor	`reg busy_wb;`
429			`reg busy_tck;`
430			`reg wb_end;`
431			`reg wb_end_rst;`
432			`reg wb_end_rst_sync;`
433			`reg wb_end_sync;`
434			`reg wb_end_tck;`
435			`reg busy_sync;`
436			`reg [799:0] TDO_WISHBONE;`
437	82	mohor
438	90	mohor
439
440	82	mohor	`always @ (posedge tck_i or posedge trst_i)`
441			`begin`
442			`if (trst_i)`
443			`status <= #1 'h0;`
444	90	mohor	`else if(crc_cnt_end & (~crc_cnt_end_q) & (~dr_read_latched))`
445	88	mohor	`status <= #1 {crc_match_i, wb_error_tck, wb_overrun_tck, busy_tck}; // igor !!! wb_overrun_tck bo uporabljen skupaj z wb_underrun_tck,`
446	90	mohor	`else if (data_cnt_end & (~data_cnt_end_q) & dr_read_latched)`
447			`status <= #1 {crc_match_reg, wb_error_tck, wb_overrun_tck, busy_tck}; // igor !!! wb_overrun_tck bo uporabljen skupaj z wb_underrun_tck,`
448	82	mohor	`else if (shift_dr_i & (~status_cnt_end))`
449			status <= #1 {status[0], status[`STATUS_LEN -1:1]};
450			`end`
451	88	mohor	`// Following status is shifted out:`
452	82	mohor	`// 1. bit: 1 if crc is OK, else 0`
453	86	mohor	`// 2. bit: 1 while WB access is in progress (busy_tck), else 0`
454	88	mohor	`// 3. bit: 1 if overrun occured during write (data couldn't be written fast enough)`
455	82	mohor	`// 4. bit: 1 if WB error occured, else 0`
456
457
458	88	mohor
459	90	mohor	`always @ (crc_cnt_end or crc_cnt_end_q or crc_match_i or status or pause_dr_i or busy_tck or cmd_read or data_cnt_end or data_cnt_end_q or crc_match_reg or dr_read_latched)`
460	82	mohor	`begin`
461			`if (pause_dr_i)`
462	87	mohor	`begin`
463	82	mohor	`tdo_o = busy_tck;`
464			`TDO_WISHBONE = "busy_tck";`
465	87	mohor	`end`
466	90	mohor	`else if (crc_cnt_end & (~crc_cnt_end_q) & (~(dr_go_latched & cmd_read))) // cmd is updated not updated, yet`
467	87	mohor	`begin`
468			`tdo_o = crc_match_i;`
469			`TDO_WISHBONE = "crc_match_i";`
470			`end`
471	90	mohor	`else if (data_cnt_end & (~data_cnt_end_q) & dr_go_latched & cmd_old_read) // cmd is already updated`
472	87	mohor	`begin`
473	90	mohor	`tdo_o = crc_match_reg;`
474			`TDO_WISHBONE = "crc_match_reg";`
475			`end`
476			`else if (crc_cnt_end & (~(dr_go_latched & cmd_old_read)) \| data_cnt_end & dr_go_latched & cmd_old_read) // cmd is already updated`
477			`begin`
478	87	mohor	`tdo_o = status[0];`
479			`TDO_WISHBONE = "status";`
480			`end`
481	82	mohor	`else`
482	87	mohor	`begin`
483			`tdo_o = 1'b0;`
484			`TDO_WISHBONE = "zero while CRC is shifted in";`
485			`end`
486	82	mohor	`end`
487
488
489	88	mohor	`reg set_addr, set_addr_sync, set_addr_wb, set_addr_wb_q;`
490	82	mohor
491			`always @ (posedge tck_i)`
492			`begin`
493	90	mohor	`if(crc_cnt_end & (~crc_cnt_end_q))`
494			`crc_match_reg <= #1 crc_match_i;`
495			`end`
496
497	91	mohor	`/*`
498	90	mohor	`always @ (posedge tck_i or posedge trst_i)`
499			`begin`
500			`if (trst_i)`

Browse

Tools

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [asyst_2/] [rtl/] [verilog/] [dbg_wb.v] - Blame information for rev 91