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[/] [dbg_interface/] [tags/] [highland_ver1/] [rtl/] [verilog/] [dbg_cpu.v] - Blame information for rev 100

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_cpu.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2004 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "dbg_cpu_defines.v"
 
// Top module
module dbg_cpu(
                // JTAG signals
                tck_i,
                tdi_i,
                tdo_o,
 
                // TAP states
                shift_dr_i,
                pause_dr_i,
                update_dr_i,
 
                cpu_ce_i,
                crc_match_i,
                crc_en_o,
                shift_crc_o,
                rst_i,
                clk_i
 
 
              );
 
// JTAG signals
input         tck_i;
input         tdi_i;
output        tdo_o;
 
// TAP states
input         shift_dr_i;
input         pause_dr_i;
input         update_dr_i;
 
input         cpu_ce_i;
input         crc_match_i;
output        crc_en_o;
output        shift_crc_o;
input         rst_i;
input         clk_i;
 
reg           tdo_o;
 
wire          cmd_cnt_en;
reg     [1:0] cmd_cnt;
wire          cmd_cnt_end;
reg           cmd_cnt_end_q;
wire          addr_cnt_en;
reg     [5:0] addr_cnt;
reg     [5:0] addr_cnt_limit;
wire          addr_cnt_end;
wire          crc_cnt_en;
reg     [5:0] crc_cnt;
wire          crc_cnt_end;
reg           crc_cnt_end_q;
wire          data_cnt_en;
reg     [5:0] data_cnt;
reg     [5:0] data_cnt_limit;
wire          data_cnt_end;
reg           data_cnt_end_q;
wire          status_cnt_end;
reg           status_cnt1, status_cnt2, status_cnt3, status_cnt4;
reg     [3:0] status;
 
wire          enable;
 
reg           read_cycle_reg;
reg           read_cycle_cpu;
reg           write_cycle_reg;
reg           write_cycle_cpu;
wire          read_cycle;
wire          write_cycle;
 
reg    [34:0] dr;
 
wire          dr_read_reg;
wire          dr_write_reg;
wire          dr_read_cpu8;
wire          dr_read_cpu32;
wire          dr_write_cpu8;
wire          dr_write_cpu32;
wire          dr_go;
 
reg           dr_read_reg_latched;
reg           dr_write_reg_latched;
reg           dr_read_cpu8_latched;
reg           dr_read_cpu32_latched;
reg           dr_write_cpu8_latched;
reg           dr_write_cpu32_latched;
reg           dr_go_latched;
 
reg           cmd_read_reg;
reg           cmd_read_cpu;
reg           cmd_write_reg;
reg           cmd_write_cpu;
 
wire          go_prelim;
wire          crc_cnt_31;
 
 
assign enable = cpu_ce_i & shift_dr_i;
assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);
assign shift_crc_o = enable & status_cnt_end;  // Signals dbg module to shift out the CRC
 
 
assign cmd_cnt_en = enable & (~cmd_cnt_end);
 
 
// Command counter
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    cmd_cnt <= #1 'h0;
  else if (update_dr_i)
    cmd_cnt <= #1 'h0;
  else if (cmd_cnt_en)
    cmd_cnt <= #1 cmd_cnt + 1'b1;
end
 
 
assign addr_cnt_en = enable & cmd_cnt_end & (~addr_cnt_end);
 
 
// Address/length counter
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    addr_cnt <= #1 'h0;
  else if (update_dr_i)
    addr_cnt <= #1 'h0;
  else if (addr_cnt_en)
    addr_cnt <= #1 addr_cnt + 1'b1;
end
 
 
assign data_cnt_en = enable & (~data_cnt_end) & (cmd_cnt_end & write_cycle | crc_cnt_end & read_cycle);
 
 
// Data counter
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    data_cnt <= #1 'h0;
  else if (update_dr_i)
    data_cnt <= #1 'h0;
  else if (data_cnt_en)
    data_cnt <= #1 data_cnt + 1'b1;
end
 
 
assign crc_cnt_en = enable & (~crc_cnt_end) & (cmd_cnt_end & addr_cnt_end  & (~write_cycle) | (data_cnt_end & write_cycle));
 
 
// crc counter
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    crc_cnt <= #1 'h0;
  else if(crc_cnt_en)
    crc_cnt <= #1 crc_cnt + 1'b1;
  else if (update_dr_i)
    crc_cnt <= #1 'h0;
end
 
 
// Upper limit. Address/length counter counts until this value is reached
always @ (posedge tck_i)
begin
  if (cmd_cnt == 2'h2)
    begin
      if ((~dr[0])  & (~tdi_i))                                   // (current command is WB_STATUS or WB_GO)
        addr_cnt_limit = 6'd0;
      else                                                        // (current command is WB_WRITEx or WB_READx)
        addr_cnt_limit = 6'd32;
    end
end
 
 
assign cmd_cnt_end  = cmd_cnt  == 2'h3;
assign addr_cnt_end = addr_cnt == addr_cnt_limit;
assign crc_cnt_end  = crc_cnt  == 6'd32;
assign crc_cnt_31 = crc_cnt  == 6'd31;
assign data_cnt_end = (data_cnt == data_cnt_limit);
 
always @ (posedge tck_i)
begin
  crc_cnt_end_q  <= #1 crc_cnt_end;
  cmd_cnt_end_q  <= #1 cmd_cnt_end;
  data_cnt_end_q <= #1 data_cnt_end;
end
 
 
// Status counter is made of 4 serialy connected registers
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    status_cnt1 <= #1 1'b0;
  else if (update_dr_i)
    status_cnt1 <= #1 1'b0;
  else if (data_cnt_end & read_cycle |
           crc_cnt_end & (~read_cycle)
          )
    status_cnt1 <= #1 1'b1;
end
 
 
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      status_cnt2 <= #1 1'b0;
      status_cnt3 <= #1 1'b0;
      status_cnt4 <= #1 1'b0;
    end
  else if (update_dr_i)
    begin
      status_cnt2 <= #1 1'b0;
      status_cnt3 <= #1 1'b0;
      status_cnt4 <= #1 1'b0;
    end
  else
    begin
      status_cnt2 <= #1 status_cnt1;
      status_cnt3 <= #1 status_cnt2;
      status_cnt4 <= #1 status_cnt3;
    end
end
 
 
assign status_cnt_end = status_cnt4;
 
 
reg [31:0] adr;
reg set_addr;
 
 
// Latching address
always @ (posedge tck_i)
begin
  if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
    begin
      if (~dr_go_latched)
        begin
          adr <= #1 dr[31:0];
          set_addr <= #1 1'b1;
        end
    end
  else
    set_addr <= #1 1'b0;
end
 
 
reg latch_data;
reg [199:0] latching_data_text;
 
// Shift register for shifting in and out the data
always @ (posedge tck_i)
begin
  if (enable & ((~addr_cnt_end) | (~cmd_cnt_end) | ((~data_cnt_end) & write_cycle)))
    begin
      dr <= #1 {dr[33:0], tdi_i};
      latch_data <= #1 1'b0;
      latching_data_text = "tdi shifted in";
    end
  else
    latching_data_text = "nothing";
end
 
 
assign dr_read_reg    = dr[2:0] == `CPU_READ_REG;
assign dr_write_reg   = dr[2:0] == `CPU_WRITE_REG;
assign dr_read_cpu8   = dr[2:0] == `CPU_READ8;
assign dr_read_cpu32  = dr[2:0] == `CPU_READ32;
assign dr_write_cpu8  = dr[2:0] == `CPU_WRITE8;
assign dr_write_cpu32 = dr[2:0] == `CPU_WRITE32;
assign dr_go          = dr[2:0] == `CPU_GO;
 
 
// Latching instruction
always @ (posedge tck_i)
begin
  if (update_dr_i)
    begin
      dr_read_reg_latched  <= #1 1'b0;
      dr_read_cpu8_latched  <= #1 1'b0;
      dr_read_cpu32_latched  <= #1 1'b0;
      dr_write_reg_latched  <= #1 1'b0;
      dr_write_cpu8_latched  <= #1 1'b0;
      dr_write_cpu32_latched  <= #1 1'b0;
      dr_go_latched  <= #1 1'b0;
    end
  else if (cmd_cnt_end & (~cmd_cnt_end_q))
    begin
      dr_read_reg_latched <= #1 dr_read_reg;
      dr_read_cpu8_latched <= #1 dr_read_cpu8;
      dr_read_cpu32_latched <= #1 dr_read_cpu32;
      dr_write_reg_latched <= #1 dr_write_reg;
      dr_write_cpu8_latched <= #1 dr_write_cpu8;
      dr_write_cpu32_latched <= #1 dr_write_cpu32;
      dr_go_latched <= #1 dr_go;
    end
end
 
// Latching instruction
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      cmd_read_reg    <= #1 1'b0;
      cmd_read_cpu    <= #1 1'b0;
      cmd_write_reg   <= #1 1'b0;
      cmd_write_cpu   <= #1 1'b0;
    end
  else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
    begin
      cmd_read_reg    <= #1 dr_read_reg_latched;
      cmd_read_cpu    <= #1 dr_read_cpu8_latched | dr_read_cpu32_latched;
      cmd_write_reg   <= #1 dr_write_reg_latched;
      cmd_write_cpu   <= #1 dr_write_cpu8_latched | dr_write_cpu32_latched;
    end
end
 
 
// Upper limit. Data counter counts until this value is reached.
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    data_cnt_limit <= #1 6'h0;
  else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
    begin
      if (dr_read_cpu32_latched | dr_write_cpu32_latched)
        data_cnt_limit <= #1 6'd32;
      else
        data_cnt_limit <= #1 6'd8;
    end
end
 
 
assign go_prelim = (cmd_cnt == 2'h2) & dr[1] & (~dr[0]) & (~tdi_i);
 
 
always @ (posedge tck_i)
begin
  if (update_dr_i)
    read_cycle_reg <= #1 1'b0;
  else if (cmd_read_reg & go_prelim)
    read_cycle_reg <= #1 1'b1;
end
 
 
always @ (posedge tck_i)
begin
  if (update_dr_i)
    read_cycle_cpu <= #1 1'b0;
  else if (cmd_read_cpu & go_prelim)
    read_cycle_cpu <= #1 1'b1;
end
 
 
always @ (posedge tck_i)
begin
  if (update_dr_i)
    write_cycle_reg <= #1 1'b0;
  else if (cmd_write_reg & go_prelim)
    write_cycle_reg <= #1 1'b1;
end
 
 
always @ (posedge tck_i)
begin
  if (update_dr_i)
    write_cycle_cpu <= #1 1'b0;
  else if (cmd_write_cpu & go_prelim)
    write_cycle_cpu <= #1 1'b1;
end
 
 
assign read_cycle = read_cycle_reg | read_cycle_cpu;
assign write_cycle = write_cycle_reg | write_cycle_cpu;
 
reg reg_access;
 
// Start register write cycle
always @ (posedge tck_i)
begin
  if (write_cycle_reg & data_cnt_end & (~data_cnt_end_q))
    begin
      reg_access <= #1 1'b1;
    end
  else
    reg_access <= #1 1'b0;
end
 
 
 
// Connecting dbg_cpu_registers
dbg_cpu_registers i_dbg_cpu_registers
     (
      .data_in          (dr[7:0]),
      .data_out         (),
      .address          (adr[1:0]),
      .rw               (write_cycle),
      .access           (reg_access),
      .clk              (tck_i),
      .bp               (1'b1),
      .reset            (rst_i),
      .cpu_stall        (),
      .cpu_stall_all    (),
      .cpu_sel          (),
      .cpu_reset        ()
     );
 
 
 
 
 
endmodule
 

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[/] [dbg_interface/] [tags/] [highland_ver1/] [rtl/] [verilog/] [dbg_cpu.v] - Blame information for rev 100

Line No.	Rev	Author	Line
1	100	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_cpu.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7			`//// http://www.opencores.org/projects/DebugInterface/ ////`
8			`//// ////`
9			`//// Author(s): ////`
10			`//// Igor Mohor (igorm@opencores.org) ////`
11			`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the README.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 - 2004 Authors ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46			`//`
47			`//`
48
49			`// synopsys translate_off`
50			`include "timescale.v"
51			`// synopsys translate_on`
52			`include "dbg_cpu_defines.v"
53
54			`// Top module`
55			`module dbg_cpu(`
56			`// JTAG signals`
57			`tck_i,`
58			`tdi_i,`
59			`tdo_o,`
60
61			`// TAP states`
62			`shift_dr_i,`
63			`pause_dr_i,`
64			`update_dr_i,`
65
66			`cpu_ce_i,`
67			`crc_match_i,`
68			`crc_en_o,`
69			`shift_crc_o,`
70			`rst_i,`
71			`clk_i`
72
73
74			`);`
75
76			`// JTAG signals`
77			`input tck_i;`
78			`input tdi_i;`
79			`output tdo_o;`
80
81			`// TAP states`
82			`input shift_dr_i;`
83			`input pause_dr_i;`
84			`input update_dr_i;`
85
86			`input cpu_ce_i;`
87			`input crc_match_i;`
88			`output crc_en_o;`
89			`output shift_crc_o;`
90			`input rst_i;`
91			`input clk_i;`
92
93			`reg tdo_o;`
94
95			`wire cmd_cnt_en;`
96			`reg [1:0] cmd_cnt;`
97			`wire cmd_cnt_end;`
98			`reg cmd_cnt_end_q;`
99			`wire addr_cnt_en;`
100			`reg [5:0] addr_cnt;`
101			`reg [5:0] addr_cnt_limit;`
102			`wire addr_cnt_end;`
103			`wire crc_cnt_en;`
104			`reg [5:0] crc_cnt;`
105			`wire crc_cnt_end;`
106			`reg crc_cnt_end_q;`
107			`wire data_cnt_en;`
108			`reg [5:0] data_cnt;`
109			`reg [5:0] data_cnt_limit;`
110			`wire data_cnt_end;`
111			`reg data_cnt_end_q;`
112			`wire status_cnt_end;`
113			`reg status_cnt1, status_cnt2, status_cnt3, status_cnt4;`
114			`reg [3:0] status;`
115
116			`wire enable;`
117
118			`reg read_cycle_reg;`
119			`reg read_cycle_cpu;`
120			`reg write_cycle_reg;`
121			`reg write_cycle_cpu;`
122			`wire read_cycle;`
123			`wire write_cycle;`
124
125			`reg [34:0] dr;`
126
127			`wire dr_read_reg;`
128			`wire dr_write_reg;`
129			`wire dr_read_cpu8;`
130			`wire dr_read_cpu32;`
131			`wire dr_write_cpu8;`
132			`wire dr_write_cpu32;`
133			`wire dr_go;`
134
135			`reg dr_read_reg_latched;`
136			`reg dr_write_reg_latched;`
137			`reg dr_read_cpu8_latched;`
138			`reg dr_read_cpu32_latched;`
139			`reg dr_write_cpu8_latched;`
140			`reg dr_write_cpu32_latched;`
141			`reg dr_go_latched;`
142
143			`reg cmd_read_reg;`
144			`reg cmd_read_cpu;`
145			`reg cmd_write_reg;`
146			`reg cmd_write_cpu;`
147
148			`wire go_prelim;`
149			`wire crc_cnt_31;`
150
151
152			`assign enable = cpu_ce_i & shift_dr_i;`
153			`assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);`
154			`assign shift_crc_o = enable & status_cnt_end; // Signals dbg module to shift out the CRC`
155
156
157			`assign cmd_cnt_en = enable & (~cmd_cnt_end);`
158
159
160			`// Command counter`
161			`always @ (posedge tck_i or posedge rst_i)`
162			`begin`
163			`if (rst_i)`
164			`cmd_cnt <= #1 'h0;`
165			`else if (update_dr_i)`
166			`cmd_cnt <= #1 'h0;`
167			`else if (cmd_cnt_en)`
168			`cmd_cnt <= #1 cmd_cnt + 1'b1;`
169			`end`
170
171
172			`assign addr_cnt_en = enable & cmd_cnt_end & (~addr_cnt_end);`
173
174
175			`// Address/length counter`
176			`always @ (posedge tck_i or posedge rst_i)`
177			`begin`
178			`if (rst_i)`
179			`addr_cnt <= #1 'h0;`
180			`else if (update_dr_i)`
181			`addr_cnt <= #1 'h0;`
182			`else if (addr_cnt_en)`
183			`addr_cnt <= #1 addr_cnt + 1'b1;`
184			`end`
185
186
187			`assign data_cnt_en = enable & (~data_cnt_end) & (cmd_cnt_end & write_cycle \| crc_cnt_end & read_cycle);`
188
189
190			`// Data counter`
191			`always @ (posedge tck_i or posedge rst_i)`
192			`begin`
193			`if (rst_i)`
194			`data_cnt <= #1 'h0;`
195			`else if (update_dr_i)`
196			`data_cnt <= #1 'h0;`
197			`else if (data_cnt_en)`
198			`data_cnt <= #1 data_cnt + 1'b1;`
199			`end`
200
201
202			`assign crc_cnt_en = enable & (~crc_cnt_end) & (cmd_cnt_end & addr_cnt_end & (~write_cycle) \| (data_cnt_end & write_cycle));`
203
204
205			`// crc counter`
206			`always @ (posedge tck_i or posedge rst_i)`
207			`begin`
208			`if (rst_i)`
209			`crc_cnt <= #1 'h0;`
210			`else if(crc_cnt_en)`
211			`crc_cnt <= #1 crc_cnt + 1'b1;`
212			`else if (update_dr_i)`
213			`crc_cnt <= #1 'h0;`
214			`end`
215
216
217			`// Upper limit. Address/length counter counts until this value is reached`
218			`always @ (posedge tck_i)`
219			`begin`
220			`if (cmd_cnt == 2'h2)`
221			`begin`
222			`if ((~dr[0]) & (~tdi_i)) // (current command is WB_STATUS or WB_GO)`
223			`addr_cnt_limit = 6'd0;`
224			`else // (current command is WB_WRITEx or WB_READx)`
225			`addr_cnt_limit = 6'd32;`
226			`end`
227			`end`
228
229
230			`assign cmd_cnt_end = cmd_cnt == 2'h3;`
231			`assign addr_cnt_end = addr_cnt == addr_cnt_limit;`
232			`assign crc_cnt_end = crc_cnt == 6'd32;`
233			`assign crc_cnt_31 = crc_cnt == 6'd31;`
234			`assign data_cnt_end = (data_cnt == data_cnt_limit);`
235
236			`always @ (posedge tck_i)`
237			`begin`
238			`crc_cnt_end_q <= #1 crc_cnt_end;`
239			`cmd_cnt_end_q <= #1 cmd_cnt_end;`
240			`data_cnt_end_q <= #1 data_cnt_end;`
241			`end`
242
243
244			`// Status counter is made of 4 serialy connected registers`
245			`always @ (posedge tck_i or posedge rst_i)`
246			`begin`
247			`if (rst_i)`
248			`status_cnt1 <= #1 1'b0;`
249			`else if (update_dr_i)`
250			`status_cnt1 <= #1 1'b0;`
251			`else if (data_cnt_end & read_cycle \|`
252			`crc_cnt_end & (~read_cycle)`
253			`)`
254			`status_cnt1 <= #1 1'b1;`
255			`end`
256
257
258			`always @ (posedge tck_i or posedge rst_i)`
259			`begin`
260			`if (rst_i)`
261			`begin`
262			`status_cnt2 <= #1 1'b0;`
263			`status_cnt3 <= #1 1'b0;`
264			`status_cnt4 <= #1 1'b0;`
265			`end`
266			`else if (update_dr_i)`
267			`begin`
268			`status_cnt2 <= #1 1'b0;`
269			`status_cnt3 <= #1 1'b0;`
270			`status_cnt4 <= #1 1'b0;`
271			`end`
272			`else`
273			`begin`
274			`status_cnt2 <= #1 status_cnt1;`
275			`status_cnt3 <= #1 status_cnt2;`
276			`status_cnt4 <= #1 status_cnt3;`
277			`end`
278			`end`
279
280
281			`assign status_cnt_end = status_cnt4;`
282
283
284			`reg [31:0] adr;`
285			`reg set_addr;`
286
287
288			`// Latching address`
289			`always @ (posedge tck_i)`
290			`begin`
291			`if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)`
292			`begin`
293			`if (~dr_go_latched)`
294			`begin`
295			`adr <= #1 dr[31:0];`
296			`set_addr <= #1 1'b1;`
297			`end`
298			`end`
299			`else`
300			`set_addr <= #1 1'b0;`
301			`end`
302
303
304			`reg latch_data;`
305			`reg [199:0] latching_data_text;`
306
307			`// Shift register for shifting in and out the data`
308			`always @ (posedge tck_i)`
309			`begin`
310			`if (enable & ((~addr_cnt_end) \| (~cmd_cnt_end) \| ((~data_cnt_end) & write_cycle)))`
311			`begin`
312			`dr <= #1 {dr[33:0], tdi_i};`
313			`latch_data <= #1 1'b0;`
314			`latching_data_text = "tdi shifted in";`
315			`end`
316			`else`
317			`latching_data_text = "nothing";`
318			`end`
319
320
321			assign dr_read_reg = dr[2:0] == `CPU_READ_REG;
322			assign dr_write_reg = dr[2:0] == `CPU_WRITE_REG;
323			assign dr_read_cpu8 = dr[2:0] == `CPU_READ8;
324			assign dr_read_cpu32 = dr[2:0] == `CPU_READ32;
325			assign dr_write_cpu8 = dr[2:0] == `CPU_WRITE8;
326			assign dr_write_cpu32 = dr[2:0] == `CPU_WRITE32;
327			assign dr_go = dr[2:0] == `CPU_GO;
328
329
330			`// Latching instruction`
331			`always @ (posedge tck_i)`
332			`begin`
333			`if (update_dr_i)`
334			`begin`
335			`dr_read_reg_latched <= #1 1'b0;`
336			`dr_read_cpu8_latched <= #1 1'b0;`
337			`dr_read_cpu32_latched <= #1 1'b0;`
338			`dr_write_reg_latched <= #1 1'b0;`
339			`dr_write_cpu8_latched <= #1 1'b0;`
340			`dr_write_cpu32_latched <= #1 1'b0;`
341			`dr_go_latched <= #1 1'b0;`
342			`end`
343			`else if (cmd_cnt_end & (~cmd_cnt_end_q))`
344			`begin`
345			`dr_read_reg_latched <= #1 dr_read_reg;`
346			`dr_read_cpu8_latched <= #1 dr_read_cpu8;`
347			`dr_read_cpu32_latched <= #1 dr_read_cpu32;`
348			`dr_write_reg_latched <= #1 dr_write_reg;`
349			`dr_write_cpu8_latched <= #1 dr_write_cpu8;`
350			`dr_write_cpu32_latched <= #1 dr_write_cpu32;`
351			`dr_go_latched <= #1 dr_go;`
352			`end`
353			`end`
354
355			`// Latching instruction`
356			`always @ (posedge tck_i or posedge rst_i)`
357			`begin`
358			`if (rst_i)`
359			`begin`
360			`cmd_read_reg <= #1 1'b0;`
361			`cmd_read_cpu <= #1 1'b0;`
362			`cmd_write_reg <= #1 1'b0;`
363			`cmd_write_cpu <= #1 1'b0;`
364			`end`
365			`else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)`
366			`begin`
367			`cmd_read_reg <= #1 dr_read_reg_latched;`
368			`cmd_read_cpu <= #1 dr_read_cpu8_latched \| dr_read_cpu32_latched;`
369			`cmd_write_reg <= #1 dr_write_reg_latched;`
370			`cmd_write_cpu <= #1 dr_write_cpu8_latched \| dr_write_cpu32_latched;`
371			`end`
372			`end`
373
374
375			`// Upper limit. Data counter counts until this value is reached.`
376			`always @ (posedge tck_i or posedge rst_i)`
377			`begin`
378			`if (rst_i)`
379			`data_cnt_limit <= #1 6'h0;`
380			`else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)`
381			`begin`
382			`if (dr_read_cpu32_latched \| dr_write_cpu32_latched)`
383			`data_cnt_limit <= #1 6'd32;`
384			`else`
385			`data_cnt_limit <= #1 6'd8;`
386			`end`
387			`end`
388
389
390			`assign go_prelim = (cmd_cnt == 2'h2) & dr[1] & (~dr[0]) & (~tdi_i);`
391
392
393			`always @ (posedge tck_i)`
394			`begin`
395			`if (update_dr_i)`
396			`read_cycle_reg <= #1 1'b0;`
397			`else if (cmd_read_reg & go_prelim)`
398			`read_cycle_reg <= #1 1'b1;`
399			`end`
400
401
402			`always @ (posedge tck_i)`
403			`begin`
404			`if (update_dr_i)`
405			`read_cycle_cpu <= #1 1'b0;`
406			`else if (cmd_read_cpu & go_prelim)`
407			`read_cycle_cpu <= #1 1'b1;`
408			`end`
409
410
411			`always @ (posedge tck_i)`
412			`begin`
413			`if (update_dr_i)`
414			`write_cycle_reg <= #1 1'b0;`
415			`else if (cmd_write_reg & go_prelim)`
416			`write_cycle_reg <= #1 1'b1;`
417			`end`
418
419
420			`always @ (posedge tck_i)`
421			`begin`
422			`if (update_dr_i)`
423			`write_cycle_cpu <= #1 1'b0;`
424			`else if (cmd_write_cpu & go_prelim)`
425			`write_cycle_cpu <= #1 1'b1;`
426			`end`
427
428
429			`assign read_cycle = read_cycle_reg \| read_cycle_cpu;`
430			`assign write_cycle = write_cycle_reg \| write_cycle_cpu;`
431
432			`reg reg_access;`
433
434			`// Start register write cycle`
435			`always @ (posedge tck_i)`
436			`begin`
437			`if (write_cycle_reg & data_cnt_end & (~data_cnt_end_q))`
438			`begin`
439			`reg_access <= #1 1'b1;`
440			`end`
441			`else`
442			`reg_access <= #1 1'b0;`
443			`end`
444
445
446
447			`// Connecting dbg_cpu_registers`
448			`dbg_cpu_registers i_dbg_cpu_registers`
449			`(`
450			`.data_in (dr[7:0]),`
451			`.data_out (),`
452			`.address (adr[1:0]),`
453			`.rw (write_cycle),`
454			`.access (reg_access),`
455			`.clk (tck_i),`
456			`.bp (1'b1),`
457			`.reset (rst_i),`
458			`.cpu_stall (),`
459			`.cpu_stall_all (),`
460			`.cpu_sel (),`
461			`.cpu_reset ()`
462			`);`
463
464
465
466
467
468			`endmodule`
469