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[/] [dbg_interface/] [tags/] [highland_ver1/] [rtl/] [verilog/] [dbg_wb_defines.v] - Blame information for rev 82

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_wb_defines.v                                            ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2003 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//
 
 
// Defining commands for wishbone
`define WB_STATUS     3'h0
`define WB_WRITE8     3'h1
`define WB_WRITE16    3'h2
`define WB_WRITE32    3'h3
`define WB_GO         3'h4
`define WB_READ8      3'h5
`define WB_READ16     3'h6
`define WB_READ32     3'h7
 
 
// Defining max. WB chain
`define WB_DR_LEN     51
 
// Length of status
`define STATUS_LEN      4
`define STATUS_CNT      3
 
 
 
 
 
 
// Enable TRACE
//`define TRACE_ENABLED  // Uncomment this define to activate the trace
 
// Define number of cpus supported by the dbg interface
`define CPU_NUM 2
 
// Define master clock (CPU clock)
//`define       CPU_CLOCK  50   // Half period = 50 ns => MCLK = 10 Mhz
`define CPU_CLOCK  2.5   // Half period = 5 ns => MCLK = 200 Mhz
 
 
 
// Trace buffer size and counter and write/read pointer width. This can be expanded when more RAM is avaliable
`define TRACECOUNTERWIDTH        5
`define TRACEBUFFERLENGTH        32 // 2^5
 
`define TRACESAMPLEWIDTH         36
 
// OpSelect width
`define OPSELECTWIDTH            3
`define OPSELECTIONCOUNTER       8    //2^3
 
// OpSelect (dbg_op_i) signal meaning
`define DEBUG_READ_0               0
`define DEBUG_WRITE_0              1
`define DEBUG_READ_1               2
`define DEBUG_WRITE_1              3
`define DEBUG_READ_2               4
`define DEBUG_WRITE_2              5
`define DEBUG_READ_3               6
`define DEBUG_WRITE_3              7
 
// Registers addresses
`define MODER_ADR           5'h00
`define TSEL_ADR            5'h01
`define QSEL_ADR            5'h02
`define SSEL_ADR            5'h03
`define CPUOP_ADR           5'h04
`define CPUSEL_ADR          5'h05
`define RECSEL_ADR          5'h10
`define MON_CNTL_ADR        5'h11
`define WB_CNTL_ADR         5'h12
 
 
// Registers default values (after reset)
`define MODER_DEF           2'h0
`define TSEL_DEF            32'h00000000
`define QSEL_DEF            32'h00000000
`define SSEL_DEF            32'h00000000
`define CPUOP_DEF           2'h0
`define RECSEL_DEF          7'h0
`define MON_CNTL_DEF        4'h0

Line No.	Rev	Author	Line
1	82	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_wb_defines.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7			`//// http://www.opencores.org/projects/DebugInterface/ ////`
8			`//// ////`
9			`//// Author(s): ////`
10			`//// Igor Mohor (igorm@opencores.org) ////`
11			`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the README.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 - 2003 Authors ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46			`//`
47			`//`
48
49
50			`// Defining commands for wishbone`
51			`define WB_STATUS 3'h0
52			`define WB_WRITE8 3'h1
53			`define WB_WRITE16 3'h2
54			`define WB_WRITE32 3'h3
55			`define WB_GO 3'h4
56			`define WB_READ8 3'h5
57			`define WB_READ16 3'h6
58			`define WB_READ32 3'h7
59
60
61			`// Defining max. WB chain`
62			`define WB_DR_LEN 51
63
64			`// Length of status`
65			`define STATUS_LEN 4
66			`define STATUS_CNT 3
67
68
69
70
71
72
73			`// Enable TRACE`
74			//`define TRACE_ENABLED // Uncomment this define to activate the trace
75
76			`// Define number of cpus supported by the dbg interface`
77			`define CPU_NUM 2
78
79			`// Define master clock (CPU clock)`
80			//`define CPU_CLOCK 50 // Half period = 50 ns => MCLK = 10 Mhz
81			`define CPU_CLOCK 2.5 // Half period = 5 ns => MCLK = 200 Mhz
82
83
84
85			`// Trace buffer size and counter and write/read pointer width. This can be expanded when more RAM is avaliable`
86			`define TRACECOUNTERWIDTH 5
87			`define TRACEBUFFERLENGTH 32 // 2^5
88
89			`define TRACESAMPLEWIDTH 36
90
91			`// OpSelect width`
92			`define OPSELECTWIDTH 3
93			`define OPSELECTIONCOUNTER 8 //2^3
94
95			`// OpSelect (dbg_op_i) signal meaning`
96			`define DEBUG_READ_0 0
97			`define DEBUG_WRITE_0 1
98			`define DEBUG_READ_1 2
99			`define DEBUG_WRITE_1 3
100			`define DEBUG_READ_2 4
101			`define DEBUG_WRITE_2 5
102			`define DEBUG_READ_3 6
103			`define DEBUG_WRITE_3 7
104
105			`// Registers addresses`
106			`define MODER_ADR 5'h00
107			`define TSEL_ADR 5'h01
108			`define QSEL_ADR 5'h02
109			`define SSEL_ADR 5'h03
110			`define CPUOP_ADR 5'h04
111			`define CPUSEL_ADR 5'h05
112			`define RECSEL_ADR 5'h10
113			`define MON_CNTL_ADR 5'h11
114			`define WB_CNTL_ADR 5'h12
115
116
117			`// Registers default values (after reset)`
118			`define MODER_DEF 2'h0
119			`define TSEL_DEF 32'h00000000
120			`define QSEL_DEF 32'h00000000
121			`define SSEL_DEF 32'h00000000
122			`define CPUOP_DEF 2'h0
123			`define RECSEL_DEF 7'h0
124			`define MON_CNTL_DEF 4'h0

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[/] [dbg_interface/] [tags/] [highland_ver1/] [rtl/] [verilog/] [dbg_wb_defines.v] - Blame information for rev 82