URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [old_debug/] [rtl/] [verilog/] [dbg_defines.v] - Blame information for rev 158

Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_defines.v                                               ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/cores/DebugInterface/              ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000,2001 Authors                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.13  2003/10/21 09:48:31  simons
// Mbist support added.
//
// Revision 1.12  2003/09/17 14:38:57  simons
// WB_CNTL register added, some syncronization fixes.
//
// Revision 1.11  2003/08/28 13:55:21  simons
// Three more chains added for cpu debug access.
//
// Revision 1.10  2003/07/31 12:19:49  simons
// Multiple cpu support added.
//
// Revision 1.9  2002/05/07 14:43:59  mohor
// mon_cntl_o signals that controls monitor mux added.
//
// Revision 1.8  2002/01/25 07:58:34  mohor
// IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
// not filled-in. Tested in hw.
//
// Revision 1.7  2001/12/06 10:08:06  mohor
// Warnings from synthesys tools fixed.
//
// Revision 1.6  2001/11/28 09:38:30  mohor
// Trace disabled by default.
//
// Revision 1.5  2001/10/15 09:55:47  mohor
// Wishbone interface added, few fixes for better performance,
// hooks for boundary scan testing added.
//
// Revision 1.4  2001/09/24 14:06:42  mohor
// Changes connected to the OpenRISC access (SPR read, SPR write).
//
// Revision 1.3  2001/09/20 10:11:25  mohor
// Working version. Few bugs fixed, comments added.
//
// Revision 1.2  2001/09/18 14:13:47  mohor
// Trace fixed. Some registers changed, trace simplified.
//
// Revision 1.1.1.1  2001/09/13 13:49:19  mohor
// Initial official release.
//
// Revision 1.3  2001/06/01 22:22:35  mohor
// This is a backup. It is not a fully working version. Not for use, yet.
//
// Revision 1.2  2001/05/18 13:10:00  mohor
// Headers changed. All additional information is now avaliable in the README.txt file.
//
// Revision 1.1.1.1  2001/05/18 06:35:08  mohor
// Initial release
//
//
 
 
 
// Enable TRACE
//`define TRACE_ENABLED  // Uncomment this define to activate the trace
 
// Define number of cpus supported by the dbg interface
`define CPU_NUM 2
 
// Define IDCODE Value
`define IDCODE_VALUE  32'h14951185
 
// Define master clock (CPU clock)
//`define       CPU_CLOCK  50   // Half period = 50 ns => MCLK = 10 Mhz
`define CPU_CLOCK  2.5   // Half period = 5 ns => MCLK = 200 Mhz
 
// Length of the Instruction register
`define IR_LENGTH       4
 
// Length of the Data register (must be equal to the longest scan chain for shifting the data in)
`define DR_LENGTH       74
 
// Length of the CHAIN ID register
`define CHAIN_ID_LENGTH 4
 
// Length of the CRC
`define CRC_LENGTH      8
 
// Trace buffer size and counter and write/read pointer width. This can be expanded when more RAM is avaliable
`define TRACECOUNTERWIDTH        5
`define TRACEBUFFERLENGTH        32 // 2^5
 
`define TRACESAMPLEWIDTH         36
 
// OpSelect width
`define OPSELECTWIDTH            3
`define OPSELECTIONCOUNTER       8    //2^3
 
// OpSelect (dbg_op_i) signal meaning
`define DEBUG_READ_0               0
`define DEBUG_WRITE_0              1
`define DEBUG_READ_1               2
`define DEBUG_WRITE_1              3
`define DEBUG_READ_2               4
`define DEBUG_WRITE_2              5
`define DEBUG_READ_3               6
`define DEBUG_WRITE_3              7
 
// Supported Instructions
`define EXTEST          4'b0000
`define SAMPLE_PRELOAD  4'b0001
`define IDCODE          4'b0010
`define CHAIN_SELECT    4'b0011
`define INTEST          4'b0100
`define CLAMP           4'b0101
`define CLAMPZ          4'b0110
`define HIGHZ           4'b0111
`define DEBUG           4'b1000
`define MBIST           4'b1001
`define BYPASS          4'b1111
 
// Chains
`define GLOBAL_BS_CHAIN     4'b0000
`define CPU_DEBUG_CHAIN_2   4'b0001
`define CPU_TEST_CHAIN      4'b0010
`define TRACE_TEST_CHAIN    4'b0011
`define REGISTER_SCAN_CHAIN 4'b0100
`define WISHBONE_SCAN_CHAIN 4'b0101
`define CPU_DEBUG_CHAIN_0   4'b0110
`define CPU_DEBUG_CHAIN_1   4'b0111
`define CPU_DEBUG_CHAIN_3   4'b1000
 
// Registers addresses
`define MODER_ADR           5'h00
`define TSEL_ADR            5'h01
`define QSEL_ADR            5'h02
`define SSEL_ADR            5'h03
`define CPUOP_ADR           5'h04
`define CPUSEL_ADR          5'h05
`define RECSEL_ADR          5'h10
`define MON_CNTL_ADR        5'h11
`define WB_CNTL_ADR         5'h12
 
 
// Registers default values (after reset)
`define MODER_DEF           2'h0
`define TSEL_DEF            32'h00000000
`define QSEL_DEF            32'h00000000
`define SSEL_DEF            32'h00000000
`define CPUOP_DEF           2'h0
`define RECSEL_DEF          7'h0
`define MON_CNTL_DEF        4'h0

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_defines.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7			`//// http://www.opencores.org/cores/DebugInterface/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is avaliable in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000,2001 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	73	mohor	`// Revision 1.13 2003/10/21 09:48:31 simons`
49			`// Mbist support added.`
50			`//`
51	71	simons	`// Revision 1.12 2003/09/17 14:38:57 simons`
52			`// WB_CNTL register added, some syncronization fixes.`
53			`//`
54	65	simons	`// Revision 1.11 2003/08/28 13:55:21 simons`
55			`// Three more chains added for cpu debug access.`
56			`//`
57	63	simons	`// Revision 1.10 2003/07/31 12:19:49 simons`
58			`// Multiple cpu support added.`
59			`//`
60	57	simons	`// Revision 1.9 2002/05/07 14:43:59 mohor`
61			`// mon_cntl_o signals that controls monitor mux added.`
62			`//`
63	47	mohor	`// Revision 1.8 2002/01/25 07:58:34 mohor`
64			`// IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in`
65			`// not filled-in. Tested in hw.`
66			`//`
67	30	mohor	`// Revision 1.7 2001/12/06 10:08:06 mohor`
68			`// Warnings from synthesys tools fixed.`
69			`//`
70	27	mohor	`// Revision 1.6 2001/11/28 09:38:30 mohor`
71			`// Trace disabled by default.`
72			`//`
73	23	mohor	`// Revision 1.5 2001/10/15 09:55:47 mohor`
74			`// Wishbone interface added, few fixes for better performance,`
75			`// hooks for boundary scan testing added.`
76			`//`
77	12	mohor	`// Revision 1.4 2001/09/24 14:06:42 mohor`
78			`// Changes connected to the OpenRISC access (SPR read, SPR write).`
79			`//`
80	11	mohor	`// Revision 1.3 2001/09/20 10:11:25 mohor`
81			`// Working version. Few bugs fixed, comments added.`
82			`//`
83	9	mohor	`// Revision 1.2 2001/09/18 14:13:47 mohor`
84			`// Trace fixed. Some registers changed, trace simplified.`
85			`//`
86	5	mohor	`// Revision 1.1.1.1 2001/09/13 13:49:19 mohor`
87			`// Initial official release.`
88			`//`
89	2	mohor	`// Revision 1.3 2001/06/01 22:22:35 mohor`
90			`// This is a backup. It is not a fully working version. Not for use, yet.`
91			`//`
92			`// Revision 1.2 2001/05/18 13:10:00 mohor`
93			`// Headers changed. All additional information is now avaliable in the README.txt file.`
94			`//`
95			`// Revision 1.1.1.1 2001/05/18 06:35:08 mohor`
96			`// Initial release`
97			`//`
98			`//`
99
100
101
102			`// Enable TRACE`
103	23	mohor	//`define TRACE_ENABLED // Uncomment this define to activate the trace
104	2	mohor
105	57	simons	`// Define number of cpus supported by the dbg interface`
106	73	mohor	`define CPU_NUM 2
107	2	mohor
108			`// Define IDCODE Value`
109	71	simons	`define IDCODE_VALUE 32'h14951185
110	2	mohor
111	73	mohor	`// Define master clock (CPU clock)`
112			//`define CPU_CLOCK 50 // Half period = 50 ns => MCLK = 10 Mhz
113			`define CPU_CLOCK 2.5 // Half period = 5 ns => MCLK = 200 Mhz
114	2	mohor
115			`// Length of the Instruction register`
116			`define IR_LENGTH 4
117
118	30	mohor	`// Length of the Data register (must be equal to the longest scan chain for shifting the data in)`
119	27	mohor	`define DR_LENGTH 74
120	2	mohor
121			`// Length of the CHAIN ID register`
122			`define CHAIN_ID_LENGTH 4
123
124			`// Length of the CRC`
125			`define CRC_LENGTH 8
126
127	9	mohor	`// Trace buffer size and counter and write/read pointer width. This can be expanded when more RAM is avaliable`
128			`define TRACECOUNTERWIDTH 5
129			`define TRACEBUFFERLENGTH 32 // 2^5
130
131	2	mohor	`define TRACESAMPLEWIDTH 36
132
133			`// OpSelect width`
134			`define OPSELECTWIDTH 3
135			`define OPSELECTIONCOUNTER 8 //2^3
136
137	11	mohor	`// OpSelect (dbg_op_i) signal meaning`
138	63	simons	`define DEBUG_READ_0 0
139			`define DEBUG_WRITE_0 1
140			`define DEBUG_READ_1 2
141			`define DEBUG_WRITE_1 3
142			`define DEBUG_READ_2 4
143			`define DEBUG_WRITE_2 5
144			`define DEBUG_READ_3 6
145			`define DEBUG_WRITE_3 7
146
147	2	mohor	`// Supported Instructions`
148	30	mohor	`define EXTEST 4'b0000
149			`define SAMPLE_PRELOAD 4'b0001
150			`define IDCODE 4'b0010
151			`define CHAIN_SELECT 4'b0011
152			`define INTEST 4'b0100
153			`define CLAMP 4'b0101
154			`define CLAMPZ 4'b0110
155			`define HIGHZ 4'b0111
156			`define DEBUG 4'b1000
157	71	simons	`define MBIST 4'b1001
158	30	mohor	`define BYPASS 4'b1111
159	2	mohor
160			`// Chains`
161			`define GLOBAL_BS_CHAIN 4'b0000
162	73	mohor	`define CPU_DEBUG_CHAIN_2 4'b0001
163			`define CPU_TEST_CHAIN 4'b0010
164	2	mohor	`define TRACE_TEST_CHAIN 4'b0011
165			`define REGISTER_SCAN_CHAIN 4'b0100
166	12	mohor	`define WISHBONE_SCAN_CHAIN 4'b0101
167	73	mohor	`define CPU_DEBUG_CHAIN_0 4'b0110
168			`define CPU_DEBUG_CHAIN_1 4'b0111
169			`define CPU_DEBUG_CHAIN_3 4'b1000
170	2	mohor
171			`// Registers addresses`
172			`define MODER_ADR 5'h00
173			`define TSEL_ADR 5'h01
174			`define QSEL_ADR 5'h02
175			`define SSEL_ADR 5'h03
176	73	mohor	`define CPUOP_ADR 5'h04
177			`define CPUSEL_ADR 5'h05
178	5	mohor	`define RECSEL_ADR 5'h10
179	47	mohor	`define MON_CNTL_ADR 5'h11
180	65	simons	`define WB_CNTL_ADR 5'h12
181	2	mohor
182
183			`// Registers default values (after reset)`
184	5	mohor	`define MODER_DEF 2'h0
185	2	mohor	`define TSEL_DEF 32'h00000000
186			`define QSEL_DEF 32'h00000000
187			`define SSEL_DEF 32'h00000000
188	73	mohor	`define CPUOP_DEF 2'h0
189	9	mohor	`define RECSEL_DEF 7'h0
190	47	mohor	`define MON_CNTL_DEF 4'h0

Browse

Tools

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [old_debug/] [rtl/] [verilog/] [dbg_defines.v] - Blame information for rev 158