URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [old_debug/] [rtl/] [verilog/] [dbg_defines.v] - Blame information for rev 71

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_defines.v                                               ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/cores/DebugInterface/              ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000,2001 Authors                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.12  2003/09/17 14:38:57  simons
// WB_CNTL register added, some syncronization fixes.
//
// Revision 1.11  2003/08/28 13:55:21  simons
// Three more chains added for cpu debug access.
//
// Revision 1.10  2003/07/31 12:19:49  simons
// Multiple cpu support added.
//
// Revision 1.9  2002/05/07 14:43:59  mohor
// mon_cntl_o signals that controls monitor mux added.
//
// Revision 1.8  2002/01/25 07:58:34  mohor
// IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
// not filled-in. Tested in hw.
//
// Revision 1.7  2001/12/06 10:08:06  mohor
// Warnings from synthesys tools fixed.
//
// Revision 1.6  2001/11/28 09:38:30  mohor
// Trace disabled by default.
//
// Revision 1.5  2001/10/15 09:55:47  mohor
// Wishbone interface added, few fixes for better performance,
// hooks for boundary scan testing added.
//
// Revision 1.4  2001/09/24 14:06:42  mohor
// Changes connected to the OpenRISC access (SPR read, SPR write).
//
// Revision 1.3  2001/09/20 10:11:25  mohor
// Working version. Few bugs fixed, comments added.
//
// Revision 1.2  2001/09/18 14:13:47  mohor
// Trace fixed. Some registers changed, trace simplified.
//
// Revision 1.1.1.1  2001/09/13 13:49:19  mohor
// Initial official release.
//
// Revision 1.3  2001/06/01 22:22:35  mohor
// This is a backup. It is not a fully working version. Not for use, yet.
//
// Revision 1.2  2001/05/18 13:10:00  mohor
// Headers changed. All additional information is now avaliable in the README.txt file.
//
// Revision 1.1.1.1  2001/05/18 06:35:08  mohor
// Initial release
//
//
 
 
 
// Enable TRACE
//`define TRACE_ENABLED  // Uncomment this define to activate the trace
 
// Define number of cpus supported by the dbg interface
`define RISC_NUM 2
 
// Define IDCODE Value
`define IDCODE_VALUE  32'h14951185
 
// Define master clock (RISC clock)
//`define       RISC_CLOCK  50   // Half period = 50 ns => MCLK = 10 Mhz
`define RISC_CLOCK  2.5   // Half period = 5 ns => MCLK = 200 Mhz
 
// Length of the Instruction register
`define IR_LENGTH       4
 
// Length of the Data register (must be equal to the longest scan chain for shifting the data in)
`define DR_LENGTH       74
 
// Length of the CHAIN ID register
`define CHAIN_ID_LENGTH 4
 
// Length of the CRC
`define CRC_LENGTH      8
 
// Trace buffer size and counter and write/read pointer width. This can be expanded when more RAM is avaliable
`define TRACECOUNTERWIDTH        5
`define TRACEBUFFERLENGTH        32 // 2^5
 
`define TRACESAMPLEWIDTH         36
 
// OpSelect width
`define OPSELECTWIDTH            3
`define OPSELECTIONCOUNTER       8    //2^3
 
// OpSelect (dbg_op_i) signal meaning
`define DEBUG_READ_0               0
`define DEBUG_WRITE_0              1
`define DEBUG_READ_1               2
`define DEBUG_WRITE_1              3
`define DEBUG_READ_2               4
`define DEBUG_WRITE_2              5
`define DEBUG_READ_3               6
`define DEBUG_WRITE_3              7
 
// Supported Instructions
`define EXTEST          4'b0000
`define SAMPLE_PRELOAD  4'b0001
`define IDCODE          4'b0010
`define CHAIN_SELECT    4'b0011
`define INTEST          4'b0100
`define CLAMP           4'b0101
`define CLAMPZ          4'b0110
`define HIGHZ           4'b0111
`define DEBUG           4'b1000
`define MBIST           4'b1001
`define BYPASS          4'b1111
 
// Chains
`define GLOBAL_BS_CHAIN     4'b0000
`define RISC_DEBUG_CHAIN_2  4'b0001
`define RISC_TEST_CHAIN     4'b0010
`define TRACE_TEST_CHAIN    4'b0011
`define REGISTER_SCAN_CHAIN 4'b0100
`define WISHBONE_SCAN_CHAIN 4'b0101
`define RISC_DEBUG_CHAIN_0  4'b0110
`define RISC_DEBUG_CHAIN_1  4'b0111
`define RISC_DEBUG_CHAIN_3  4'b1000
 
// Registers addresses
`define MODER_ADR           5'h00
`define TSEL_ADR            5'h01
`define QSEL_ADR            5'h02
`define SSEL_ADR            5'h03
`define RISCOP_ADR          5'h04
`define RISCSEL_ADR         5'h05
`define RECSEL_ADR          5'h10
`define MON_CNTL_ADR        5'h11
`define WB_CNTL_ADR         5'h12
 
 
// Registers default values (after reset)
`define MODER_DEF           2'h0
`define TSEL_DEF            32'h00000000
`define QSEL_DEF            32'h00000000
`define SSEL_DEF            32'h00000000
`define RISCOP_DEF          2'h0
`define RECSEL_DEF          7'h0
`define MON_CNTL_DEF        4'h0

Line No.	Rev	Author	Line
1	2	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_defines.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7			`//// http://www.opencores.org/cores/DebugInterface/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is avaliable in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000,2001 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	71	simons	`// Revision 1.12 2003/09/17 14:38:57 simons`
49			`// WB_CNTL register added, some syncronization fixes.`
50			`//`
51	65	simons	`// Revision 1.11 2003/08/28 13:55:21 simons`
52			`// Three more chains added for cpu debug access.`
53			`//`
54	63	simons	`// Revision 1.10 2003/07/31 12:19:49 simons`
55			`// Multiple cpu support added.`
56			`//`
57	57	simons	`// Revision 1.9 2002/05/07 14:43:59 mohor`
58			`// mon_cntl_o signals that controls monitor mux added.`
59			`//`
60	47	mohor	`// Revision 1.8 2002/01/25 07:58:34 mohor`
61			`// IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in`
62			`// not filled-in. Tested in hw.`
63			`//`
64	30	mohor	`// Revision 1.7 2001/12/06 10:08:06 mohor`
65			`// Warnings from synthesys tools fixed.`
66			`//`
67	27	mohor	`// Revision 1.6 2001/11/28 09:38:30 mohor`
68			`// Trace disabled by default.`
69			`//`
70	23	mohor	`// Revision 1.5 2001/10/15 09:55:47 mohor`
71			`// Wishbone interface added, few fixes for better performance,`
72			`// hooks for boundary scan testing added.`
73			`//`
74	12	mohor	`// Revision 1.4 2001/09/24 14:06:42 mohor`
75			`// Changes connected to the OpenRISC access (SPR read, SPR write).`
76			`//`
77	11	mohor	`// Revision 1.3 2001/09/20 10:11:25 mohor`
78			`// Working version. Few bugs fixed, comments added.`
79			`//`
80	9	mohor	`// Revision 1.2 2001/09/18 14:13:47 mohor`
81			`// Trace fixed. Some registers changed, trace simplified.`
82			`//`
83	5	mohor	`// Revision 1.1.1.1 2001/09/13 13:49:19 mohor`
84			`// Initial official release.`
85			`//`
86	2	mohor	`// Revision 1.3 2001/06/01 22:22:35 mohor`
87			`// This is a backup. It is not a fully working version. Not for use, yet.`
88			`//`
89			`// Revision 1.2 2001/05/18 13:10:00 mohor`
90			`// Headers changed. All additional information is now avaliable in the README.txt file.`
91			`//`
92			`// Revision 1.1.1.1 2001/05/18 06:35:08 mohor`
93			`// Initial release`
94			`//`
95			`//`
96
97
98
99			`// Enable TRACE`
100	23	mohor	//`define TRACE_ENABLED // Uncomment this define to activate the trace
101	2	mohor
102	57	simons	`// Define number of cpus supported by the dbg interface`
103	71	simons	`define RISC_NUM 2
104	2	mohor
105			`// Define IDCODE Value`
106	71	simons	`define IDCODE_VALUE 32'h14951185
107	2	mohor
108			`// Define master clock (RISC clock)`
109	5	mohor	//`define RISC_CLOCK 50 // Half period = 50 ns => MCLK = 10 Mhz
110			`define RISC_CLOCK 2.5 // Half period = 5 ns => MCLK = 200 Mhz
111	2	mohor
112			`// Length of the Instruction register`
113			`define IR_LENGTH 4
114
115	30	mohor	`// Length of the Data register (must be equal to the longest scan chain for shifting the data in)`
116	27	mohor	`define DR_LENGTH 74
117	2	mohor
118			`// Length of the CHAIN ID register`
119			`define CHAIN_ID_LENGTH 4
120
121			`// Length of the CRC`
122			`define CRC_LENGTH 8
123
124	9	mohor	`// Trace buffer size and counter and write/read pointer width. This can be expanded when more RAM is avaliable`
125			`define TRACECOUNTERWIDTH 5
126			`define TRACEBUFFERLENGTH 32 // 2^5
127
128	2	mohor	`define TRACESAMPLEWIDTH 36
129
130			`// OpSelect width`
131			`define OPSELECTWIDTH 3
132			`define OPSELECTIONCOUNTER 8 //2^3
133
134	11	mohor	`// OpSelect (dbg_op_i) signal meaning`
135	63	simons	`define DEBUG_READ_0 0
136			`define DEBUG_WRITE_0 1
137			`define DEBUG_READ_1 2
138			`define DEBUG_WRITE_1 3
139			`define DEBUG_READ_2 4
140			`define DEBUG_WRITE_2 5
141			`define DEBUG_READ_3 6
142			`define DEBUG_WRITE_3 7
143
144	2	mohor	`// Supported Instructions`
145	30	mohor	`define EXTEST 4'b0000
146			`define SAMPLE_PRELOAD 4'b0001
147			`define IDCODE 4'b0010
148			`define CHAIN_SELECT 4'b0011
149			`define INTEST 4'b0100
150			`define CLAMP 4'b0101
151			`define CLAMPZ 4'b0110
152			`define HIGHZ 4'b0111
153			`define DEBUG 4'b1000
154	71	simons	`define MBIST 4'b1001
155	30	mohor	`define BYPASS 4'b1111
156	2	mohor
157			`// Chains`
158			`define GLOBAL_BS_CHAIN 4'b0000
159	63	simons	`define RISC_DEBUG_CHAIN_2 4'b0001
160	2	mohor	`define RISC_TEST_CHAIN 4'b0010
161			`define TRACE_TEST_CHAIN 4'b0011
162			`define REGISTER_SCAN_CHAIN 4'b0100
163	12	mohor	`define WISHBONE_SCAN_CHAIN 4'b0101
164	63	simons	`define RISC_DEBUG_CHAIN_0 4'b0110
165			`define RISC_DEBUG_CHAIN_1 4'b0111
166			`define RISC_DEBUG_CHAIN_3 4'b1000
167	2	mohor
168			`// Registers addresses`
169			`define MODER_ADR 5'h00
170			`define TSEL_ADR 5'h01
171			`define QSEL_ADR 5'h02
172			`define SSEL_ADR 5'h03
173	5	mohor	`define RISCOP_ADR 5'h04
174	57	simons	`define RISCSEL_ADR 5'h05
175	5	mohor	`define RECSEL_ADR 5'h10
176	47	mohor	`define MON_CNTL_ADR 5'h11
177	65	simons	`define WB_CNTL_ADR 5'h12
178	2	mohor
179
180			`// Registers default values (after reset)`
181	5	mohor	`define MODER_DEF 2'h0
182	2	mohor	`define TSEL_DEF 32'h00000000
183			`define QSEL_DEF 32'h00000000
184			`define SSEL_DEF 32'h00000000
185	5	mohor	`define RISCOP_DEF 2'h0
186	9	mohor	`define RECSEL_DEF 7'h0
187	47	mohor	`define MON_CNTL_DEF 4'h0

Browse

Tools

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [old_debug/] [rtl/] [verilog/] [dbg_defines.v] - Blame information for rev 71