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1 2 mohor 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 
////  dbg_top.v                                                   ////
4 
////                                                              ////
5 
////                                                              ////
6 
////  This file is part of the SoC/OpenRISC Development Interface ////
7 
////  http://www.opencores.org/cores/DebugInterface/              ////
8 
////                                                              ////
9 
////                                                              ////
10 
////  Author(s):                                                  ////
11 
////       Igor Mohor                                             ////
12 
////       igorm@opencores.org                                    ////
13 
////                                                              ////
14 
////                                                              ////
15 
////  All additional information is avaliable in the README.txt   ////
16 
////  file.                                                       ////
17 
////                                                              ////
18 
//////////////////////////////////////////////////////////////////////
19 
////                                                              ////
20 
//// Copyright (C) 2000,2001 Authors                              ////
21 
////                                                              ////
22 
//// This source file may be used and distributed without         ////
23 
//// restriction provided that this copyright statement is not    ////
24 
//// removed from the file and that any derivative work contains  ////
25 
//// the original copyright notice and the associated disclaimer. ////
26 
////                                                              ////
27 
//// This source file is free software; you can redistribute it   ////
28 
//// and/or modify it under the terms of the GNU Lesser General   ////
29 
//// Public License as published by the Free Software Foundation; ////
30 
//// either version 2.1 of the License, or (at your option) any   ////
31 
//// later version.                                               ////
32 
////                                                              ////
33 
//// This source is distributed in the hope that it will be       ////
34 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
35 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37 
//// details.                                                     ////
38 
////                                                              ////
39 
//// You should have received a copy of the GNU Lesser General    ////
40 
//// Public License along with this source; if not, download it   ////
41 
//// from http://www.opencores.org/lgpl.shtml                     ////
42 
////                                                              ////
43 
//////////////////////////////////////////////////////////////////////
44 
//
45 
// CVS Revision History
46 
//
47 
// $Log: not supported by cvs2svn $
48 13 mohor 
//
49 
// Revision 1.6  2001/10/15 09:55:47  mohor
50 
// Wishbone interface added, few fixes for better performance,
51 
// hooks for boundary scan testing added.
52 
//
53 12 mohor 
// Revision 1.5  2001/09/24 14:06:42  mohor
54 
// Changes connected to the OpenRISC access (SPR read, SPR write).
55 
//
56 11 mohor 
// Revision 1.4  2001/09/20 10:11:25  mohor
57 
// Working version. Few bugs fixed, comments added.
58 
//
59 9 mohor 
// Revision 1.3  2001/09/19 11:55:13  mohor
60 
// Asynchronous set/reset not used in trace any more.
61 
//
62 8 mohor 
// Revision 1.2  2001/09/18 14:13:47  mohor
63 
// Trace fixed. Some registers changed, trace simplified.
64 
//
65 5 mohor 
// Revision 1.1.1.1  2001/09/13 13:49:19  mohor
66 
// Initial official release.
67 
//
68 2 mohor 
// Revision 1.3  2001/06/01 22:22:35  mohor
69 
// This is a backup. It is not a fully working version. Not for use, yet.
70 
//
71 
// Revision 1.2  2001/05/18 13:10:00  mohor
72 
// Headers changed. All additional information is now avaliable in the README.txt file.
73 
//
74 
// Revision 1.1.1.1  2001/05/18 06:35:02  mohor
75 
// Initial release
76 
//
77 
//
78 
 
79 
`include "dbg_timescale.v"
80 
`include "dbg_defines.v"
81 
 
82 
// Top module
83 9 mohor 
module dbg_top(
84 
                // JTAG pins
85 
                tms_pad_i, tck_pad_i, trst_pad_i, tdi_pad_i, tdo_pad_o,
86 12 mohor 
 
87 
                // Boundary Scan signals
88 13 mohor 
                capture_dr_o, shift_dr_o, update_dr_o, extest_selected_o, bs_chain_i,
89 9 mohor 
 
90 
                // RISC signals
91 11 mohor 
                risc_clk_i, risc_addr_o, risc_data_i, risc_data_o, wp_i,
92 
                bp_i, opselect_o, lsstatus_i, istatus_i, risc_stall_o, reset_o,
93 9 mohor 
 
94 12 mohor 
                // WISHBONE common signals
95 
                wb_rst_i, wb_clk_i,
96 
 
97 
                // WISHBONE master interface
98 
                wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,
99 
                wb_we_o, wb_ack_i, wb_cab_o, wb_err_i
100 
 
101 
 
102 2 mohor 
              );
103 
 
104 
parameter Tp = 1;
105 
 
106 9 mohor 
// JTAG pins
107 
input         tms_pad_i;                  // JTAG test mode select pad
108 
input         tck_pad_i;                  // JTAG test clock pad
109 
input         trst_pad_i;                 // JTAG test reset pad
110 
input         tdi_pad_i;                  // JTAG test data input pad
111 
output        tdo_pad_o;                  // JTAG test data output pad
112 2 mohor 
 
113 
 
114 12 mohor 
// Boundary Scan signals
115 13 mohor 
output capture_dr_o;
116 
output shift_dr_o;
117 
output update_dr_o;
118 
output extest_selected_o;
119 
input  bs_chain_i;
120 12 mohor 
 
121 
 
122 9 mohor 
// RISC signals
123 11 mohor 
input         risc_clk_i;                 // Master clock (RISC clock)
124 9 mohor 
input  [31:0] risc_data_i;                // RISC data inputs (data that is written to the RISC registers)
125 
input  [10:0] wp_i;                       // Watchpoint inputs
126 
input         bp_i;                       // Breakpoint input
127 
input  [3:0]  lsstatus_i;                 // Load/store status inputs
128 
input  [1:0]  istatus_i;                  // Instruction status inputs
129 
output [31:0] risc_addr_o;                // RISC address output (for adressing registers within RISC)
130 
output [31:0] risc_data_o;                // RISC data output (data read from risc registers)
131 
output [`OPSELECTWIDTH-1:0] opselect_o;   // Operation selection (selecting what kind of data is set to the risc_data_i)
132 
output                      risc_stall_o; // Stalls the RISC
133 11 mohor 
output                      reset_o;      // Resets the RISC
134 2 mohor 
 
135 
 
136 12 mohor 
// WISHBONE common signals
137 9 mohor 
input         wb_rst_i;                   // WISHBONE reset
138 12 mohor 
input         wb_clk_i;                   // WISHBONE clock
139 9 mohor 
 
140 12 mohor 
// WISHBONE master interface
141 
output [31:0] wb_adr_o;
142 
output [31:0] wb_dat_o;
143 
input  [31:0] wb_dat_i;
144 
output        wb_cyc_o;
145 
output        wb_stb_o;
146 
output  [3:0] wb_sel_o;
147 
output        wb_we_o;
148 
input         wb_ack_i;
149 
output        wb_cab_o;
150 
input         wb_err_i;
151 9 mohor 
 
152 12 mohor 
reg    [31:0] wb_adr_o;
153 
reg    [31:0] wb_dat_o;
154 
reg           wb_we_o;
155 
reg           wb_cyc_o;
156 
 
157 9 mohor 
// TAP states
158 2 mohor 
reg TestLogicReset;
159 
reg RunTestIdle;
160 
reg SelectDRScan;
161 
reg CaptureDR;
162 
reg ShiftDR;
163 
reg Exit1DR;
164 
reg PauseDR;
165 
reg Exit2DR;
166 
reg UpdateDR;
167 
 
168 
reg SelectIRScan;
169 
reg CaptureIR;
170 
reg ShiftIR;
171 
reg Exit1IR;
172 
reg PauseIR;
173 
reg Exit2IR;
174 
reg UpdateIR;
175 
 
176 9 mohor 
 
177 
// Defining which instruction is selected
178 2 mohor 
reg EXTESTSelected;
179 
reg SAMPLE_PRELOADSelected;
180 
reg IDCODESelected;
181 
reg CHAIN_SELECTSelected;
182 
reg INTESTSelected;
183 
reg CLAMPSelected;
184 
reg CLAMPZSelected;
185 
reg HIGHZSelected;
186 
reg DEBUGSelected;
187 
reg BYPASSSelected;
188 
 
189 9 mohor 
reg [31:0]  ADDR;
190 
reg [31:0]  DataOut;
191 
 
192 11 mohor 
reg [`OPSELECTWIDTH-1:0] opselect_o;      // Operation selection (selecting what kind of data is set to the risc_data_i)
193 
 
194 2 mohor 
reg [`CHAIN_ID_LENGTH-1:0] Chain;         // Selected chain
195 11 mohor 
reg [31:0]  RISC_DATAINLatch;             // Data from DataIn is latched one risc_clk_i clock cycle after RISC register is
196 2 mohor 
                                          // accessed for reading
197 9 mohor 
reg [31:0]  RegisterReadLatch;            // Data when reading register is latched one TCK clock after the register is read.
198 
reg         RegAccessTck;                 // Indicates access to the registers (read or write)
199 
reg         RISCAccessTck;                // Indicates access to the RISC (read or write)
200 
reg [7:0]   BitCounter;                   // Counting bits in the ShiftDR and Exit1DR stages
201 
reg         RW;                           // Read/Write bit
202 
reg         CrcMatch;                     // The crc that is shifted in and the internaly calculated crc are equal
203 2 mohor 
 
204 9 mohor 
reg         RegAccess_q;                  // Delayed signals used for accessing the registers
205 
reg         RegAccess_q2;                 // Delayed signals used for accessing the registers
206 
reg         RISCAccess_q;                 // Delayed signals used for accessing the RISC
207 
reg         RISCAccess_q2;                // Delayed signals used for accessing the RISC
208 2 mohor 
 
209 12 mohor 
reg         wb_AccessTck;                 // Indicates access to the WISHBONE
210 
reg [31:0]  WBReadLatch;                  // Data latched during WISHBONE read
211 
reg         WBErrorLatch;                 // Error latched during WISHBONE read
212 2 mohor 
 
213 9 mohor 
wire TCK = tck_pad_i;
214 
wire TMS = tms_pad_i;
215 
wire TDI = tdi_pad_i;
216 12 mohor 
wire RESET = ~trst_pad_i | wb_rst_i;      // trst_pad_i is active low
217 2 mohor 
 
218 9 mohor 
wire [31:0]             RegDataIn;        // Data from registers (read data)
219 
wire [`CRC_LENGTH-1:0]  CalculatedCrcOut; // CRC calculated in this module. This CRC is apended at the end of the TDO.
220 2 mohor 
 
221 9 mohor 
wire RiscStall_reg;                       // RISC is stalled by setting the register bit
222 
wire RiscReset_reg;                       // RISC is reset by setting the register bit
223 
wire RiscStall_trace;                     // RISC is stalled by trace module
224 
 
225 
 
226 
wire RegisterScanChain;                   // Register Scan chain selected
227 
wire RiscDebugScanChain;                  // Risc Debug Scan chain selected
228 12 mohor 
wire WishboneScanChain;                   // WISHBONE Scan chain selected
229 11 mohor 
 
230 
wire RiscStall_read_access;               // Stalling RISC because of the read access (SPR read)
231 
wire RiscStall_write_access;              // Stalling RISC because of the write access (SPR write)
232 
wire RiscStall_access;                    // Stalling RISC because of the read or write access
233 
 
234 9 mohor 
 
235 13 mohor 
assign capture_dr_o       = CaptureDR;
236 
assign shift_dr_o         = ShiftDR;
237 
assign update_dr_o        = UpdateDR;
238 
assign extest_selected_o  = EXTESTSelected;
239 
wire   BS_CHAIN_I         = bs_chain_i;
240 9 mohor 
 
241 
// This signals are used only when TRACE is used in the design
242 2 mohor 
`ifdef TRACE_ENABLED
243 9 mohor 
  wire [39:0] TraceChain;                 // Chain that comes from trace module
244 
  reg  ReadBuffer_Tck;                    // Command for incrementing the trace read pointer (synchr with TCK)
245 
  wire ReadTraceBuffer;                   // Command for incrementing the trace read pointer (synchr with MClk)
246 
  reg  ReadTraceBuffer_q;                 // Delayed command for incrementing the trace read pointer (synchr with MClk)
247 
  wire ReadTraceBufferPulse;              // Pulse for reading the trace buffer (valid for only one Mclk command)
248 2 mohor 
 
249 
  // Outputs from registers
250 9 mohor 
  wire ContinMode;                        // Trace working in continous mode
251 
  wire TraceEnable;                       // Trace enabled
252 2 mohor 
 
253 9 mohor 
  wire [10:0] WpTrigger;                  // Watchpoint starts trigger
254 
  wire        BpTrigger;                  // Breakpoint starts trigger
255 
  wire [3:0]  LSSTrigger;                 // Load/store status starts trigger
256 
  wire [1:0]  ITrigger;                   // Instruction status starts trigger
257 
  wire [1:0]  TriggerOper;                // Trigger operation
258 2 mohor 
 
259 9 mohor 
  wire        WpTriggerValid;             // Watchpoint trigger is valid
260 
  wire        BpTriggerValid;             // Breakpoint trigger is valid
261 
  wire        LSSTriggerValid;            // Load/store status trigger is valid
262 
  wire        ITriggerValid;              // Instruction status trigger is valid
263 2 mohor 
 
264 9 mohor 
  wire [10:0] WpQualif;                   // Watchpoint starts qualifier
265 
  wire        BpQualif;                   // Breakpoint starts qualifier
266 
  wire [3:0]  LSSQualif;                  // Load/store status starts qualifier
267 
  wire [1:0]  IQualif;                    // Instruction status starts qualifier
268 
  wire [1:0]  QualifOper;                 // Qualifier operation
269 2 mohor 
 
270 9 mohor 
  wire        WpQualifValid;              // Watchpoint qualifier is valid
271 
  wire        BpQualifValid;              // Breakpoint qualifier is valid
272 
  wire        LSSQualifValid;             // Load/store status qualifier is valid
273 
  wire        IQualifValid;               // Instruction status qualifier is valid
274 2 mohor 
 
275 9 mohor 
  wire [10:0] WpStop;                     // Watchpoint stops recording of the trace
276 
  wire        BpStop;                     // Breakpoint stops recording of the trace
277 
  wire [3:0]  LSSStop;                    // Load/store status stops recording of the trace
278 
  wire [1:0]  IStop;                      // Instruction status stops recording of the trace
279 
  wire [1:0]  StopOper;                   // Stop operation
280 2 mohor 
 
281 9 mohor 
  wire WpStopValid;                       // Watchpoint stop is valid
282 
  wire BpStopValid;                       // Breakpoint stop is valid
283 
  wire LSSStopValid;                      // Load/store status stop is valid
284 
  wire IStopValid;                        // Instruction status stop is valid
285 2 mohor 
 
286 9 mohor 
  wire RecordPC;                          // Recording program counter
287 
  wire RecordLSEA;                        // Recording load/store effective address
288 
  wire RecordLDATA;                       // Recording load data
289 
  wire RecordSDATA;                       // Recording store data
290 
  wire RecordReadSPR;                     // Recording read SPR
291 
  wire RecordWriteSPR;                    // Recording write SPR
292 
  wire RecordINSTR;                       // Recording instruction
293 2 mohor 
 
294 
  // End: Outputs from registers
295 
 
296 9 mohor 
  wire TraceTestScanChain;                // Trace Test Scan chain selected
297 
  wire [47:0] Trace_Data;                 // Trace data
298 2 mohor 
 
299 11 mohor 
  wire [`OPSELECTWIDTH-1:0]opselect_trace;// Operation selection (trace selecting what kind of
300 
                                          // data is set to the risc_data_i)
301 
 
302 2 mohor 
`endif
303 
 
304 
 
305 
/**********************************************************************************
306 
*                                                                                 *
307 
*   TAP State Machine: Fully JTAG compliant                                       *
308 
*                                                                                 *
309 
**********************************************************************************/
310 
 
311 
// TestLogicReset state
312 
always @ (posedge TCK or posedge RESET)
313 
begin
314 
  if(RESET)
315 
    TestLogicReset<=#Tp 1;
316 
  else
317 
    begin
318 
      if(TMS & (TestLogicReset | SelectIRScan))
319 
        TestLogicReset<=#Tp 1;
320 
      else
321 
        TestLogicReset<=#Tp 0;
322 
    end
323 
end
324 
 
325 
// RunTestIdle state
326 
always @ (posedge TCK or posedge RESET)
327 
begin
328 
  if(RESET)
329 
    RunTestIdle<=#Tp 0;
330 
  else
331 
    begin
332 
      if(~TMS & (TestLogicReset | RunTestIdle | UpdateDR | UpdateIR))
333 
        RunTestIdle<=#Tp 1;
334 
      else
335 
        RunTestIdle<=#Tp 0;
336 
    end
337 
end
338 
 
339 
// SelectDRScan state
340 
always @ (posedge TCK or posedge RESET)
341 
begin
342 
  if(RESET)
343 
    SelectDRScan<=#Tp 0;
344 
  else
345 
    begin
346 
      if(TMS & (RunTestIdle | UpdateDR | UpdateIR))
347 
        SelectDRScan<=#Tp 1;
348 
      else
349 
        SelectDRScan<=#Tp 0;
350 
    end
351 
end
352 
 
353 
// CaptureDR state
354 
always @ (posedge TCK or posedge RESET)
355 
begin
356 
  if(RESET)
357 
    CaptureDR<=#Tp 0;
358 
  else
359 
    begin
360 
      if(~TMS & SelectDRScan)
361 
        CaptureDR<=#Tp 1;
362 
      else
363 
        CaptureDR<=#Tp 0;
364 
    end
365 
end
366 
 
367 
// ShiftDR state
368 
always @ (posedge TCK or posedge RESET)
369 
begin
370 
  if(RESET)
371 
    ShiftDR<=#Tp 0;
372 
  else
373 
    begin
374 
      if(~TMS & (CaptureDR | ShiftDR | Exit2DR))
375 
        ShiftDR<=#Tp 1;
376 
      else
377 
        ShiftDR<=#Tp 0;
378 
    end
379 
end
380 
 
381 
// Exit1DR state
382 
always @ (posedge TCK or posedge RESET)
383 
begin
384 
  if(RESET)
385 
    Exit1DR<=#Tp 0;
386 
  else
387 
    begin
388 
      if(TMS & (CaptureDR | ShiftDR))
389 
        Exit1DR<=#Tp 1;
390 
      else
391 
        Exit1DR<=#Tp 0;
392 
    end
393 
end
394 
 
395 
// PauseDR state
396 
always @ (posedge TCK or posedge RESET)
397 
begin
398 
  if(RESET)
399 
    PauseDR<=#Tp 0;
400 
  else
401 
    begin
402 
      if(~TMS & (Exit1DR | PauseDR))
403 
        PauseDR<=#Tp 1;
404 
      else
405 
        PauseDR<=#Tp 0;
406 
    end
407 
end
408 
 
409 
// Exit2DR state
410 
always @ (posedge TCK or posedge RESET)
411 
begin
412 
  if(RESET)
413 
    Exit2DR<=#Tp 0;
414 
  else
415 
    begin
416 
      if(TMS & PauseDR)
417 
        Exit2DR<=#Tp 1;
418 
      else
419 
        Exit2DR<=#Tp 0;
420 
    end
421 
end
422 
 
423 
// UpdateDR state
424 
always @ (posedge TCK or posedge RESET)
425 
begin
426 
  if(RESET)
427 
    UpdateDR<=#Tp 0;
428 
  else
429 
    begin
430 
      if(TMS & (Exit1DR | Exit2DR))
431 
        UpdateDR<=#Tp 1;
432 
      else
433 
        UpdateDR<=#Tp 0;
434 
    end
435 
end
436 
 
437 9 mohor 
// Delayed UpdateDR state
438 2 mohor 
reg UpdateDR_q;
439 
always @ (posedge TCK)
440 
begin
441 
  UpdateDR_q<=#Tp UpdateDR;
442 
end
443 
 
444 
 
445 
// SelectIRScan state
446 
always @ (posedge TCK or posedge RESET)
447 
begin
448 
  if(RESET)
449 
    SelectIRScan<=#Tp 0;
450 
  else
451 
    begin
452 
      if(TMS & SelectDRScan)
453 
        SelectIRScan<=#Tp 1;
454 
      else
455 
        SelectIRScan<=#Tp 0;
456 
    end
457 
end
458 
 
459 
// CaptureIR state
460 
always @ (posedge TCK or posedge RESET)
461 
begin
462 
  if(RESET)
463 
    CaptureIR<=#Tp 0;
464 
  else
465 
    begin
466 
      if(~TMS & SelectIRScan)
467 
        CaptureIR<=#Tp 1;
468 
      else
469 
        CaptureIR<=#Tp 0;
470 
    end
471 
end
472 
 
473 
// ShiftIR state
474 
always @ (posedge TCK or posedge RESET)
475 
begin
476 
  if(RESET)
477 
    ShiftIR<=#Tp 0;
478 
  else
479 
    begin
480 
      if(~TMS & (CaptureIR | ShiftIR | Exit2IR))
481 
        ShiftIR<=#Tp 1;
482 
      else
483 
        ShiftIR<=#Tp 0;
484 
    end
485 
end
486 
 
487 
// Exit1IR state
488 
always @ (posedge TCK or posedge RESET)
489 
begin
490 
  if(RESET)
491 
    Exit1IR<=#Tp 0;
492 
  else
493 
    begin
494 
      if(TMS & (CaptureIR | ShiftIR))
495 
        Exit1IR<=#Tp 1;
496 
      else
497 
        Exit1IR<=#Tp 0;
498 
    end
499 
end
500 
 
501 
// PauseIR state
502 
always @ (posedge TCK or posedge RESET)
503 
begin
504 
  if(RESET)
505 
    PauseIR<=#Tp 0;
506 
  else
507 
    begin
508 
      if(~TMS & (Exit1IR | PauseIR))
509 
        PauseIR<=#Tp 1;
510 
      else
511 
        PauseIR<=#Tp 0;
512 
    end
513 
end
514 
 
515 
// Exit2IR state
516 
always @ (posedge TCK or posedge RESET)
517 
begin
518 
  if(RESET)
519 
    Exit2IR<=#Tp 0;
520 
  else
521 
    begin
522 
      if(TMS & PauseIR)
523 
        Exit2IR<=#Tp 1;
524 
      else
525 
        Exit2IR<=#Tp 0;
526 
    end
527 
end
528 
 
529 
// UpdateIR state
530 
always @ (posedge TCK or posedge RESET)
531 
begin
532 
  if(RESET)
533 
    UpdateIR<=#Tp 0;
534 
  else
535 
    begin
536 
      if(TMS & (Exit1IR | Exit2IR))
537 
        UpdateIR<=#Tp 1;
538 
      else
539 
        UpdateIR<=#Tp 0;
540 
    end
541 
end
542 
 
543 
/**********************************************************************************
544 
*                                                                                 *
545 
*   End: TAP State Machine                                                        *
546 
*                                                                                 *
547 
**********************************************************************************/
548 
 
549 
 
550 
 
551 
/**********************************************************************************
552 
*                                                                                 *
553 
*   JTAG_IR:  JTAG Instruction Register                                           *
554 
*                                                                                 *
555 
**********************************************************************************/
556 9 mohor 
wire [1:0]Status = 2'b10;     // Holds current chip status. Core should return this status. For now a constant is used.
557 2 mohor 
 
558 9 mohor 
reg [`IR_LENGTH-1:0]JTAG_IR;  // Instruction register
559 
reg [`IR_LENGTH-1:0]LatchedJTAG_IR;
560 
 
561 2 mohor 
reg TDOInstruction;
562 
 
563 
always @ (posedge TCK or posedge RESET)
564 
begin
565 
  if(RESET)
566 
    JTAG_IR[`IR_LENGTH-1:0] <= #Tp 0;
567 
  else
568 
    begin
569 
      if(CaptureIR)
570 
        begin
571 
          JTAG_IR[1:0] <= #Tp 2'b01;       // This value is fixed for easier fault detection
572 
          JTAG_IR[3:2] <= #Tp Status[1:0]; // Current status of chip
573 
        end
574 
      else
575 
        begin
576 
          if(ShiftIR)
577 
            begin
578 
              JTAG_IR[`IR_LENGTH-1:0] <= #Tp {TDI, JTAG_IR[`IR_LENGTH-1:1]};
579 
            end
580 
        end
581 
    end
582 
end
583 
 
584 
 
585 
//TDO is changing on the falling edge of TCK
586 
always @ (negedge TCK)
587 
begin
588 
  if(ShiftIR)
589 
    TDOInstruction <= #Tp JTAG_IR[0];
590 
end
591 9 mohor 
 
592 2 mohor 
/**********************************************************************************
593 
*                                                                                 *
594 
*   End: JTAG_IR                                                                  *
595 
*                                                                                 *
596 
**********************************************************************************/
597 
 
598 
 
599 
/**********************************************************************************
600 
*                                                                                 *
601 
*   JTAG_DR:  JTAG Data Register                                                  *
602 
*                                                                                 *
603 
**********************************************************************************/
604 
wire [31:0] IDCodeValue = `IDCODE_VALUE;  // IDCODE value is 32-bit long.
605 
 
606 
reg [`DR_LENGTH-1:0]JTAG_DR_IN;    // Data register
607 
reg TDOData;
608 
 
609 
 
610 
always @ (posedge TCK or posedge RESET)
611 
begin
612 
  if(RESET)
613 
    JTAG_DR_IN[`DR_LENGTH-1:0]<=#Tp 0;
614 
  else
615 
  if(ShiftDR)
616 
    JTAG_DR_IN[BitCounter]<=#Tp TDI;
617 
end
618 
 
619 
wire [72:0] RISC_Data;
620 
wire [45:0] Register_Data;
621 12 mohor 
wire [72:0] WISHBONE_Data;
622 
wire wb_Access_wbClk;
623 2 mohor 
 
624 
assign RISC_Data      = {CalculatedCrcOut, RISC_DATAINLatch, 33'h0};
625 
assign Register_Data  = {CalculatedCrcOut, RegisterReadLatch, 6'h0};
626 12 mohor 
assign WISHBONE_Data  = {CalculatedCrcOut, WBReadLatch, 32'h0, WBErrorLatch};
627 2 mohor 
 
628 12 mohor 
 
629 2 mohor 
`ifdef TRACE_ENABLED
630 
  assign Trace_Data     = {CalculatedCrcOut, TraceChain};
631 
`endif
632 
 
633 
//TDO is changing on the falling edge of TCK
634 
always @ (negedge TCK or posedge RESET)
635 
begin
636 
  if(RESET)
637 
    begin
638 
      TDOData <= #Tp 0;
639 
      `ifdef TRACE_ENABLED
640 
      ReadBuffer_Tck<=#Tp 0;
641 
      `endif
642 
    end
643 
  else
644 
  if(UpdateDR)
645 
    begin
646 
      TDOData <= #Tp CrcMatch;
647 
      `ifdef TRACE_ENABLED
648 9 mohor 
      if(DEBUGSelected & TraceTestScanChain & TraceChain[0])  // Sample in the trace buffer is valid
649 
        ReadBuffer_Tck<=#Tp 1;                                // Increment read pointer
650 2 mohor 
      `endif
651 
    end
652 
  else
653 
    begin
654 
      if(ShiftDR)
655 
        begin
656 
          if(IDCODESelected)
657 9 mohor 
            TDOData <= #Tp IDCodeValue[BitCounter];           // IDCODE is shifted out
658 2 mohor 
          else
659 
          if(CHAIN_SELECTSelected)
660 
            TDOData <= #Tp 0;
661 
          else
662 
          if(DEBUGSelected)
663 
            begin
664 
              if(RiscDebugScanChain)
665 9 mohor 
                TDOData <= #Tp RISC_Data[BitCounter];         // Data read from RISC in the previous cycle is shifted out
666 2 mohor 
              else
667 
              if(RegisterScanChain)
668 9 mohor 
                TDOData <= #Tp Register_Data[BitCounter];     // Data read from register in the previous cycle is shifted out
669 12 mohor 
              else
670 
              if(WishboneScanChain)
671 
                TDOData <= #Tp WISHBONE_Data[BitCounter];     // Data read from the WISHBONE slave
672 2 mohor 
              `ifdef TRACE_ENABLED
673 
              else
674 
              if(TraceTestScanChain)
675 9 mohor 
                TDOData <= #Tp Trace_Data[BitCounter];        // Data from the trace buffer is shifted out
676 2 mohor 
              `endif
677 
            end
678 
        end
679 
      else
680 
        begin
681 
          TDOData <= #Tp 0;
682 
          `ifdef TRACE_ENABLED
683 
          ReadBuffer_Tck<=#Tp 0;
684 
          `endif
685 
        end
686 
    end
687 
end
688 
 
689 
/**********************************************************************************
690 
*                                                                                 *
691 
*   End: JTAG_DR                                                                  *
692 
*                                                                                 *
693 
**********************************************************************************/
694 
 
695 
 
696 
 
697 
/**********************************************************************************
698 
*                                                                                 *
699 
*   CHAIN_SELECT logic                                                            *
700 
*                                                                                 *
701 
**********************************************************************************/
702 
always @ (posedge TCK or posedge RESET)
703 
begin
704 
  if(RESET)
705 9 mohor 
    Chain[`CHAIN_ID_LENGTH-1:0]<=#Tp `GLOBAL_BS_CHAIN;  // Global BS chain is selected after reset
706 2 mohor 
  else
707 
  if(UpdateDR & CHAIN_SELECTSelected & CrcMatch)
708 9 mohor 
    Chain[`CHAIN_ID_LENGTH-1:0]<=#Tp JTAG_DR_IN[3:0];   // New chain is selected
709 2 mohor 
end
710 
 
711 
 
712 
 
713 
/**********************************************************************************
714 
*                                                                                 *
715 
*   Register read/write logic                                                     *
716 
*   RISC registers read/write logic                                               *
717 
*                                                                                 *
718 
**********************************************************************************/
719 
always @ (posedge TCK or posedge RESET)
720 
begin
721 
  if(RESET)
722 
    begin
723 
      ADDR[31:0]        <=#Tp 32'h0;
724 
      DataOut[31:0]     <=#Tp 32'h0;
725 
      RW                <=#Tp 1'b0;
726 
      RegAccessTck      <=#Tp 1'b0;
727 
      RISCAccessTck     <=#Tp 1'b0;
728 12 mohor 
      wb_adr_o          <=#Tp 32'h0;
729 
      wb_we_o           <=#Tp 1'h0;
730 
      wb_dat_o          <=#Tp 32'h0;
731 
      wb_AccessTck      <=#Tp 1'h0;
732 2 mohor 
    end
733 
  else
734 
  if(UpdateDR & DEBUGSelected & CrcMatch)
735 
    begin
736 
      if(RegisterScanChain)
737 
        begin
738 
          ADDR[4:0]         <=#Tp JTAG_DR_IN[4:0];    // Latching address for register access
739 
          RW                <=#Tp JTAG_DR_IN[5];      // latch R/W bit
740 
          DataOut[31:0]     <=#Tp JTAG_DR_IN[37:6];   // latch data for write
741 
          RegAccessTck      <=#Tp 1'b1;
742 
        end
743 
      else
744 
      if(RiscDebugScanChain)
745 
        begin
746 
          ADDR[31:0]        <=#Tp JTAG_DR_IN[31:0];   // Latching address for RISC register access
747 
          RW                <=#Tp JTAG_DR_IN[32];     // latch R/W bit
748 
          DataOut[31:0]     <=#Tp JTAG_DR_IN[64:33];  // latch data for write
749 
          RISCAccessTck     <=#Tp 1'b1;
750 
        end
751 12 mohor 
      else
752 
      if(WishboneScanChain)
753 
        begin
754 
          wb_adr_o          <=#Tp JTAG_DR_IN[31:0];   // Latching address for WISHBONE slave access
755 
          wb_we_o           <=#Tp JTAG_DR_IN[32];     // latch R/W bit
756 
          wb_dat_o          <=#Tp JTAG_DR_IN[64:33];  // latch data for write
757 
          wb_AccessTck      <=#Tp 1'b1;               //
758 
        end
759 2 mohor 
    end
760 
  else
761 
    begin
762 
      RegAccessTck      <=#Tp 1'b0;       // This signals are valid for one TCK clock period only
763 
      RISCAccessTck     <=#Tp 1'b0;
764 12 mohor 
      wb_AccessTck      <=#Tp 1'b0;
765 2 mohor 
    end
766 
end
767 
 
768 12 mohor 
assign wb_sel_o[3:0] = 4'hf;
769 
assign wb_cab_o = 1'b0;
770 9 mohor 
 
771 2 mohor 
 
772 11 mohor 
// Synchronizing the RegAccess signal to risc_clk_i clock
773 
dbg_sync_clk1_clk2 syn1 (.clk1(risc_clk_i),   .clk2(TCK),           .reset1(RESET),  .reset2(RESET),
774 2 mohor 
                         .set2(RegAccessTck), .sync_out(RegAccess)
775 
                        );
776 
 
777 11 mohor 
// Synchronizing the RISCAccess signal to risc_clk_i clock
778 
dbg_sync_clk1_clk2 syn2 (.clk1(risc_clk_i),    .clk2(TCK),           .reset1(RESET),  .reset2(RESET),
779 2 mohor 
                         .set2(RISCAccessTck), .sync_out(RISCAccess)
780 
                        );
781 
 
782 
 
783 12 mohor 
// Synchronizing the wb_Access signal to wishbone clock
784 
dbg_sync_clk1_clk2 syn3 (.clk1(wb_clk_i),      .clk2(TCK),          .reset1(RESET),  .reset2(RESET),
785 
                         .set2(wb_AccessTck), .sync_out(wb_Access_wbClk)
786 
                        );
787 
 
788 
 
789 
 
790 
 
791 
 
792 9 mohor 
// Delayed signals used for accessing registers and RISC
793 11 mohor 
always @ (posedge risc_clk_i or posedge RESET)
794 2 mohor 
begin
795 
  if(RESET)
796 
    begin
797 
      RegAccess_q   <=#Tp 1'b0;
798 
      RegAccess_q2  <=#Tp 1'b0;
799 
      RISCAccess_q  <=#Tp 1'b0;
800 
      RISCAccess_q2 <=#Tp 1'b0;
801 
    end
802 
  else
803 
    begin
804 
      RegAccess_q   <=#Tp RegAccess;
805 
      RegAccess_q2  <=#Tp RegAccess_q;
806 
      RISCAccess_q  <=#Tp RISCAccess;
807 
      RISCAccess_q2 <=#Tp RISCAccess_q;
808 
    end
809 
end
810 
 
811 9 mohor 
 
812 2 mohor 
// Latching data read from registers
813 11 mohor 
always @ (posedge risc_clk_i or posedge RESET)
814 2 mohor 
begin
815 
  if(RESET)
816 
    RegisterReadLatch[31:0]<=#Tp 0;
817 
  else
818 
  if(RegAccess_q & ~RegAccess_q2)
819 
    RegisterReadLatch[31:0]<=#Tp RegDataIn[31:0];
820 
end
821 
 
822 
 
823 9 mohor 
// Chip select and read/write signals for accessing RISC
824 11 mohor 
assign RiscStall_write_access = RISCAccess & ~RISCAccess_q  &  RW;
825 
assign RiscStall_read_access  = RISCAccess & ~RISCAccess_q2 & ~RW;
826 
assign RiscStall_access = RiscStall_write_access | RiscStall_read_access;
827 2 mohor 
 
828 
 
829 12 mohor 
reg wb_Access_wbClk_q;
830 
// Delayed signals used for accessing WISHBONE
831 
always @ (posedge wb_clk_i or posedge RESET)
832 
begin
833 
  if(RESET)
834 
    wb_Access_wbClk_q <=#Tp 1'b0;
835 
  else
836 
    wb_Access_wbClk_q <=#Tp wb_Access_wbClk;
837 
end
838 
 
839 
always @ (posedge wb_clk_i or posedge RESET)
840 
begin
841 
  if(RESET)
842 
    wb_cyc_o <=#Tp 1'b0;
843 
  else
844 
  if(wb_Access_wbClk & ~wb_Access_wbClk_q & ~(wb_ack_i | wb_err_i))
845 
    wb_cyc_o <=#Tp 1'b1;
846 
  else
847 
  if(wb_ack_i | wb_err_i)
848 
    wb_cyc_o <=#Tp 1'b0;
849 
end
850 
 
851 
assign wb_stb_o = wb_cyc_o;
852 
 
853 
 
854 
// Latching data read from registers
855 
always @ (posedge risc_clk_i or posedge RESET)
856 
begin
857 
  if(RESET)
858 
    WBReadLatch[31:0]<=#Tp 32'h0;
859 
  else
860 
  if(wb_ack_i)
861 
    WBReadLatch[31:0]<=#Tp wb_dat_i[31:0];
862 
end
863 
 
864 
// Latching WISHBONE error cycle
865 
always @ (posedge wb_clk_i or posedge RESET)
866 
begin
867 
  if(RESET)
868 
    WBErrorLatch<=#Tp 1'b0;
869 
  else
870 
  if(wb_err_i)
871 
    WBErrorLatch<=#Tp 1'b1;     // Latching wb_err_i while performing WISHBONE access
872 
  if(wb_ack_i)
873 
    WBErrorLatch<=#Tp 1'b0;     // Clearing status
874 
end
875 
 
876 
 
877 9 mohor 
// Whan enabled, TRACE stalls RISC while saving data to the trace buffer.
878 5 mohor 
`ifdef TRACE_ENABLED
879 11 mohor 
  assign  risc_stall_o = RiscStall_access | RiscStall_reg | RiscStall_trace ;
880 5 mohor 
`else
881 12 mohor 
  assign  risc_stall_o = RiscStall_access | RiscStall_reg;
882 5 mohor 
`endif
883 
 
884 11 mohor 
assign  reset_o = RiscReset_reg;
885 5 mohor 
 
886 
 
887 12 mohor 
`ifdef TRACE_ENABLED
888 11 mohor 
always @ (RiscStall_write_access or RiscStall_read_access or opselect_trace)
889 12 mohor 
`else
890 
always @ (RiscStall_write_access or RiscStall_read_access)
891 
`endif
892 11 mohor 
begin
893 
  if(RiscStall_write_access)
894 
    opselect_o = `DEBUG_WRITE_SPR;  // Write spr
895 
  else
896 
  if(RiscStall_read_access)
897 
    opselect_o = `DEBUG_READ_SPR;   // Read spr
898 
  else
899 12 mohor 
`ifdef TRACE_ENABLED
900 11 mohor 
    opselect_o = opselect_trace;
901 12 mohor 
`else
902 
    opselect_o = 3'h0;
903 
`endif
904 11 mohor 
end
905 9 mohor 
 
906 11 mohor 
 
907 
 
908 2 mohor 
// Latching data read from RISC
909 11 mohor 
always @ (posedge risc_clk_i or posedge RESET)
910 2 mohor 
begin
911 
  if(RESET)
912 
    RISC_DATAINLatch[31:0]<=#Tp 0;
913 
  else
914 
  if(RISCAccess_q & ~RISCAccess_q2)
915 12 mohor 
    RISC_DATAINLatch[31:0]<=#Tp risc_data_i[31:0];
916 2 mohor 
end
917 
 
918 12 mohor 
assign risc_addr_o = ADDR;
919 
assign risc_data_o = DataOut;
920 2 mohor 
 
921 
 
922 
 
923 
/**********************************************************************************
924 
*                                                                                 *
925 
*   Read Trace buffer logic                                                       *
926 
*                                                                                 *
927 
**********************************************************************************/
928 
`ifdef TRACE_ENABLED
929 
 
930 9 mohor 
 
931 11 mohor 
// Synchronizing the trace read buffer signal to risc_clk_i clock
932 12 mohor 
dbg_sync_clk1_clk2 syn4 (.clk1(risc_clk_i),     .clk2(TCK),           .reset1(RESET),  .reset2(RESET),
933 9 mohor 
                         .set2(ReadBuffer_Tck), .sync_out(ReadTraceBuffer)
934 
                        );
935 
 
936 
 
937 
 
938 11 mohor 
  always @(posedge risc_clk_i or posedge RESET)
939 2 mohor 
  begin
940 9 mohor 
    if(RESET)
941 
      ReadTraceBuffer_q <=#Tp 0;
942 2 mohor 
    else
943 9 mohor 
      ReadTraceBuffer_q <=#Tp ReadTraceBuffer;
944 2 mohor 
  end
945 9 mohor 
 
946 
  assign ReadTraceBufferPulse = ReadTraceBuffer & ~ReadTraceBuffer_q;
947 
 
948 2 mohor 
`endif
949 
 
950 
/**********************************************************************************
951 
*                                                                                 *
952 
*   End: Read Trace buffer logic                                                  *
953 
*                                                                                 *
954 
**********************************************************************************/
955 
 
956 
 
957 
/**********************************************************************************
958 
*                                                                                 *
959 
*   Bypass logic                                                                  *
960 
*                                                                                 *
961 
**********************************************************************************/
962 
reg BypassRegister;
963 
reg TDOBypassed;
964 
 
965 
always @ (posedge TCK)
966 
begin
967 
  if(ShiftDR)
968 
    BypassRegister<=#Tp TDI;
969 
end
970 
 
971 
always @ (negedge TCK)
972 
begin
973 
    TDOBypassed<=#Tp BypassRegister;
974 
end
975 
/**********************************************************************************
976 
*                                                                                 *
977 
*   End: Bypass logic                                                             *
978 
*                                                                                 *
979 
**********************************************************************************/
980 
 
981 
 
982 
 
983 
 
984 
 
985 
/**********************************************************************************
986 
*                                                                                 *
987 
*   Activating Instructions                                                       *
988 
*                                                                                 *
989 
**********************************************************************************/
990 
 
991 
// Updating JTAG_IR (Instruction Register)
992 
always @ (posedge TCK or posedge RESET)
993 
begin
994 
  if(RESET)
995 9 mohor 
    LatchedJTAG_IR <=#Tp `IDCODE;   // IDCODE selected after reset
996 2 mohor 
  else
997 9 mohor 
  if(UpdateIR)
998 
    LatchedJTAG_IR <=#Tp JTAG_IR;
999 2 mohor 
end
1000 
 
1001 
 
1002 9 mohor 
 
1003 
// Updating JTAG_IR (Instruction Register)
1004 
always @ (LatchedJTAG_IR)
1005 
begin
1006 
  EXTESTSelected          = 0;
1007 
  SAMPLE_PRELOADSelected  = 0;
1008 
  IDCODESelected          = 0;
1009 
  CHAIN_SELECTSelected    = 0;
1010 
  INTESTSelected          = 0;
1011 
  CLAMPSelected           = 0;
1012 
  CLAMPZSelected          = 0;
1013 
  HIGHZSelected           = 0;
1014 
  DEBUGSelected           = 0;
1015 
  BYPASSSelected          = 0;
1016 
 
1017 
  case(LatchedJTAG_IR)
1018 
    `EXTEST:            EXTESTSelected          = 1;    // External test
1019 
    `SAMPLE_PRELOAD:    SAMPLE_PRELOADSelected  = 1;    // Sample preload
1020 
    `IDCODE:            IDCODESelected          = 1;    // ID Code
1021 
    `CHAIN_SELECT:      CHAIN_SELECTSelected    = 1;    // Chain select
1022 
    `INTEST:            INTESTSelected          = 1;    // Internal test
1023 
    `CLAMP:             CLAMPSelected           = 1;    // Clamp
1024 
    `CLAMPZ:            CLAMPZSelected          = 1;    // ClampZ
1025 
    `HIGHZ:             HIGHZSelected           = 1;    // High Z
1026 
    `DEBUG:             DEBUGSelected           = 1;    // Debug
1027 
    `BYPASS:            BYPASSSelected          = 1;    // BYPASS
1028 
    default:            BYPASSSelected          = 1;    // BYPASS
1029 
  endcase
1030 
end
1031 
 
1032 
 
1033 5 mohor 
/**********************************************************************************
1034 9 mohor 
*                                                                                 *
1035 
*   Multiplexing TDO and Tristate control                                         *
1036 
*                                                                                 *
1037 5 mohor 
**********************************************************************************/
1038 
wire TDOShifted;
1039 
assign TDOShifted = (ShiftIR | Exit1IR)? TDOInstruction : TDOData;
1040 
/**********************************************************************************
1041 9 mohor 
*                                                                                 *
1042 
*   End:  Multiplexing TDO and Tristate control                                   *
1043 
*                                                                                 *
1044 5 mohor 
**********************************************************************************/
1045 
 
1046 
 
1047 
 
1048 9 mohor 
// This multiplexer can be expanded with number of user registers
1049 5 mohor 
reg TDOMuxed;
1050 12 mohor 
always @ (JTAG_IR or TDOShifted or TDOBypassed or BS_CHAIN_I)
1051 2 mohor 
begin
1052 
  case(JTAG_IR)
1053 
    `IDCODE: // Reading ID code
1054 
      begin
1055 
        TDOMuxed<=#Tp TDOShifted;
1056 
      end
1057 
    `CHAIN_SELECT: // Selecting the chain
1058 
      begin
1059 
        TDOMuxed<=#Tp TDOShifted;
1060 
      end
1061 
    `DEBUG: // Debug
1062 
      begin
1063 
        TDOMuxed<=#Tp TDOShifted;
1064 
      end
1065 12 mohor 
    `SAMPLE_PRELOAD:  // Sampling/Preloading
1066 
      begin
1067 
        TDOMuxed<=#Tp BS_CHAIN_I;
1068 
      end
1069 
    `EXTEST:  // External test
1070 
      begin
1071 
        TDOMuxed<=#Tp BS_CHAIN_I;
1072 
      end
1073 2 mohor 
    default:  // BYPASS instruction
1074 
      begin
1075 
        TDOMuxed<=#Tp TDOBypassed;
1076 
      end
1077 
  endcase
1078 
end
1079 
 
1080 9 mohor 
// Tristate control for tdo_pad_o pin
1081 
assign tdo_pad_o = (ShiftIR | ShiftDR | Exit1IR | Exit1DR | UpdateDR)? TDOMuxed : 1'bz;
1082 2 mohor 
 
1083 
/**********************************************************************************
1084 
*                                                                                 *
1085 
*   End: Activating Instructions                                                  *
1086 
*                                                                                 *
1087 
**********************************************************************************/
1088 
 
1089 
/**********************************************************************************
1090 
*                                                                                 *
1091 
*   Bit counter                                                                   *
1092 
*                                                                                 *
1093 
**********************************************************************************/
1094 
 
1095 
 
1096 
always @ (posedge TCK or posedge RESET)
1097 
begin
1098 
  if(RESET)
1099 
    BitCounter[7:0]<=#Tp 0;
1100 
  else
1101 
  if(ShiftDR)
1102 
    BitCounter[7:0]<=#Tp BitCounter[7:0]+1;
1103 
  else
1104 
  if(UpdateDR)
1105 
    BitCounter[7:0]<=#Tp 0;
1106 
end
1107 
 
1108 
 
1109 
 
1110 
/**********************************************************************************
1111 
*                                                                                 *
1112 
*   End: Bit counter                                                              *
1113 
*                                                                                 *
1114 
**********************************************************************************/
1115 
 
1116 
 
1117 
 
1118 
/**********************************************************************************
1119 
*                                                                                 *
1120 
*   Connecting Registers                                                          *
1121 
*                                                                                 *
1122 
**********************************************************************************/
1123 
dbg_registers dbgregs(.DataIn(DataOut[31:0]), .DataOut(RegDataIn[31:0]),
1124 11 mohor 
                      .Address(ADDR[4:0]), .RW(RW), .Access(RegAccess & ~RegAccess_q), .Clk(risc_clk_i),
1125 12 mohor 
                      .Bp(bp_i), .Reset(wb_rst_i),
1126 2 mohor 
                      `ifdef TRACE_ENABLED
1127 5 mohor 
                      .ContinMode(ContinMode), .TraceEnable(TraceEnable),
1128 2 mohor 
                      .WpTrigger(WpTrigger), .BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger),
1129 
                      .ITrigger(ITrigger), .TriggerOper(TriggerOper), .WpQualif(WpQualif),
1130 
                      .BpQualif(BpQualif), .LSSQualif(LSSQualif), .IQualif(IQualif),
1131 5 mohor 
                      .QualifOper(QualifOper), .RecordPC(RecordPC),
1132 
                      .RecordLSEA(RecordLSEA), .RecordLDATA(RecordLDATA),
1133 
                      .RecordSDATA(RecordSDATA), .RecordReadSPR(RecordReadSPR),
1134 
                      .RecordWriteSPR(RecordWriteSPR), .RecordINSTR(RecordINSTR),
1135 
                      .WpTriggerValid(WpTriggerValid),
1136 2 mohor 
                      .BpTriggerValid(BpTriggerValid), .LSSTriggerValid(LSSTriggerValid),
1137 
                      .ITriggerValid(ITriggerValid), .WpQualifValid(WpQualifValid),
1138 
                      .BpQualifValid(BpQualifValid), .LSSQualifValid(LSSQualifValid),
1139 
                      .IQualifValid(IQualifValid),
1140 
                      .WpStop(WpStop), .BpStop(BpStop), .LSSStop(LSSStop), .IStop(IStop),
1141 5 mohor 
                      .StopOper(StopOper), .WpStopValid(WpStopValid), .BpStopValid(BpStopValid),
1142 
                      .LSSStopValid(LSSStopValid), .IStopValid(IStopValid),
1143 2 mohor 
                      `endif
1144 5 mohor 
                      .RiscStall(RiscStall_reg), .RiscReset(RiscReset_reg)
1145 
 
1146 2 mohor 
                     );
1147 
 
1148 
/**********************************************************************************
1149 
*                                                                                 *
1150 
*   End: Connecting Registers                                                     *
1151 
*                                                                                 *
1152 
**********************************************************************************/
1153 
 
1154 
 
1155 
/**********************************************************************************
1156 
*                                                                                 *
1157 
*   Connecting CRC module                                                         *
1158 
*                                                                                 *
1159 
**********************************************************************************/
1160 9 mohor 
wire AsyncResetCrc = RESET;
1161 
wire SyncResetCrc = UpdateDR_q;
1162 2 mohor 
wire [7:0] CalculatedCrcIn;     // crc calculated from the input data (shifted in)
1163 
 
1164 
wire EnableCrcIn = ShiftDR &
1165 9 mohor 
                  ( (CHAIN_SELECTSelected                 & (BitCounter<4))  |
1166 2 mohor 
                    ((DEBUGSelected & RegisterScanChain)  & (BitCounter<38)) |
1167 12 mohor 
                    ((DEBUGSelected & RiscDebugScanChain) & (BitCounter<65)) |
1168 
                    ((DEBUGSelected & WishboneScanChain)  & (BitCounter<65))
1169 9 mohor 
                  );
1170 2 mohor 
 
1171 
wire EnableCrcOut= ShiftDR &
1172 9 mohor 
                   (
1173 2 mohor 
                    ((DEBUGSelected & RegisterScanChain)  & (BitCounter<38)) |
1174 12 mohor 
                    ((DEBUGSelected & RiscDebugScanChain) & (BitCounter<65)) |
1175 
                    ((DEBUGSelected & WishboneScanChain)  & (BitCounter<65))
1176 2 mohor 
                    `ifdef TRACE_ENABLED
1177 
                                                                             |
1178 
                    ((DEBUGSelected & TraceTestScanChain) & (BitCounter<40))
1179 
                    `endif
1180 9 mohor 
                   );
1181 2 mohor 
 
1182 
// Calculating crc for input data
1183 9 mohor 
dbg_crc8_d1 crc1 (.Data(TDI), .EnableCrc(EnableCrcIn), .Reset(AsyncResetCrc), .SyncResetCrc(SyncResetCrc),
1184 2 mohor 
                  .CrcOut(CalculatedCrcIn), .Clk(TCK));
1185 
 
1186 
// Calculating crc for output data
1187 9 mohor 
dbg_crc8_d1 crc2 (.Data(TDOData), .EnableCrc(EnableCrcOut), .Reset(AsyncResetCrc), .SyncResetCrc(SyncResetCrc),
1188 2 mohor 
                  .CrcOut(CalculatedCrcOut), .Clk(TCK));
1189 
 
1190 
 
1191 
// Generating CrcMatch signal
1192 
always @ (posedge TCK or posedge RESET)
1193 
begin
1194 
  if(RESET)
1195 
    CrcMatch <=#Tp 1'b0;
1196 
  else
1197 
  if(Exit1DR)
1198 
    begin
1199 
      if(CHAIN_SELECTSelected)
1200 
        CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[11:4];
1201 
      else
1202 
      if(RegisterScanChain & ~CHAIN_SELECTSelected)
1203 
        CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[45:38];
1204 
      else
1205 
      if(RiscDebugScanChain & ~CHAIN_SELECTSelected)
1206 
        CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[72:65];
1207 12 mohor 
      else
1208 
      if(WishboneScanChain & ~CHAIN_SELECTSelected)
1209 
        CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[72:65];
1210 2 mohor 
    end
1211 
end
1212 
 
1213 
 
1214 
// Active chain
1215 
assign RegisterScanChain   = Chain == `REGISTER_SCAN_CHAIN;
1216 
assign RiscDebugScanChain  = Chain == `RISC_DEBUG_CHAIN;
1217 12 mohor 
assign WishboneScanChain   = Chain == `WISHBONE_SCAN_CHAIN;
1218 2 mohor 
 
1219 
`ifdef TRACE_ENABLED
1220 
  assign TraceTestScanChain  = Chain == `TRACE_TEST_CHAIN;
1221 
`endif
1222 
 
1223 
/**********************************************************************************
1224 
*                                                                                 *
1225 
*   End: Connecting CRC module                                                    *
1226 
*                                                                                 *
1227 
**********************************************************************************/
1228 
 
1229 
/**********************************************************************************
1230 
*                                                                                 *
1231 
*   Connecting trace module                                                       *
1232 
*                                                                                 *
1233 
**********************************************************************************/
1234 
`ifdef TRACE_ENABLED
1235 11 mohor 
  dbg_trace dbgTrace1(.Wp(wp_i), .Bp(bp_i), .DataIn(risc_data_i), .OpSelect(opselect_trace),
1236 9 mohor 
                      .LsStatus(lsstatus_i), .IStatus(istatus_i), .RiscStall_O(RiscStall_trace),
1237 11 mohor 
                      .Mclk(risc_clk_i), .Reset(RESET), .TraceChain(TraceChain),
1238 8 mohor 
                      .ContinMode(ContinMode), .TraceEnable_reg(TraceEnable),
1239 5 mohor 
                      .WpTrigger(WpTrigger),
1240 2 mohor 
                      .BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger), .ITrigger(ITrigger),
1241 
                      .TriggerOper(TriggerOper), .WpQualif(WpQualif), .BpQualif(BpQualif),
1242 
                      .LSSQualif(LSSQualif), .IQualif(IQualif), .QualifOper(QualifOper),
1243 5 mohor 
                      .RecordPC(RecordPC), .RecordLSEA(RecordLSEA),
1244 
                      .RecordLDATA(RecordLDATA), .RecordSDATA(RecordSDATA),
1245 
                      .RecordReadSPR(RecordReadSPR), .RecordWriteSPR(RecordWriteSPR),
1246 
                      .RecordINSTR(RecordINSTR),
1247 2 mohor 
                      .WpTriggerValid(WpTriggerValid), .BpTriggerValid(BpTriggerValid),
1248 
                      .LSSTriggerValid(LSSTriggerValid), .ITriggerValid(ITriggerValid),
1249 
                      .WpQualifValid(WpQualifValid), .BpQualifValid(BpQualifValid),
1250 
                      .LSSQualifValid(LSSQualifValid), .IQualifValid(IQualifValid),
1251 9 mohor 
                      .ReadBuffer(ReadTraceBufferPulse),
1252 2 mohor 
                      .WpStop(WpStop), .BpStop(BpStop), .LSSStop(LSSStop), .IStop(IStop),
1253 
                      .StopOper(StopOper), .WpStopValid(WpStopValid), .BpStopValid(BpStopValid),
1254 
                      .LSSStopValid(LSSStopValid), .IStopValid(IStopValid)
1255 
                     );
1256 
`endif
1257 
/**********************************************************************************
1258 
*                                                                                 *
1259 
*   End: Connecting trace module                                                  *
1260 
*                                                                                 *
1261 
**********************************************************************************/
1262 
 
1263 
 
1264 
 
1265 9 mohor 
endmodule

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