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[/] [dbg_interface/] [tags/] [rel_1/] [rtl/] [verilog/] [tap_top.v] - Blame information for rev 40

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  tap_top.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor                                             ////
////       igorm@opencores.org                                    ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000, 2001, 2002 Authors                       ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4  2002/03/25 13:16:15  mohor
// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
// not named correctly.
//
// Revision 1.3  2002/03/12 14:30:05  mohor
// Few outputs for boundary scan chain added.
//
// Revision 1.2  2002/03/12 10:31:53  mohor
// tap_top and dbg_top modules are put into two separate modules. tap_top
// contains only tap state machine and related logic. dbg_top contains all
// logic necessery for debugging.
//
// Revision 1.1  2002/03/08 15:28:16  mohor
// Structure changed. Hooks for jtag chain added.
//
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "dbg_defines.v"
 
// Top module
module tap_top(
                // JTAG pins
                tms_pad_i, tck_pad_i, trst_pad_i, tdi_pad_i, tdo_pad_o, tdo_padoen_o,
 
                // TAP states
                ShiftDR, Exit1DR, UpdateDR, UpdateDR_q, CaptureDR,
 
                // Instructions
                IDCODESelected, CHAIN_SELECTSelected, DEBUGSelected, EXTESTSelected,
 
                // TDO from dbg module
                TDOData_dbg, BypassRegister,
 
                // From Boundary Scan Chain
                bs_chain_i
 
              );
 
parameter Tp = 1;
 
// JTAG pins
input   tms_pad_i;                  // JTAG test mode select pad
input   tck_pad_i;                  // JTAG test clock pad
input   trst_pad_i;                 // JTAG test reset pad
input   tdi_pad_i;                  // JTAG test data input pad
output  tdo_pad_o;                  // JTAG test data output pad
output  tdo_padoen_o;               // Output enable for JTAG test data output pad 
 
// TAP states
output  ShiftDR;
output  Exit1DR;
output  UpdateDR;
output  UpdateDR_q;
output  CaptureDR;
 
// Instructions
output  IDCODESelected;
output  CHAIN_SELECTSelected;
output  DEBUGSelected;
output  EXTESTSelected;
 
input   TDOData_dbg;
output  BypassRegister;
 
// From Boundary Scan Chain
input   bs_chain_i;
 
 
reg     tdo_pad_o;
 
// TAP states
reg     TestLogicReset;
reg     RunTestIdle;
reg     SelectDRScan;
reg     CaptureDR;
reg     ShiftDR;
reg     Exit1DR;
reg     PauseDR;
reg     Exit2DR;
reg     UpdateDR;
 
reg     SelectIRScan;
reg     CaptureIR;
reg     ShiftIR;
reg     Exit1IR;
reg     PauseIR;
reg     Exit2IR;
reg     UpdateIR;
 
 
// Defining which instruction is selected
reg     EXTESTSelected;
reg     SAMPLE_PRELOADSelected;
reg     IDCODESelected;
reg     CHAIN_SELECTSelected;
reg     INTESTSelected;
reg     CLAMPSelected;
reg     CLAMPZSelected;
reg     HIGHZSelected;
reg     DEBUGSelected;
reg     BYPASSSelected;
 
reg     BypassRegister;               // Bypass register
 
wire    trst;                         // trst is active high while trst_pad_i is active low
wire    tck;
wire    TMS;
wire    tdi;
 
wire    RiscDebugScanChain;
wire    WishboneScanChain;
wire    RegisterScanChain;
 
 
assign trst = ~trst_pad_i;                // trst_pad_i is active low
assign tck  = tck_pad_i;
assign TMS  = tms_pad_i;
assign tdi  = tdi_pad_i;
 
 
/**********************************************************************************
*                                                                                 *
*   TAP State Machine: Fully JTAG compliant                                       *
*                                                                                 *
**********************************************************************************/
 
// TestLogicReset state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    TestLogicReset<=#Tp 1;
  else
    begin
      if(TMS & (TestLogicReset | SelectIRScan))
        TestLogicReset<=#Tp 1;
      else
        TestLogicReset<=#Tp 0;
    end
end
 
// RunTestIdle state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    RunTestIdle<=#Tp 0;
  else
  if(~TMS & (TestLogicReset | RunTestIdle | UpdateDR | UpdateIR))
    RunTestIdle<=#Tp 1;
  else
    RunTestIdle<=#Tp 0;
end
 
// SelectDRScan state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    SelectDRScan<=#Tp 0;
  else
  if(TMS & (RunTestIdle | UpdateDR | UpdateIR))
    SelectDRScan<=#Tp 1;
  else
    SelectDRScan<=#Tp 0;
end
 
// CaptureDR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    CaptureDR<=#Tp 0;
  else
  if(~TMS & SelectDRScan)
    CaptureDR<=#Tp 1;
  else
    CaptureDR<=#Tp 0;
end
 
// ShiftDR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    ShiftDR<=#Tp 0;
  else
  if(~TMS & (CaptureDR | ShiftDR | Exit2DR))
    ShiftDR<=#Tp 1;
  else
    ShiftDR<=#Tp 0;
end
 
// Exit1DR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    Exit1DR<=#Tp 0;
  else
  if(TMS & (CaptureDR | ShiftDR))
    Exit1DR<=#Tp 1;
  else
    Exit1DR<=#Tp 0;
end
 
// PauseDR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    PauseDR<=#Tp 0;
  else
  if(~TMS & (Exit1DR | PauseDR))
    PauseDR<=#Tp 1;
  else
    PauseDR<=#Tp 0;
end
 
// Exit2DR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    Exit2DR<=#Tp 0;
  else
  if(TMS & PauseDR)
    Exit2DR<=#Tp 1;
  else
    Exit2DR<=#Tp 0;
end
 
// UpdateDR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    UpdateDR<=#Tp 0;
  else
  if(TMS & (Exit1DR | Exit2DR))
    UpdateDR<=#Tp 1;
  else
    UpdateDR<=#Tp 0;
end
 
// Delayed UpdateDR state
reg UpdateDR_q;
always @ (posedge tck)
begin
  UpdateDR_q<=#Tp UpdateDR;
end
 
// SelectIRScan state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    SelectIRScan<=#Tp 0;
  else
  if(TMS & SelectDRScan)
    SelectIRScan<=#Tp 1;
  else
    SelectIRScan<=#Tp 0;
end
 
// CaptureIR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    CaptureIR<=#Tp 0;
  else
  if(~TMS & SelectIRScan)
    CaptureIR<=#Tp 1;
  else
    CaptureIR<=#Tp 0;
end
 
// ShiftIR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    ShiftIR<=#Tp 0;
  else
  if(~TMS & (CaptureIR | ShiftIR | Exit2IR))
    ShiftIR<=#Tp 1;
  else
    ShiftIR<=#Tp 0;
end
 
// Exit1IR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    Exit1IR<=#Tp 0;
  else
  if(TMS & (CaptureIR | ShiftIR))
    Exit1IR<=#Tp 1;
  else
    Exit1IR<=#Tp 0;
end
 
// PauseIR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    PauseIR<=#Tp 0;
  else
  if(~TMS & (Exit1IR | PauseIR))
    PauseIR<=#Tp 1;
  else
    PauseIR<=#Tp 0;
end
 
// Exit2IR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    Exit2IR<=#Tp 0;
  else
  if(TMS & PauseIR)
    Exit2IR<=#Tp 1;
  else
    Exit2IR<=#Tp 0;
end
 
// UpdateIR state
always @ (posedge tck or posedge trst)
begin
  if(trst)
    UpdateIR<=#Tp 0;
  else
  if(TMS & (Exit1IR | Exit2IR))
    UpdateIR<=#Tp 1;
  else
    UpdateIR<=#Tp 0;
end
 
/**********************************************************************************
*                                                                                 *
*   End: TAP State Machine                                                        *
*                                                                                 *
**********************************************************************************/
 
 
 
/**********************************************************************************
*                                                                                 *
*   JTAG_IR:  JTAG Instruction Register                                           *
*                                                                                 *
**********************************************************************************/
wire [1:0]Status = 2'b10;     // Holds current chip status. Core should return this status. For now a constant is used.
 
reg [`IR_LENGTH-1:0]JTAG_IR;  // Instruction register
reg [`IR_LENGTH-1:0]LatchedJTAG_IR;
 
reg TDOInstruction;
 
always @ (posedge tck or posedge trst)
begin
  if(trst)
    JTAG_IR[`IR_LENGTH-1:0] <= #Tp 0;
  else
  if(CaptureIR)
    begin
      JTAG_IR[1:0] <= #Tp 2'b01;       // This value is fixed for easier fault detection
      JTAG_IR[3:2] <= #Tp Status[1:0]; // Current status of chip
    end
  else
  if(ShiftIR)
    JTAG_IR[`IR_LENGTH-1:0] <= #Tp {tdi, JTAG_IR[`IR_LENGTH-1:1]};
end
 
 
//TDO is changing on the falling edge of tck
always @ (negedge tck)
begin
  if(ShiftIR)
    TDOInstruction <= #Tp JTAG_IR[0];
end
 
/**********************************************************************************
*                                                                                 *
*   End: JTAG_IR                                                                  *
*                                                                                 *
**********************************************************************************/
 
 
/**********************************************************************************
*                                                                                 *
*   JTAG_DR:  JTAG Data Register                                                  *
*                                                                                 *
**********************************************************************************/
reg [`DR_LENGTH-1:0]JTAG_DR_IN;    // Data register
 
 
always @ (posedge tck or posedge trst)
begin
  if(trst)
    JTAG_DR_IN[`DR_LENGTH-1:0]<=#Tp 0;
  else
  if(IDCODESelected)                          // To save space JTAG_DR_IN is also used for shifting out IDCODE
    begin
      if(ShiftDR)
        JTAG_DR_IN[31:0] <= #Tp {tdi, JTAG_DR_IN[31:1]};
      else
        JTAG_DR_IN[31:0] <= #Tp `IDCODE_VALUE;
    end
  else
  if(CHAIN_SELECTSelected & ShiftDR)
    JTAG_DR_IN[12:0] <= #Tp {tdi, JTAG_DR_IN[12:1]};
  else
  if(DEBUGSelected & ShiftDR)
    begin
      if(RiscDebugScanChain | WishboneScanChain)
        JTAG_DR_IN[73:0] <= #Tp {tdi, JTAG_DR_IN[73:1]};
      else
      if(RegisterScanChain)
        JTAG_DR_IN[46:0] <= #Tp {tdi, JTAG_DR_IN[46:1]};
    end
end
 
 
 
/**********************************************************************************
*                                                                                 *
*   End: JTAG_DR                                                                  *
*                                                                                 *
**********************************************************************************/
 
 
 
 
 
/**********************************************************************************
*                                                                                 *
*   Bypass logic                                                                  *
*                                                                                 *
**********************************************************************************/
reg TDOBypassed;
 
always @ (posedge tck)
begin
  if(ShiftDR)
    BypassRegister<=#Tp tdi;
end
 
always @ (negedge tck)
begin
  TDOBypassed<=#Tp BypassRegister;
end
/**********************************************************************************
*                                                                                 *
*   End: Bypass logic                                                             *
*                                                                                 *
**********************************************************************************/
 
 
 
 
 
/**********************************************************************************
*                                                                                 *
*   Activating Instructions                                                       *
*                                                                                 *
**********************************************************************************/
 
// Updating JTAG_IR (Instruction Register)
always @ (posedge tck or posedge trst)
begin
  if(trst)
    LatchedJTAG_IR <=#Tp `IDCODE;   // IDCODE selected after reset
  else
  if(UpdateIR)
    LatchedJTAG_IR <=#Tp JTAG_IR;
end
 
/**********************************************************************************
*                                                                                 *
*   End: Activating Instructions                                                  *
*                                                                                 *
**********************************************************************************/
 
 
// Updating JTAG_IR (Instruction Register)
always @ (LatchedJTAG_IR)
begin
  EXTESTSelected          = 0;
  SAMPLE_PRELOADSelected  = 0;
  IDCODESelected          = 0;
  CHAIN_SELECTSelected    = 0;
  INTESTSelected          = 0;
  CLAMPSelected           = 0;
  CLAMPZSelected          = 0;
  HIGHZSelected           = 0;
  DEBUGSelected           = 0;
  BYPASSSelected          = 0;
 
  case(LatchedJTAG_IR)
    `EXTEST:            EXTESTSelected          = 1;    // External test
    `SAMPLE_PRELOAD:    SAMPLE_PRELOADSelected  = 1;    // Sample preload
    `IDCODE:            IDCODESelected          = 1;    // ID Code
    `CHAIN_SELECT:      CHAIN_SELECTSelected    = 1;    // Chain select
    `INTEST:            INTESTSelected          = 1;    // Internal test
    `CLAMP:             CLAMPSelected           = 1;    // Clamp
    `CLAMPZ:            CLAMPZSelected          = 1;    // ClampZ
    `HIGHZ:             HIGHZSelected           = 1;    // High Z
    `DEBUG:             DEBUGSelected           = 1;    // Debug
    `BYPASS:            BYPASSSelected          = 1;    // BYPASS
    default:            BYPASSSelected          = 1;    // BYPASS
  endcase
end
 
 
 
/**********************************************************************************
*                                                                                 *
*   Multiplexing TDO data                                                         *
*                                                                                 *
**********************************************************************************/
 
// This multiplexer can be expanded with number of user registers
always @ (LatchedJTAG_IR or TDOInstruction or TDOData_dbg or TDOBypassed or bs_chain_i or ShiftIR or Exit1IR)
begin
  if(ShiftIR | Exit1IR)
    tdo_pad_o <=#Tp TDOInstruction;
  else
    begin
      case(LatchedJTAG_IR)
        `IDCODE:            tdo_pad_o <=#Tp TDOData_dbg;      // Reading ID code
        `CHAIN_SELECT:      tdo_pad_o <=#Tp TDOData_dbg;      // Selecting the chain
        `DEBUG:             tdo_pad_o <=#Tp TDOData_dbg;      // Debug
        `SAMPLE_PRELOAD:    tdo_pad_o <=#Tp bs_chain_i;   // Sampling/Preloading
        `EXTEST:            tdo_pad_o <=#Tp bs_chain_i;   // External test
        default:            tdo_pad_o <=#Tp TDOBypassed;  // BYPASS instruction
      endcase
    end
end
 
// Tristate control for tdo_pad_o pin
assign tdo_padoen_o = ShiftIR | ShiftDR | Exit1IR | Exit1DR | UpdateDR;
 
/**********************************************************************************
*                                                                                 *
*   End: Multiplexing TDO data                                                    *
*                                                                                 *
**********************************************************************************/
 
endmodule

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Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_1/] [rtl/] [verilog/] [tap_top.v] - Blame information for rev 40

Line No.	Rev	Author	Line
1	36	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// tap_top.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7			`//// http://www.opencores.org/projects/DebugInterface/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Igor Mohor ////`
12			`//// igorm@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is avaliable in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000, 2001, 2002 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	40	mohor	`// Revision 1.4 2002/03/25 13:16:15 mohor`
49			`// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just`
50			`// not named correctly.`
51			`//`
52	39	mohor	`// Revision 1.3 2002/03/12 14:30:05 mohor`
53			`// Few outputs for boundary scan chain added.`
54			`//`
55	38	mohor	`// Revision 1.2 2002/03/12 10:31:53 mohor`
56			`// tap_top and dbg_top modules are put into two separate modules. tap_top`
57			`// contains only tap state machine and related logic. dbg_top contains all`
58			`// logic necessery for debugging.`
59			`//`
60	37	mohor	`// Revision 1.1 2002/03/08 15:28:16 mohor`
61			`// Structure changed. Hooks for jtag chain added.`
62	36	mohor	`//`
63			`//`
64			`//`
65	37	mohor	`//`
66	36	mohor
67			`// synopsys translate_off`
68			`include "timescale.v"
69			`// synopsys translate_on`
70			`include "dbg_defines.v"
71
72			`// Top module`
73			`module tap_top(`
74			`// JTAG pins`
75	40	mohor	`tms_pad_i, tck_pad_i, trst_pad_i, tdi_pad_i, tdo_pad_o, tdo_padoen_o,`
76	36	mohor
77	37	mohor	`// TAP states`
78	38	mohor	`ShiftDR, Exit1DR, UpdateDR, UpdateDR_q, CaptureDR,`
79	36	mohor
80	37	mohor	`// Instructions`
81	38	mohor	`IDCODESelected, CHAIN_SELECTSelected, DEBUGSelected, EXTESTSelected,`
82	37	mohor
83			`// TDO from dbg module`
84	38	mohor	`TDOData_dbg, BypassRegister,`
85
86			`// From Boundary Scan Chain`
87			`bs_chain_i`
88
89	36	mohor	`);`
90
91			`parameter Tp = 1;`
92
93			`// JTAG pins`
94			`input tms_pad_i; // JTAG test mode select pad`
95			`input tck_pad_i; // JTAG test clock pad`
96			`input trst_pad_i; // JTAG test reset pad`
97			`input tdi_pad_i; // JTAG test data input pad`
98			`output tdo_pad_o; // JTAG test data output pad`
99	40	mohor	`output tdo_padoen_o; // Output enable for JTAG test data output pad`
100	36	mohor
101	37	mohor	`// TAP states`
102			`output ShiftDR;`
103			`output Exit1DR;`
104			`output UpdateDR;`
105			`output UpdateDR_q;`
106	38	mohor	`output CaptureDR;`
107	36	mohor
108	37	mohor	`// Instructions`
109			`output IDCODESelected;`
110			`output CHAIN_SELECTSelected;`
111			`output DEBUGSelected;`
112	38	mohor	`output EXTESTSelected;`
113	36	mohor
114	37	mohor	`input TDOData_dbg;`
115			`output BypassRegister;`
116	36	mohor
117	38	mohor	`// From Boundary Scan Chain`
118			`input bs_chain_i;`
119
120
121	36	mohor	`reg tdo_pad_o;`
122
123			`// TAP states`
124			`reg TestLogicReset;`
125			`reg RunTestIdle;`
126			`reg SelectDRScan;`
127			`reg CaptureDR;`
128			`reg ShiftDR;`
129			`reg Exit1DR;`
130			`reg PauseDR;`
131			`reg Exit2DR;`
132			`reg UpdateDR;`
133
134			`reg SelectIRScan;`
135			`reg CaptureIR;`
136			`reg ShiftIR;`
137			`reg Exit1IR;`
138			`reg PauseIR;`
139			`reg Exit2IR;`
140			`reg UpdateIR;`
141
142
143			`// Defining which instruction is selected`
144			`reg EXTESTSelected;`
145			`reg SAMPLE_PRELOADSelected;`
146			`reg IDCODESelected;`
147			`reg CHAIN_SELECTSelected;`
148			`reg INTESTSelected;`
149			`reg CLAMPSelected;`
150			`reg CLAMPZSelected;`
151			`reg HIGHZSelected;`
152			`reg DEBUGSelected;`
153			`reg BYPASSSelected;`
154
155			`reg BypassRegister; // Bypass register`
156
157			`wire trst; // trst is active high while trst_pad_i is active low`
158			`wire tck;`
159			`wire TMS;`
160			`wire tdi;`
161
162			`wire RiscDebugScanChain;`
163			`wire WishboneScanChain;`
164			`wire RegisterScanChain;`
165
166
167			`assign trst = ~trst_pad_i; // trst_pad_i is active low`
168			`assign tck = tck_pad_i;`
169			`assign TMS = tms_pad_i;`
170			`assign tdi = tdi_pad_i;`
171
172
173			`/**********************************************************************************`
174			`* *`
175			`* TAP State Machine: Fully JTAG compliant *`
176			`* *`
177			`**********************************************************************************/`
178
179			`// TestLogicReset state`
180			`always @ (posedge tck or posedge trst)`
181			`begin`
182			`if(trst)`
183			`TestLogicReset<=#Tp 1;`
184			`else`
185			`begin`
186			`if(TMS & (TestLogicReset \| SelectIRScan))`
187			`TestLogicReset<=#Tp 1;`
188			`else`
189			`TestLogicReset<=#Tp 0;`
190			`end`
191			`end`
192
193			`// RunTestIdle state`
194			`always @ (posedge tck or posedge trst)`
195			`begin`
196			`if(trst)`
197			`RunTestIdle<=#Tp 0;`
198			`else`
199			`if(~TMS & (TestLogicReset \| RunTestIdle \| UpdateDR \| UpdateIR))`
200			`RunTestIdle<=#Tp 1;`
201			`else`
202			`RunTestIdle<=#Tp 0;`
203			`end`
204
205			`// SelectDRScan state`
206			`always @ (posedge tck or posedge trst)`
207			`begin`
208			`if(trst)`
209			`SelectDRScan<=#Tp 0;`
210			`else`
211			`if(TMS & (RunTestIdle \| UpdateDR \| UpdateIR))`
212			`SelectDRScan<=#Tp 1;`
213			`else`
214			`SelectDRScan<=#Tp 0;`
215			`end`
216
217			`// CaptureDR state`
218			`always @ (posedge tck or posedge trst)`
219			`begin`
220			`if(trst)`
221			`CaptureDR<=#Tp 0;`
222			`else`
223			`if(~TMS & SelectDRScan)`
224			`CaptureDR<=#Tp 1;`
225			`else`
226			`CaptureDR<=#Tp 0;`
227			`end`
228
229			`// ShiftDR state`
230			`always @ (posedge tck or posedge trst)`
231			`begin`
232			`if(trst)`
233			`ShiftDR<=#Tp 0;`
234			`else`
235			`if(~TMS & (CaptureDR \| ShiftDR \| Exit2DR))`
236			`ShiftDR<=#Tp 1;`
237			`else`
238			`ShiftDR<=#Tp 0;`
239			`end`
240
241			`// Exit1DR state`
242			`always @ (posedge tck or posedge trst)`
243			`begin`
244			`if(trst)`
245			`Exit1DR<=#Tp 0;`
246			`else`
247			`if(TMS & (CaptureDR \| ShiftDR))`
248			`Exit1DR<=#Tp 1;`
249			`else`
250			`Exit1DR<=#Tp 0;`
251			`end`
252
253			`// PauseDR state`
254			`always @ (posedge tck or posedge trst)`
255			`begin`
256			`if(trst)`
257			`PauseDR<=#Tp 0;`
258			`else`
259			`if(~TMS & (Exit1DR \| PauseDR))`
260			`PauseDR<=#Tp 1;`
261			`else`
262			`PauseDR<=#Tp 0;`
263			`end`
264
265			`// Exit2DR state`
266			`always @ (posedge tck or posedge trst)`
267			`begin`
268			`if(trst)`
269			`Exit2DR<=#Tp 0;`
270			`else`
271			`if(TMS & PauseDR)`
272			`Exit2DR<=#Tp 1;`
273			`else`
274			`Exit2DR<=#Tp 0;`
275			`end`
276
277			`// UpdateDR state`
278			`always @ (posedge tck or posedge trst)`
279			`begin`
280			`if(trst)`
281			`UpdateDR<=#Tp 0;`
282			`else`
283			`if(TMS & (Exit1DR \| Exit2DR))`
284			`UpdateDR<=#Tp 1;`
285			`else`
286			`UpdateDR<=#Tp 0;`
287			`end`
288
289			`// Delayed UpdateDR state`
290			`reg UpdateDR_q;`
291			`always @ (posedge tck)`
292			`begin`
293			`UpdateDR_q<=#Tp UpdateDR;`
294			`end`
295
296			`// SelectIRScan state`
297			`always @ (posedge tck or posedge trst)`
298			`begin`
299			`if(trst)`
300			`SelectIRScan<=#Tp 0;`
301			`else`
302			`if(TMS & SelectDRScan)`
303			`SelectIRScan<=#Tp 1;`
304			`else`
305			`SelectIRScan<=#Tp 0;`
306			`end`
307
308			`// CaptureIR state`
309			`always @ (posedge tck or posedge trst)`
310			`begin`
311			`if(trst)`
312			`CaptureIR<=#Tp 0;`
313			`else`
314			`if(~TMS & SelectIRScan)`
315			`CaptureIR<=#Tp 1;`
316			`else`
317			`CaptureIR<=#Tp 0;`
318			`end`
319
320			`// ShiftIR state`
321			`always @ (posedge tck or posedge trst)`
322			`begin`
323			`if(trst)`
324			`ShiftIR<=#Tp 0;`
325			`else`
326			`if(~TMS & (CaptureIR \| ShiftIR \| Exit2IR))`
327			`ShiftIR<=#Tp 1;`
328			`else`
329			`ShiftIR<=#Tp 0;`
330			`end`
331
332			`// Exit1IR state`
333			`always @ (posedge tck or posedge trst)`
334			`begin`
335			`if(trst)`
336			`Exit1IR<=#Tp 0;`
337			`else`
338			`if(TMS & (CaptureIR \| ShiftIR))`
339			`Exit1IR<=#Tp 1;`
340			`else`
341			`Exit1IR<=#Tp 0;`
342			`end`
343
344			`// PauseIR state`
345			`always @ (posedge tck or posedge trst)`
346			`begin`
347			`if(trst)`
348			`PauseIR<=#Tp 0;`
349			`else`
350			`if(~TMS & (Exit1IR \| PauseIR))`
351			`PauseIR<=#Tp 1;`
352			`else`
353			`PauseIR<=#Tp 0;`
354			`end`
355
356			`// Exit2IR state`
357			`always @ (posedge tck or posedge trst)`
358			`begin`
359			`if(trst)`
360			`Exit2IR<=#Tp 0;`
361			`else`
362			`if(TMS & PauseIR)`
363			`Exit2IR<=#Tp 1;`
364			`else`
365			`Exit2IR<=#Tp 0;`
366			`end`
367
368			`// UpdateIR state`
369			`always @ (posedge tck or posedge trst)`
370			`begin`
371			`if(trst)`
372			`UpdateIR<=#Tp 0;`
373			`else`
374			`if(TMS & (Exit1IR \| Exit2IR))`
375			`UpdateIR<=#Tp 1;`
376			`else`
377			`UpdateIR<=#Tp 0;`
378			`end`
379
380			`/**********************************************************************************`
381			`* *`
382			`* End: TAP State Machine *`
383			`* *`
384			`**********************************************************************************/`
385
386
387
388			`/**********************************************************************************`
389			`* *`
390			`* JTAG_IR: JTAG Instruction Register *`
391			`* *`
392			`**********************************************************************************/`
393			`wire [1:0]Status = 2'b10; // Holds current chip status. Core should return this status. For now a constant is used.`
394
395			reg [`IR_LENGTH-1:0]JTAG_IR; // Instruction register
396			reg [`IR_LENGTH-1:0]LatchedJTAG_IR;
397
398			`reg TDOInstruction;`
399
400			`always @ (posedge tck or posedge trst)`
401			`begin`
402			`if(trst)`
403			JTAG_IR[`IR_LENGTH-1:0] <= #Tp 0;
404			`else`
405			`if(CaptureIR)`
406			`begin`
407			`JTAG_IR[1:0] <= #Tp 2'b01; // This value is fixed for easier fault detection`
408			`JTAG_IR[3:2] <= #Tp Status[1:0]; // Current status of chip`
409			`end`
410			`else`
411			`if(ShiftIR)`
412			JTAG_IR[`IR_LENGTH-1:0] <= #Tp {tdi, JTAG_IR[`IR_LENGTH-1:1]};
413			`end`
414
415
416			`//TDO is changing on the falling edge of tck`
417			`always @ (negedge tck)`
418			`begin`
419			`if(ShiftIR)`
420			`TDOInstruction <= #Tp JTAG_IR[0];`
421			`end`
422
423			`/**********************************************************************************`
424			`* *`
425			`* End: JTAG_IR *`
426			`* *`
427			`**********************************************************************************/`
428
429
430			`/**********************************************************************************`
431			`* *`
432			`* JTAG_DR: JTAG Data Register *`
433			`* *`
434			`**********************************************************************************/`
435			reg [`DR_LENGTH-1:0]JTAG_DR_IN; // Data register
436
437
438			`always @ (posedge tck or posedge trst)`
439			`begin`
440			`if(trst)`
441			JTAG_DR_IN[`DR_LENGTH-1:0]<=#Tp 0;
442			`else`
443			`if(IDCODESelected) // To save space JTAG_DR_IN is also used for shifting out IDCODE`
444			`begin`
445			`if(ShiftDR)`
446			`JTAG_DR_IN[31:0] <= #Tp {tdi, JTAG_DR_IN[31:1]};`
447			`else`
448			JTAG_DR_IN[31:0] <= #Tp `IDCODE_VALUE;
449			`end`
450			`else`
451			`if(CHAIN_SELECTSelected & ShiftDR)`
452			`JTAG_DR_IN[12:0] <= #Tp {tdi, JTAG_DR_IN[12:1]};`
453			`else`
454			`if(DEBUGSelected & ShiftDR)`
455			`begin`
456			`if(RiscDebugScanChain \| WishboneScanChain)`
457			`JTAG_DR_IN[73:0] <= #Tp {tdi, JTAG_DR_IN[73:1]};`
458			`else`
459			`if(RegisterScanChain)`
460			`JTAG_DR_IN[46:0] <= #Tp {tdi, JTAG_DR_IN[46:1]};`
461			`end`
462			`end`
463
464
465
466			`/**********************************************************************************`
467			`* *`
468			`* End: JTAG_DR *`
469			`* *`
470			`**********************************************************************************/`
471
472
473
474
475
476			`/**********************************************************************************`
477			`* *`
478			`* Bypass logic *`
479			`* *`
480			`**********************************************************************************/`
481			`reg TDOBypassed;`
482
483			`always @ (posedge tck)`
484			`begin`
485			`if(ShiftDR)`
486			`BypassRegister<=#Tp tdi;`
487			`end`
488
489			`always @ (negedge tck)`
490			`begin`
491			`TDOBypassed<=#Tp BypassRegister;`
492			`end`
493			`/**********************************************************************************`
494			`* *`
495			`* End: Bypass logic *`
496			`* *`
497			`**********************************************************************************/`
498
499
500
501
502
503			`/**********************************************************************************`
504			`* *`
505			`* Activating Instructions *`
506			`* *`
507			`**********************************************************************************/`
508
509			`// Updating JTAG_IR (Instruction Register)`
510			`always @ (posedge tck or posedge trst)`
511			`begin`
512			`if(trst)`
513			LatchedJTAG_IR <=#Tp `IDCODE; // IDCODE selected after reset
514			`else`
515			`if(UpdateIR)`
516			`LatchedJTAG_IR <=#Tp JTAG_IR;`
517			`end`
518
519			`/**********************************************************************************`
520			`* *`
521			`* End: Activating Instructions *`
522			`* *`
523			`**********************************************************************************/`
524
525
526			`// Updating JTAG_IR (Instruction Register)`
527			`always @ (LatchedJTAG_IR)`
528			`begin`
529			`EXTESTSelected = 0;`
530			`SAMPLE_PRELOADSelected = 0;`
531			`IDCODESelected = 0;`
532			`CHAIN_SELECTSelected = 0;`
533			`INTESTSelected = 0;`
534			`CLAMPSelected = 0;`
535			`CLAMPZSelected = 0;`
536			`HIGHZSelected = 0;`
537			`DEBUGSelected = 0;`
538			`BYPASSSelected = 0;`
539
540			`case(LatchedJTAG_IR)`
541			`EXTEST: EXTESTSelected = 1; // External test
542			`SAMPLE_PRELOAD: SAMPLE_PRELOADSelected = 1; // Sample preload
543			`IDCODE: IDCODESelected = 1; // ID Code
544			`CHAIN_SELECT: CHAIN_SELECTSelected = 1; // Chain select
545			`INTEST: INTESTSelected = 1; // Internal test
546			`CLAMP: CLAMPSelected = 1; // Clamp
547			`CLAMPZ: CLAMPZSelected = 1; // ClampZ
548			`HIGHZ: HIGHZSelected = 1; // High Z
549			`DEBUG: DEBUGSelected = 1; // Debug
550			`BYPASS: BYPASSSelected = 1; // BYPASS
551			`default: BYPASSSelected = 1; // BYPASS`
552			`endcase`
553			`end`
554
555
556
557			`/**********************************************************************************`
558			`* *`
559			`* Multiplexing TDO data *`
560			`* *`
561			`**********************************************************************************/`
562
563			`// This multiplexer can be expanded with number of user registers`
564	38	mohor	`always @ (LatchedJTAG_IR or TDOInstruction or TDOData_dbg or TDOBypassed or bs_chain_i or ShiftIR or Exit1IR)`
565	36	mohor	`begin`
566			`if(ShiftIR \| Exit1IR)`
567			`tdo_pad_o <=#Tp TDOInstruction;`
568			`else`
569			`begin`
570			`case(LatchedJTAG_IR)`
571	37	mohor	`IDCODE: tdo_pad_o <=#Tp TDOData_dbg; // Reading ID code
572			`CHAIN_SELECT: tdo_pad_o <=#Tp TDOData_dbg; // Selecting the chain
573			`DEBUG: tdo_pad_o <=#Tp TDOData_dbg; // Debug
574	38	mohor	`SAMPLE_PRELOAD: tdo_pad_o <=#Tp bs_chain_i; // Sampling/Preloading
575			`EXTEST: tdo_pad_o <=#Tp bs_chain_i; // External test
576	36	mohor	`default: tdo_pad_o <=#Tp TDOBypassed; // BYPASS instruction`
577			`endcase`
578			`end`
579			`end`
580
581			`// Tristate control for tdo_pad_o pin`
582	40	mohor	`assign tdo_padoen_o = ShiftIR \| ShiftDR \| Exit1IR \| Exit1DR \| UpdateDR;`
583	36	mohor
584			`/**********************************************************************************`
585			`* *`
586			`* End: Multiplexing TDO data *`
587			`* *`
588			`**********************************************************************************/`
589
590			`endmodule`