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[/] [dbg_interface/] [tags/] [rel_12/] [rtl/] [verilog/] [dbg_wb.v] - Blame information for rev 86

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_wb.v                                                    ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC/OpenRISC Development Interface ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2003 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2003/12/23 15:26:26  mohor
// Small fix.
//
// Revision 1.1  2003/12/23 15:09:04  mohor
// New directory structure. New version of the debug interface.
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "dbg_wb_defines.v"
 
// Top module
module dbg_wb(
                // JTAG signals
                trst_i,     // trst_i is active high (inverted on higher layers)
                tck_i,
                tdi_i,
                tdo_o,
 
                // TAP states
                shift_dr_i,
                pause_dr_i,
                update_dr_i,
 
                wishbone_ce_i,
                crc_match_i,
                crc_en_o,
                shift_crc_o,
 
                // WISHBONE common signals
                wb_rst_i, wb_clk_i,
 
                // WISHBONE master interface
                wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,
                wb_we_o, wb_ack_i, wb_cab_o, wb_err_i, wb_cti_o, wb_bte_o
 
              );
 
// JTAG signals
input   trst_i;
input   tck_i;
input   tdi_i;
output  tdo_o;
 
// TAP states
input   shift_dr_i;
input   pause_dr_i;
input   update_dr_i;
 
input   wishbone_ce_i;
input   crc_match_i;
output  crc_en_o;
output  shift_crc_o;
 
// WISHBONE common signals
input         wb_rst_i;                   // WISHBONE reset
input         wb_clk_i;                   // WISHBONE clock
 
// WISHBONE master interface
output [31:0] wb_adr_o;
output [31:0] wb_dat_o;
input  [31:0] wb_dat_i;
output        wb_cyc_o;
output        wb_stb_o;
output  [3:0] wb_sel_o;
output        wb_we_o;
input         wb_ack_i;
output        wb_cab_o;
input         wb_err_i;
output  [2:0] wb_cti_o;
output  [1:0] wb_bte_o;
 
reg           wb_cyc_o;
reg    [31:0] wb_adr_o;
reg     [3:0] wb_sel_o;
 
reg           tdo_o;
 
reg [`WB_DR_LEN -1:0] dr;
wire enable;
reg [5:0] cnt;
reg [5:0] crc_cnt;
wire      cnt_end;
wire      crc_cnt_end;
reg       crc_cnt_end_q;
 
 
reg [`STATUS_CNT -1:0]      status_cnt;
wire status_cnt_end;
 
assign enable = wishbone_ce_i & shift_dr_i;
assign shift_crc_o = wishbone_ce_i & status_cnt_end & shift_dr_i;  // Signals dbg module to shift out the CRC
 
 
always @ (posedge tck_i)
begin
  if (enable & (~cnt_end))
    dr <= #1 {tdi_i, dr[`WB_DR_LEN -1:1]};
end
 
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    cnt <= #1 'h0;
  else if (update_dr_i)
    cnt <= #1 'h0;
  else if (enable & (~cnt_end))
    cnt <= #1 cnt + 1'b1;
end
 
assign cnt_end = cnt == `WB_DR_LEN;
 
 
// crc counter
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    crc_cnt <= #1 'h0;
  else if(enable & cnt_end & (~crc_cnt_end))
    crc_cnt <= #1 crc_cnt + 1'b1;
  else if (update_dr_i)
    crc_cnt <= #1 'h0;
end
 
assign crc_cnt_end = crc_cnt == 6'd32;
 
always @ (posedge tck_i)
begin
  crc_cnt_end_q <= #1 crc_cnt_end;
end
 
// status counter
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    status_cnt <= #1 'h0;
  else if(shift_dr_i & crc_cnt_end & (~status_cnt_end))
    status_cnt <= #1 status_cnt + 1'b1;
  else if (update_dr_i)
    status_cnt <= #1 'h0;
end
 
assign status_cnt_end = status_cnt == `STATUS_LEN;
reg [`STATUS_LEN -1:0] status;
reg address_unaligned;
 
reg wb_error, wb_error_sync, wb_error_tck;
reg wb_timeout, wb_timeout_sync, wb_timeout_tck;
 
reg busy_wb;
reg busy_tck;
reg wb_end;
reg wb_end_rst;
reg wb_end_rst_sync;
reg wb_end_sync;
reg wb_end_tck;
reg busy_sync;
reg [799:0] TDO_WISHBONE;
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    status <= #1 'h0;
  else if(crc_cnt_end & (~crc_cnt_end_q))
    begin
      if (dr[2:0] == `WB_STATUS)
        status <= #1 {crc_match_i, wb_error_tck, wb_timeout_tck, busy_tck};
      else
        status <= #1 {crc_match_i, 2'b10, address_unaligned};
    end
  else if (shift_dr_i & (~status_cnt_end))
    status <= #1 {status[0], status[`STATUS_LEN -1:1]};
end
// Following status is shifted out after each command except WB_STATUS: 
// 1. bit:          1 if crc is OK, else 0
// 2. bit:          1 if address is unaligned, else 0
// 3. bit:          always 0
// 4. bit:          always 1
 
// Following status is shifted out after WB_STATUS: 
// 1. bit:          1 if crc is OK, else 0
// 2. bit:          1 while WB access is in progress (busy_tck), else 0
// 3. bit:          1 if WB timeout occured, else 0
// 4. bit:          1 if WB error occured, else 0
 
 
always @ (crc_cnt_end or crc_cnt_end_q or crc_match_i or status or pause_dr_i or busy_tck)
begin
  if (pause_dr_i)
  begin
    tdo_o = busy_tck;
    TDO_WISHBONE = "busy_tck";
  end
  else if (crc_cnt_end & (~crc_cnt_end_q))
  begin
    tdo_o = crc_match_i;
    TDO_WISHBONE = "crc_match_i";
  end
  else
  begin
    tdo_o = status[0];
    TDO_WISHBONE = "status";
  end
end
 
assign crc_en_o = crc_cnt_end & (~status_cnt_end) & shift_dr_i;
 
reg [2:0]  cmd;
reg [31:0] adr;
reg [15:0] len;
reg start_tck;
reg start_sync1;
reg start_wb;
reg start_wb_q;
 
always @ (posedge tck_i)
begin
  if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
    begin
      cmd <= #1 dr[2:0];
      adr <= #1 dr[34:3];
      len <= #1 dr[50:35];
      start_tck <= #1 1'b1;
    end
  else
    start_tck <= #1 1'b0;
end
 
 
always @ (posedge wb_clk_i)
begin
  start_sync1 <= #1 start_tck;
  start_wb <= #1 start_sync1;
  start_wb_q <= #1 start_wb;
end
 
reg [7:0] acc_cnt;
wire acc_cnt_limit;
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    wb_cyc_o <= #1 1'b0;
  else if (start_wb & (~start_wb_q) & cmd[2])     // "read" or "go" command   igor !!! tu pride se nekaj, ki starta vse naslednje accesse
    wb_cyc_o <= #1 1'b1;
  else if (wb_ack_i | wb_err_i | acc_cnt_limit)
    wb_cyc_o <= #1 1'b0;
end
 
 
 
always @ (posedge wb_clk_i)
begin
//  if (start_wb & (~start_wb_q) & (cmd > `WB_STATUS) & (cmd < `WB_GO)) // Setting starting address
  if (start_wb & (~start_wb_q) & (cmd !== `WB_STATUS) & (cmd !== `WB_GO)) // Setting starting address
    wb_adr_o <= #1 adr;
  else if (wb_ack_i)
    begin
      if ((cmd == `WB_WRITE8) | (cmd == `WB_READ8))
        wb_adr_o <= #1 wb_adr_o + 1'd1;
      else if ((cmd == `WB_WRITE16) | (cmd == `WB_READ16))
        wb_adr_o <= #1 wb_adr_o + 2'd2;
      else
        wb_adr_o <= #1 wb_adr_o + 3'd4;
    end
end
 
 
always @ (wb_adr_o or cmd)
begin
  wb_sel_o[0] = (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b11) |
                (cmd[1:0] == 2'b10) & (wb_adr_o[1:0] == 2'b10);
  wb_sel_o[1] = (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (cmd[1] ^ cmd[0]) & (wb_adr_o[1:0] == 2'b10);
  wb_sel_o[2] = (cmd[1]) & (wb_adr_o[1:0] == 2'b00) | (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b01);
  wb_sel_o[3] = (wb_adr_o[1:0] == 2'b00);
end
//      byte  |  short  |  long
//  0   1000     1100      1111
//  1   0100     err       err
//  2   0010     0011      err
//  3   0001     err       err
 
 
always @ (dr)
begin
  address_unaligned = (dr[1:0] == 2'b11) & (dr[4:3] > 2'b00) | (dr[1:0] == 2'b10) & (dr[3]);
end
 
`define WB_STATUS     3'h0  // 000
`define WB_WRITE8     3'h1  // 001
`define WB_WRITE16    3'h2  // 010
`define WB_WRITE32    3'h3  // 011
`define WB_GO         3'h4  // 100
`define WB_READ8      3'h5  // 101
`define WB_READ16     3'h6  // 110
`define WB_READ32     3'h7  // 111
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if(wb_rst_i)
    acc_cnt<= #1 8'h0;
  else
  if(wb_ack_i | wb_err_i | acc_cnt_limit)
    acc_cnt<= #1 8'h0;
  else
  if(wb_cyc_o)
    acc_cnt<= #1 acc_cnt + 1'b1;
end
 
assign acc_cnt_limit = acc_cnt==8'hff;
 
 
assign wb_we_o = ~cmd[2];   // Status or write (for simpler logic status is allowed)
assign wb_cab_o = 1'b0;
assign wb_stb_o = wb_cyc_o;
assign wb_cti_o = 3'h0;     // always performing single access
assign wb_bte_o = 2'h0;     // always performing single access
 
reg [31:0] input_data;
 
always @ (posedge wb_clk_i)
begin
  if(wb_ack_i)
    input_data <= #1 wb_dat_i;
end
 
 
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    wb_end <= #1 1'b0;
  else if (wb_ack_i | wb_err_i | acc_cnt_limit)
    wb_end <= #1 1'b1;
  else if (wb_end_rst)
    wb_end <= #1 1'b0;
end
 
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    begin
      wb_end_sync <= #1 1'b0;
      wb_end_tck  <= #1 1'b0;
    end
  else
    begin
      wb_end_sync <= #1 wb_end;
      wb_end_tck  <= #1 wb_end_sync;
    end
end
 
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    busy_wb <= #1 1'b0;
  else if (wb_end_rst)
    busy_wb <= #1 1'b0;
  else if (wb_cyc_o)
    busy_wb <= #1 1'b1;
end
 
 
always @ (posedge tck_i or posedge trst_i)
begin
  if (trst_i)
    begin
      busy_sync <= #1 1'b0;
      busy_tck <= #1 1'b0;
    end
  else
    begin
      busy_sync <= #1 busy_wb;
      busy_tck <= #1 busy_sync;
    end
end
 
 
always @ (posedge wb_clk_i)
begin
  wb_end_rst_sync <= #1 wb_end_tck;
  wb_end_rst  <= #1 wb_end_rst_sync;
end
 
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    wb_error <= #1 1'b0;
  else if(wb_err_i)
    wb_error <= #1 1'b1;
  else if(wb_ack_i | acc_cnt_limit)
    wb_error <= #1 1'b0;
end
 
always @ (posedge tck_i)
begin
  wb_error_sync <= #1 wb_error;
  wb_error_tck  <= #1 wb_error_sync;
end
 
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    wb_timeout <= #1 1'b0;
  else if(acc_cnt_limit)
    wb_timeout <= #1 1'b1;
  else if(wb_ack_i | wb_err_i)
    wb_timeout <= #1 1'b0;
end
 
always @ (posedge tck_i)
begin
  wb_timeout_sync <= #1 wb_timeout;
  wb_timeout_tck  <= #1 wb_timeout_sync;
end
 
 
endmodule
 

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[/] [dbg_interface/] [tags/] [rel_12/] [rtl/] [verilog/] [dbg_wb.v] - Blame information for rev 86

Line No.	Rev	Author	Line
1	82	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_wb.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC/OpenRISC Development Interface ////`
7			`//// http://www.opencores.org/projects/DebugInterface/ ////`
8			`//// ////`
9			`//// Author(s): ////`
10			`//// Igor Mohor (igorm@opencores.org) ////`
11			`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the README.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 - 2003 Authors ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46	86	mohor	`// Revision 1.2 2003/12/23 15:26:26 mohor`
47			`// Small fix.`
48			`//`
49	83	mohor	`// Revision 1.1 2003/12/23 15:09:04 mohor`
50			`// New directory structure. New version of the debug interface.`
51	82	mohor	`//`
52			`//`
53	83	mohor	`//`
54	82	mohor
55			`// synopsys translate_off`
56			`include "timescale.v"
57			`// synopsys translate_on`
58			`include "dbg_wb_defines.v"
59
60			`// Top module`
61			`module dbg_wb(`
62			`// JTAG signals`
63			`trst_i, // trst_i is active high (inverted on higher layers)`
64			`tck_i,`
65			`tdi_i,`
66			`tdo_o,`
67
68			`// TAP states`
69			`shift_dr_i,`
70			`pause_dr_i,`
71			`update_dr_i,`
72
73			`wishbone_ce_i,`
74			`crc_match_i,`
75			`crc_en_o,`
76			`shift_crc_o,`
77
78			`// WISHBONE common signals`
79			`wb_rst_i, wb_clk_i,`
80
81			`// WISHBONE master interface`
82			`wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,`
83			`wb_we_o, wb_ack_i, wb_cab_o, wb_err_i, wb_cti_o, wb_bte_o`
84
85			`);`
86
87			`// JTAG signals`
88			`input trst_i;`
89			`input tck_i;`
90			`input tdi_i;`
91			`output tdo_o;`
92
93			`// TAP states`
94			`input shift_dr_i;`
95			`input pause_dr_i;`
96			`input update_dr_i;`
97
98			`input wishbone_ce_i;`
99			`input crc_match_i;`
100			`output crc_en_o;`
101			`output shift_crc_o;`
102
103			`// WISHBONE common signals`
104			`input wb_rst_i; // WISHBONE reset`
105			`input wb_clk_i; // WISHBONE clock`
106
107			`// WISHBONE master interface`
108			`output [31:0] wb_adr_o;`
109			`output [31:0] wb_dat_o;`
110			`input [31:0] wb_dat_i;`
111			`output wb_cyc_o;`
112			`output wb_stb_o;`
113			`output [3:0] wb_sel_o;`
114			`output wb_we_o;`
115			`input wb_ack_i;`
116			`output wb_cab_o;`
117			`input wb_err_i;`
118			`output [2:0] wb_cti_o;`
119			`output [1:0] wb_bte_o;`
120
121			`reg wb_cyc_o;`
122			`reg [31:0] wb_adr_o;`
123			`reg [3:0] wb_sel_o;`
124
125			`reg tdo_o;`
126
127			reg [`WB_DR_LEN -1:0] dr;
128			`wire enable;`
129			`reg [5:0] cnt;`
130			`reg [5:0] crc_cnt;`
131			`wire cnt_end;`
132			`wire crc_cnt_end;`
133			`reg crc_cnt_end_q;`
134
135
136			reg [`STATUS_CNT -1:0] status_cnt;
137			`wire status_cnt_end;`
138
139			`assign enable = wishbone_ce_i & shift_dr_i;`
140			`assign shift_crc_o = wishbone_ce_i & status_cnt_end & shift_dr_i; // Signals dbg module to shift out the CRC`
141
142
143			`always @ (posedge tck_i)`
144			`begin`
145			`if (enable & (~cnt_end))`
146			dr <= #1 {tdi_i, dr[`WB_DR_LEN -1:1]};
147			`end`
148
149
150			`always @ (posedge tck_i or posedge trst_i)`
151			`begin`
152			`if (trst_i)`
153			`cnt <= #1 'h0;`
154			`else if (update_dr_i)`
155			`cnt <= #1 'h0;`
156			`else if (enable & (~cnt_end))`
157			`cnt <= #1 cnt + 1'b1;`
158			`end`
159
160			assign cnt_end = cnt == `WB_DR_LEN;
161
162
163			`// crc counter`
164			`always @ (posedge tck_i or posedge trst_i)`
165			`begin`
166			`if (trst_i)`
167			`crc_cnt <= #1 'h0;`
168			`else if(enable & cnt_end & (~crc_cnt_end))`
169			`crc_cnt <= #1 crc_cnt + 1'b1;`
170			`else if (update_dr_i)`
171			`crc_cnt <= #1 'h0;`
172			`end`
173
174			`assign crc_cnt_end = crc_cnt == 6'd32;`
175
176			`always @ (posedge tck_i)`
177			`begin`
178			`crc_cnt_end_q <= #1 crc_cnt_end;`
179			`end`
180
181			`// status counter`
182			`always @ (posedge tck_i or posedge trst_i)`
183			`begin`
184			`if (trst_i)`
185			`status_cnt <= #1 'h0;`
186			`else if(shift_dr_i & crc_cnt_end & (~status_cnt_end))`
187			`status_cnt <= #1 status_cnt + 1'b1;`
188			`else if (update_dr_i)`
189			`status_cnt <= #1 'h0;`
190			`end`
191
192			assign status_cnt_end = status_cnt == `STATUS_LEN;
193			reg [`STATUS_LEN -1:0] status;
194			`reg address_unaligned;`
195
196			`reg wb_error, wb_error_sync, wb_error_tck;`
197			`reg wb_timeout, wb_timeout_sync, wb_timeout_tck;`
198
199	86	mohor	`reg busy_wb;`
200			`reg busy_tck;`
201			`reg wb_end;`
202			`reg wb_end_rst;`
203			`reg wb_end_rst_sync;`
204			`reg wb_end_sync;`
205			`reg wb_end_tck;`
206			`reg busy_sync;`
207			`reg [799:0] TDO_WISHBONE;`
208	82	mohor
209			`always @ (posedge tck_i or posedge trst_i)`
210			`begin`
211			`if (trst_i)`
212			`status <= #1 'h0;`
213			`else if(crc_cnt_end & (~crc_cnt_end_q))`
214			`begin`
215			if (dr[2:0] == `WB_STATUS)
216	86	mohor	`status <= #1 {crc_match_i, wb_error_tck, wb_timeout_tck, busy_tck};`
217			`else`
218	82	mohor	`status <= #1 {crc_match_i, 2'b10, address_unaligned};`
219			`end`
220			`else if (shift_dr_i & (~status_cnt_end))`
221			status <= #1 {status[0], status[`STATUS_LEN -1:1]};
222			`end`
223	86	mohor	`// Following status is shifted out after each command except WB_STATUS:`
224	82	mohor	`// 1. bit: 1 if crc is OK, else 0`
225			`// 2. bit: 1 if address is unaligned, else 0`
226			`// 3. bit: always 0`
227			`// 4. bit: always 1`
228
229	86	mohor	`// Following status is shifted out after WB_STATUS:`
230	82	mohor	`// 1. bit: 1 if crc is OK, else 0`
231	86	mohor	`// 2. bit: 1 while WB access is in progress (busy_tck), else 0`
232	82	mohor	`// 3. bit: 1 if WB timeout occured, else 0`
233			`// 4. bit: 1 if WB error occured, else 0`
234
235
236			`always @ (crc_cnt_end or crc_cnt_end_q or crc_match_i or status or pause_dr_i or busy_tck)`
237			`begin`
238			`if (pause_dr_i)`
239			`begin`
240			`tdo_o = busy_tck;`
241			`TDO_WISHBONE = "busy_tck";`
242			`end`
243			`else if (crc_cnt_end & (~crc_cnt_end_q))`
244			`begin`
245			`tdo_o = crc_match_i;`
246			`TDO_WISHBONE = "crc_match_i";`
247			`end`
248			`else`
249			`begin`
250			`tdo_o = status[0];`
251			`TDO_WISHBONE = "status";`
252			`end`
253			`end`
254
255			`assign crc_en_o = crc_cnt_end & (~status_cnt_end) & shift_dr_i;`
256
257			`reg [2:0] cmd;`
258			`reg [31:0] adr;`
259			`reg [15:0] len;`
260			`reg start_tck;`
261			`reg start_sync1;`
262			`reg start_wb;`
263			`reg start_wb_q;`
264
265			`always @ (posedge tck_i)`
266			`begin`
267			`if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)`
268			`begin`
269			`cmd <= #1 dr[2:0];`
270			`adr <= #1 dr[34:3];`
271			`len <= #1 dr[50:35];`
272			`start_tck <= #1 1'b1;`
273			`end`
274			`else`
275			`start_tck <= #1 1'b0;`
276			`end`
277
278
279			`always @ (posedge wb_clk_i)`
280			`begin`
281			`start_sync1 <= #1 start_tck;`
282			`start_wb <= #1 start_sync1;`
283			`start_wb_q <= #1 start_wb;`
284			`end`
285
286			`reg [7:0] acc_cnt;`
287			`wire acc_cnt_limit;`
288
289			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
290			`begin`
291			`if (wb_rst_i)`
292			`wb_cyc_o <= #1 1'b0;`
293			`else if (start_wb & (~start_wb_q) & cmd[2]) // "read" or "go" command igor !!! tu pride se nekaj, ki starta vse naslednje accesse`
294			`wb_cyc_o <= #1 1'b1;`
295			`else if (wb_ack_i \| wb_err_i \| acc_cnt_limit)`
296			`wb_cyc_o <= #1 1'b0;`
297			`end`
298
299
300
301			`always @ (posedge wb_clk_i)`
302			`begin`
303			// if (start_wb & (~start_wb_q) & (cmd > `WB_STATUS) & (cmd < `WB_GO)) // Setting starting address
304			if (start_wb & (~start_wb_q) & (cmd !== `WB_STATUS) & (cmd !== `WB_GO)) // Setting starting address
305			`wb_adr_o <= #1 adr;`
306			`else if (wb_ack_i)`
307			`begin`
308			if ((cmd == `WB_WRITE8) \| (cmd == `WB_READ8))
309			`wb_adr_o <= #1 wb_adr_o + 1'd1;`
310			else if ((cmd == `WB_WRITE16) \| (cmd == `WB_READ16))
311			`wb_adr_o <= #1 wb_adr_o + 2'd2;`
312			`else`
313			`wb_adr_o <= #1 wb_adr_o + 3'd4;`
314			`end`
315			`end`
316
317
318			`always @ (wb_adr_o or cmd)`
319			`begin`
320			`wb_sel_o[0] = (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) \| (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b11) \|`
321			`(cmd[1:0] == 2'b10) & (wb_adr_o[1:0] == 2'b10);`
322			`wb_sel_o[1] = (cmd[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) \| (cmd[1] ^ cmd[0]) & (wb_adr_o[1:0] == 2'b10);`
323			`wb_sel_o[2] = (cmd[1]) & (wb_adr_o[1:0] == 2'b00) \| (cmd[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b01);`
324			`wb_sel_o[3] = (wb_adr_o[1:0] == 2'b00);`
325			`end`
326			`// byte \| short \| long`
327			`// 0 1000 1100 1111`
328			`// 1 0100 err err`
329			`// 2 0010 0011 err`
330			`// 3 0001 err err`
331
332
333			`always @ (dr)`
334			`begin`
335			`address_unaligned = (dr[1:0] == 2'b11) & (dr[4:3] > 2'b00) \| (dr[1:0] == 2'b10) & (dr[3]);`
336			`end`
337
338			`define WB_STATUS 3'h0 // 000
339			`define WB_WRITE8 3'h1 // 001
340			`define WB_WRITE16 3'h2 // 010
341			`define WB_WRITE32 3'h3 // 011
342			`define WB_GO 3'h4 // 100
343			`define WB_READ8 3'h5 // 101
344			`define WB_READ16 3'h6 // 110
345			`define WB_READ32 3'h7 // 111
346
347			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
348			`begin`
349			`if(wb_rst_i)`
350			`acc_cnt<= #1 8'h0;`
351			`else`
352			`if(wb_ack_i \| wb_err_i \| acc_cnt_limit)`
353			`acc_cnt<= #1 8'h0;`
354			`else`
355			`if(wb_cyc_o)`
356			`acc_cnt<= #1 acc_cnt + 1'b1;`
357			`end`
358
359			`assign acc_cnt_limit = acc_cnt==8'hff;`
360
361
362			`assign wb_we_o = ~cmd[2]; // Status or write (for simpler logic status is allowed)`
363			`assign wb_cab_o = 1'b0;`
364			`assign wb_stb_o = wb_cyc_o;`
365			`assign wb_cti_o = 3'h0; // always performing single access`
366			`assign wb_bte_o = 2'h0; // always performing single access`
367
368	86	mohor	`reg [31:0] input_data;`
369	82	mohor
370			`always @ (posedge wb_clk_i)`
371			`begin`
372			`if(wb_ack_i)`
373	86	mohor	`input_data <= #1 wb_dat_i;`
374	82	mohor	`end`
375
376
377
378			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
379			`begin`
380			`if (wb_rst_i)`
381	86	mohor	`wb_end <= #1 1'b0;`
382			`else if (wb_ack_i \| wb_err_i \| acc_cnt_limit)`
383			`wb_end <= #1 1'b1;`
384			`else if (wb_end_rst)`
385			`wb_end <= #1 1'b0;`
386	82	mohor	`end`
387
388
389			`always @ (posedge tck_i or posedge trst_i)`
390			`begin`
391			`if (trst_i)`
392			`begin`
393	86	mohor	`wb_end_sync <= #1 1'b0;`
394			`wb_end_tck <= #1 1'b0;`
395	82	mohor	`end`
396			`else`
397			`begin`
398	86	mohor	`wb_end_sync <= #1 wb_end;`
399			`wb_end_tck <= #1 wb_end_sync;`
400	82	mohor	`end`
401			`end`
402
403
404			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
405			`begin`
406			`if (wb_rst_i)`
407			`busy_wb <= #1 1'b0;`
408	86	mohor	`else if (wb_end_rst)`
409	82	mohor	`busy_wb <= #1 1'b0;`
410			`else if (wb_cyc_o)`
411			`busy_wb <= #1 1'b1;`
412			`end`
413
414
415			`always @ (posedge tck_i or posedge trst_i)`
416			`begin`
417			`if (trst_i)`
418			`begin`
419			`busy_sync <= #1 1'b0;`
420			`busy_tck <= #1 1'b0;`
421			`end`
422			`else`
423			`begin`
424			`busy_sync <= #1 busy_wb;`
425			`busy_tck <= #1 busy_sync;`
426			`end`
427			`end`
428
429
430			`always @ (posedge wb_clk_i)`
431			`begin`
432	86	mohor	`wb_end_rst_sync <= #1 wb_end_tck;`
433			`wb_end_rst <= #1 wb_end_rst_sync;`
434	82	mohor	`end`
435
436
437			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
438			`begin`
439			`if (wb_rst_i)`
440			`wb_error <= #1 1'b0;`
441			`else if(wb_err_i)`
442			`wb_error <= #1 1'b1;`
443			`else if(wb_ack_i \| acc_cnt_limit)`
444			`wb_error <= #1 1'b0;`
445			`end`
446
447			`always @ (posedge tck_i)`
448			`begin`
449			`wb_error_sync <= #1 wb_error;`
450			`wb_error_tck <= #1 wb_error_sync;`
451			`end`
452
453
454			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
455			`begin`
456			`if (wb_rst_i)`
457			`wb_timeout <= #1 1'b0;`
458			`else if(acc_cnt_limit)`
459			`wb_timeout <= #1 1'b1;`
460			`else if(wb_ack_i \| wb_err_i)`
461			`wb_timeout <= #1 1'b0;`
462			`end`
463
464			`always @ (posedge tck_i)`
465			`begin`
466			`wb_timeout_sync <= #1 wb_timeout;`
467			`wb_timeout_tck <= #1 wb_timeout_sync;`
468			`end`
469
470
471			`endmodule`
472